A Compact Test Structure for Characterizing Transistor ... - IEEE Xplore

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 28, NO. 3, AUGUST 2015

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A Compact Test Structure for Characterizing Transistor Variability Beyond 3σ Christopher S. Chen, Member, IEEE, Liping Li, Queennie Lim, Hong Hai Teh, Member, IEEE, Noor Fadillah Binti Omar, Chun-Lee Ler, Member, IEEE, and Jeffrey T. Watt, Senior Member, IEEE

Abstract—An addressable array test structure is proposed for characterization of transistor variability beyond 3σ away from the mean. The design of the array is based on very compact basic cells which enable a highly efficient layout which has over three times higher normalized device density than similar arrays. Implementations of a 32k array are demonstrated for placement in a standard wafer scribe lane module. Characterization results based on an advanced high-k/metal gate process show that transistor threshold voltages follow a Gaussian distribution at current levels typically used in digital circuits. Analysis of random and systematic components of variability confirms that there are no systematic spatial gradients across the array and that random variations account for 99% of total variability. Index Terms—MOSFETs, measurement, variability, statistics.

(2) additional technical details on the design and measurement of our test structure, and (3) PMOS VT variability data. The remainder of the paper is organized as follows. Section II describes transistor variability characterization and expands on [9] by giving a brief survey of published work on this topic. A new figure of merit is proposed to show that our array is much more efficient in area usage compared to other published arrays. Section III describes our array test structure and expands on [9] by providing more detailed descriptions and schematics to explain the decoder circuit and its relationship to the transistor array. In Section IV, we present characterization data and discuss the nature of the measured distributions at various current levels for the PMOS transistor array. Finally, a concluding summary of our work is provided in Section V.

I. I NTRODUCTION ROCESS induced variability is an increasingly important aspect of deeply scaled semiconductor manufacturing technologies [1]–[4]. Due to the granularity of matter, devices which have identical drawn layouts can have drastically different electrical behavior caused by random variations in their physical features such as random dopant fluctuations, metal gate granularity, and line edge roughness [5]–[7]. Random variations need to be characterized so that their impact can be understood for both analog circuits which rely on precisely matched devices and for memory circuits which are often built from large numbers of repeated cells. Random variations in transistor threshold voltage (VT ) can cause large mismatch in analog circuits [2] and degrade design margins for static random access memory circuits [7], [8]. To characterize random variability, we previously proposed a novel test structure and presented NMOS VT variability data [9]. In this work, we extend upon [9] by presenting: (1) a detailed comparison between our test structure and existing structures for characterizing transistor variability,

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Manuscript received October 10, 2014; revised May 12, 2015; accepted May 25, 2015. Date of publication June 1, 2015; date of current version July 31, 2015. C. S. Chen, L. Li, Q. Lim, and J. T. Watt are with the Department of Process Technology Development, Altera Corporation, San Jose, CA 95134 USA (e-mail: [email protected]; [email protected]; [email protected]; [email protected]). H. H. Teh, N. F. B. Omar, and C.-L. Ler are with the Department of Process Technology Development, Altera Corporation, Penang 11900, Malaysia (e-mail: [email protected]; [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TSM.2015.2439275

II. T RANSISTOR VARIABILITY C HARACTERIZATION The importance of transistor variability can be attested by the abundance of publications on this topic in recent years. An excellent survey of various characterization methods is given in [10] where the author notes that most characterization approaches can be broadly classified in two general categories: (1) matched pairs and (2) array based measurements. Although [10] is primarily focused on matched pair characterization, the author notes that the single undisputable advantage of array based measurements is in their usefulness for gathering large volumes of statistical data. A. Variability and Sample Size Foundries typically create transistor variability models based on their characterization of devices up to 2σ or 3σ away from the mean. The σ values obtained for a relatively small sample size of transistors are used to create statistical models which customers use to design circuits with large numbers of repeated cells which are required to function properly for transistors which vary by 4σ to 6σ away from the mean. The small sample sizes typically used by foundries can be problematic in two ways. First, the measured results from a small sample size of transistors do not guarantee that the underlying distribution is Gaussian beyond the range of 3σ from the mean. Second, the limited sample size can only provide a point estimate (s) of the true population σ value, according to Chi-squared statistics [11], [12]. For example, given a sample of 100 transistors where s = 30 mV, we would have 95% confidence that the measured s value is within

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Fig. 2. Matched pair of transistors can be used to measure mismatch and random variations in VT .

Fig. 1. Upper (squares) and lower (circles) confidence limits for predicting σ using various sample sizes. Calculation based on chi-squared distribution using 95% confidence level for a representative value of s = 30 mV. The amount of uncertainty decreases drastically for larger sample sizes.

a range of −3.7 mV to +4.9 mV of the true population σ value (Fig. 1). Stated differently, the true population σ value could be anywhere within the range of 26.3 mV to 34.9 mV. B. Variability Characterization Methods Process technology characterization is typically based on single transistor test structures where each of the four transistor terminals is connected to a probe pad. Characterization of statistical variability typically requires a very large number of test structures which occupy large amounts of silicon area and testing resources. Three common approaches have been employed to characterize transistor variability: matched pairs, simple arrays, and addressable arrays. 1) Matched Pairs: One common approach for measuring random variability is to use matched pairs [10]. In matched pair test structures, the layout is drawn very carefully to ensure that both devices in the pair have identical layout surroundings and electrical connectivity. The threshold voltages of each device (VTa , VTb ) are measured and the VT mismatch (VT ) is calculated for each matched pair (Fig. 2) [13]–[15]. After measuring a large number of matched pairs, the random variability can be calculated using the standard deviation of the mismatch by the following equation: √ √ σ (VT ) = σ (VTa − VTb ) = 2 · σ (VT ) = AVT / WL (1) where VTa and VTb are the threshold voltages of the two devices in the matched pair, VT is the mismatch, AVT is the mismatch coefficient, W is the transistor width, and L is the transistor length. The advantage of using matched pairs is their simplicity. Although much care must be taken to ensure identical layouts of the matched devices, the measurement and analysis of matched pairs is relatively straightforward. The clearest disadvantage of this approach, however, is the difficulty of

Fig. 3. Simple array of transistors with common connections for gate, drain, source, and well [16]. Illustration shows example where T11 is the device under test.

measuring a large sample size. The probe pads alone consume a large enough area so that a typical wafer would typically contain only hundreds of matched pairs. The limitation on sample size makes it difficult to analyze random variability up to 3σ away from the mean. 2) Simple Arrays: A second approach for measuring transistor variability is to use simple arrays with shared row and column buses (Fig. 3). In this approach, the transistor bulk, source, gate, and drain pads can be shared between multiple devices. The benefit of using a simple array is the ability to increase the sample size by 10 to 100 times for a similar silicon footprint and a modest increase in the number of probe pads. When designing a simple array, care must be taken to ensure that parasitic leakages from unselected devices do not affect the measurement of the device under test (DUT). This approach was demonstrated in [16] to characterize random variability in a 65 nm technology up to 3σ away from the mean and to understand the impact of well proximity and temperature on local variations. While simple arrays have proven extremely useful for characterizing local variations up to 3σ , the size of the array is limited by parasitic effects. Thus, it is very difficult to use simple arrays to validate statistical models beyond 3σ away from the mean. 3) Addressable Arrays: A third approach for measuring variability is to use an addressable array where decoder circuits are used to select one DUT within a large array of devices [17]–[20]. Address decoder circuitry is typically placed along the periphery of the array to increase the number of testable devices for a given number of probe pads. This is by far the most complex approach, requiring longer development times to implement the addressing circuitry.

CHEN et al.: COMPACT TEST STRUCTURE FOR CHARACTERIZING TRANSISTOR VARIABILITY BEYOND 3σ

Fig. 4. Top level block diagram of addressable transistor array. In our 32k array, there are 64 rows (n = 6) and 512 columns (m = 9). The drain bias (DL) and drain Kelvin sense (DR) are connected to the selected row through the left and right decoders, respectively. The gate biases (G or GOFF) are applied to entire columns of the array through the top and bottom decoders. All unselected columns have GOFF voltage applied.

Addressable arrays are the most practical option for measuring statistics up to 4σ to 6σ away from the mean [9], [17], [19]–[24]. Recently, addressable arrays have been employed to understand deviations from the Gaussian distribution for devices beyond 3σ away from the mean [17], [22], [23]. The most significant challenges for implementing large addressable arrays are (1) parasitic leakages and (2) voltage loss due to the high series resistance of the periphery circuitry. Arrays are often designed using special features to suppress parasitic leakages of unselected devices, or to compensate for voltage loss using Kelvin methods. These features are typically implemented by adding transmission gates to the decoder or DUT basic cells – which increases design complexity and increases the total area of the test structure [4], [19]–[21], [24]–[31]. III. T EST S TRUCTURE In this work, we describe a compact addressable array which enables testing of a very large number of transistors using a small number of probe pads and standard parametric test equipment. The novelty of our array test structure is in its simple design which enables an extremely compact layout and a simple test method. The addressable array test structure consists of a large array of transistors surrounded by decoder circuits which are placed along the periphery of the array to provide individual access to each of the devices in the array (Fig. 4). The decoder circuits use a binary addressing scheme where the number of address bits corresponds to the number of rows and columns in the array. Binary addresses are generated using an off-chip parametric tester, while on-chip buffers are used to create complementary address signals. A simplified schematic of the test structure is shown in Fig. 5.

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Fig. 5. Simplified schematic of nMOS test structure showing a 2 × 2 array surrounded by address decoder circuits based on 2:1 muxes. Array transistors are core devices, while mux transistors are IO transistors. The DUT basic cell consists of only one core transistor, while the mux basic cell consists of two IO transistors. Gate biases are supplied through the top and bottom muxes, while drain force and sense utilize the left and right muxes, respectively. The column decoder is split into two halves which are placed at the top and bottom of the array. The row decoder is placed on the left side of the array, and a mirrored copy is placed at the right side to facilitate a Kelvin connection to the selected row. Illustration shows addressing of device at row 0 and column 0.

Fig. 6. Layout of 32k transistor array and decoders. Area of DUT array is 94 × 23 um. Portions of two probe pads are visible at the far left and far right. A third probe pad which covers ∼30% of the array area is barely visible near the center of the array.

We present results from our 32k array developed using an advanced high-k/metal gate technology with supply voltages of 0.9V (core) and 1.8V (IO). Due to its compact design, the 32k transistor array can fit within an ordinary wafer scribe lane module (Fig. 6). Core transistors are laid out in an array of 64 rows and 512 columns such that an individual DUT can be accessed through a 15 bit addressing scheme. The core transistors in the array are identical in device type and drawn dimensions and share common source and bulk connections. One array was drawn using 32k NMOS transistors, while a second array was drawn using 32k PMOS transistors. Each row has one common drain connection which is accessed simultaneously through the left and right decoders, while each column has one common gate connection which is accessed through either the top decoder (for even columns) or bottom decoder (for odd columns). A. Address Decoder Design The row and column decoder circuits are built from 2:1 muxes constructed of IO pass gates which can sustain a higher voltage than the core devices. The decoding circuit uses a very compact basic cell consisting of only two IO

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NMOS pass gates for the NMOS array (Fig. 5) or two IO PMOS pass gates for the PMOS array (not shown). B. Drain and Gate Connections A common gate connection is shared by all devices in the same column, while a common drain connection is shared by devices in the same row. The array is designed such that the DUT is located at the intersection of the selected row and column. To suppress the drain leakage of unselected devices in the same row as the DUT, a negative gate bias (GOFF) is applied to all unselected columns. To minimize parasitic leakage through the mux transistors, GOFF must be kept sufficiently close to ground. Otherwise, a large parasitic current can flow from G to GOFF, causing a voltage drop on the gate lines which reduces the voltage seen at the DUT and artificially increases the measured VT . The drain bias (DL) is supplied from the left mux and a Kelvin connection (DR) senses the voltage at the DUT drain through the right mux. At high drain current levels, the series resistance of the decoder and interconnect can cause the voltage at DR to be significantly lower than the bias supplied at DL. To compensate for drain voltage loss due to series resistances, the biases at DL and VDD can be increased so that the desired voltage is attained at the DUT drain.

Fig. 7. Comparison of device density figure of merit (FOM) for various transistor arrays where authors published the total test structure area. The FOM is normalized to remove the improvements in density due to geometrical scaling. The FOM shows that our 32k transistor array has over three times higher packing density than similar arrays. Number of metal layers is shown for arrays where authors published this information.

on-chip address generators and op amps can increase area significantly [17], [28], [30], [32], [33]. D. Number of Metal Layers

C. Device Density Our compact array structure can be compared to similar arrays using a density figure of merit (FOM). Our FOM quantifies the number of addressable devices per unit area of the array and addressing circuit. To make a fair comparison across technology nodes, the FOM is normalized to exclude density improvements due to technology scaling. The FOM is calculated based on the total test structure area, not including the probe pads. As shown in Fig. 7, our array has over three times higher packing density than similar arrays where the total test structure area was published. The improvements in density are due to several reasons. First, our DUT basic cell contains only one transistor, while many arrays add transmission gates to the DUT basic cell [19], [24]–[26]. Second, our decoder cell uses only two IO transistors to implement our 2:1 decoding scheme, while many other arrays use combinations of CMOS pass gates and NAND gates in the decoder basic cell [4], [19], [26], [28]–[31]. Third, we implement our G and GOFF connections in a single mux, while most other approaches require extra transmission gates to apply a negative voltage to unselected gates [4], [20], [21], [26], [27]. A fourth reason for area efficiency is that our drain Kelvin connection does not require a larger DUT basic cell. While some arrays use extra transmission gates within the DUT basic cell to implement Kelvin sensing, our approach doubles the area of the row decoder without changing the DUT basic cell [24], [29]. Finally, our array does not require extra circuitry for on-chip measurements. While on-chip measurement circuitry can offer significant benefits in testing throughput, the addition of

Our compact array structure was designed using 9 metal layers to achieve 1 resistance on the common source node to minimize ohmic voltage loss during measurements at high current levels. The number of metal layers could be reduced to 6 layers for a design of our array which is intended only for measuring variability at low current levels. In a 6 layer design, resistance on the source would be sufficiently low to measure variability of constant current threshold voltage (as described in Section IV). The number of metal layers in our design is consistent with similar arrays which utilized two [27], four [30], five [21], seven [29], and ten [19] layers (Fig. 7). Our design could be adapted to use fewer layers by sacrificing area or restricting usage to low current regimes. E. Test Methods The transistor array can be tested using an industry standard Agilent 4072A parametric tester. Binary addresses are generated using a source monitor unit and ground unit to supply high and low address signals. Constant current threshold voltage can be measured at low current values where parasitic series resistances can be neglected. At higher current values, series resistance is mitigated by sensing the voltage at the DUT drain through the right mux, and compensating for the voltage loss by increasing the voltages at DL or VDD. Using a binary search routine, threshold voltage can be measured with +/− 1mV accuracy across the entire 32k array in 100 minutes (180 msec per DUT) using medium integration time to average out noise from 60 Hz AC power lines. Kelvin-compensated drain current can be measured across the


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Fig. 8. Normal quantile plots of constant current VT values measured on a 32k pMOS array. Constant current threshold voltage was measured at various current levels. (a) 46 nA, (b) 92 nA, (c) 138 nA, (d) 230 nA, (e) 322 nA, and (f) 460 nA. A slight tail at low absolute voltage is observed in cases (a)–(c). The horizontal axis is voltage and the two vertical axes are the probability and the number of standard deviations.

entire 32k array in 25 minutes (46 msec per DUT) using short integration time.

TABLE I pMOS V T R ESULTS AT VARIOUS TARGET C URRENT L EVELS

IV. T RANSISTOR VARIABILITY DATA The 32k transistor array was utilized for characterization of threshold voltage up to 4σ away from the mean. By characterizing the entire 32k array, the population σ can be estimated with 95% confidence to be within +/−0.2 mV of the measured s value, for a Gaussian distribution with s = 32 mV. A. Distributions of pMOS VT at Various Current Levels The constant current method was employed to measure the threshold voltage at VDS = 50 mV for all 32k devices in the array. The PMOS array was measured at varying current levels and the distributions are plotted in Fig. 8. For current levels up to 138 nA, the measured data follows a Gaussian distribution, with a slight tail at low absolute gate voltages [Fig. 8(a)–(c)]. This tail diminishes at higher current levels [Table I, Fig. 8(d)–(f)]. Our results are consistent with previous reports of distribution tails at low current levels which were attributed to percolation paths across the channel caused by random dopant fluctuations [17], [22], [23]. Although percolation dominates

at low current levels, it is expected that for higher current levels used in digital circuits, the measured data would follow a Gaussian distribution.

B. Variance Due to Test Method The aforementioned +/− 1 mV accuracy of our binary search test method can be modeled as a uniformly distributed independent random variable with a 2 mV range, whose variance is given by: Var(Test method) =

(2mV)2 (b − a)2 = = 0.33mV 2 12 12

(2)

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Fig. 9. Contour plots of measured threshold voltages of 32k pMOS transistors. Contours show no systematic spatial variations near decoders or beneath probe pads. (a) Raw VT data. (b) VT data after smoothing with eight nearest neighbors.

where (b − a) denotes the range of the uniform distribution [35]. Thus, the total measured variance (s2 ) can be analyzed as the sum of variances of the test method and the DUT: s2 = Var(Total) = Var(Test method) + Var(DUT) (3) (32 mV)2 = 1024 mV 2 = 0.33 mV 2 + Var(DUT)

(4)

Based on this analysis, the variance contributed by the test method (0.33mV2 ) is negligible compared to the total measured variance (1024mV2 ) and the total variance can be entirely attributed to the DUT. Thus, although the underlying test methodology has a +/− 1 mV accuracy, the measured s value still provides a very accurate estimate of the population σ . C. Systematic and Random Variations The measured data can also be used to analyze systematic or spatial variations across the array. One basic approach to visualize spatial variations is to plot two-dimensional contour plots using the raw data [Fig. 9(a)] and smoothed data where each data point was averaged with its eight nearest neighbors [Fig. 9(b)]. A visual inspection of the contour plots shows no spatial variations across the array, including the center portion of the array which lies underneath a probe pad. Contrary to previous reports, our data suggests that the impact of probing pressure is either negligible or is overshadowed by random variation due to small device sizes [36]. While contour plots are helpful for visualizing spatial effects, it is also helpful to quantify spatial variations by analyzing the data by columns and rows. The mean of each row (or column) is calculated and compared to the population average to confirm that the row (or column) averages match the expected values based on the entire array population data. With the exception of one column, each row and column average was within the expected confidence intervals for the given sample sizes (Fig. 10). Systematic variation (σsystematic ) can also be calculated using the sum of variances approach employed in [4] using the total variation (σtotal ) and random variation (σrandom ): 2 2 2 σtotal = σsystematic + σrandom 2 2 − σrandom σsystematic = σtotal

(5) (6)

Fig. 10. Row and column averages for a 32k pMOS array. Solid symbols denote measured mean values for each row or column; dashed lines represent varying confidence intervals placed around the measured average for the entire 32k array.

TABLE II VARIATION C OMPONENTS FOR pMOS V T

Total variation is calculated from the overall population data, while random variation is calculated using measured mismatch values according to (1). Matched pairs were generated using three different methods: • Neighboring devices: mismatch between DUTs in adjacent columns of the same row • Center row reference: mismatch between DUTs in a given row compared to the DUT in the same column in the center row • Center column reference: mismatch between DUTs in a given column compared to the DUT in the same row in the center column Similar results were obtained for each of these three cases, which confirm that mismatch does not vary with location. Statistical analysis of the PMOS data shows that systematic variations account for less than 1% of total variation, while random variations account for over 99% of total variation (Table II).


D. Distribution of nMOS VT Similar to the PMOS data, the distribution for the 32k NMOS array follows a Gaussian distribution for current levels in the range of a few hundred nano-Amperes. Details of the NMOS results were previously published in [9]. Compared to the PMOS data, the NMOS data shows smaller total variation due to the larger drawn dimensions used in our NMOS devices. Analysis of systematic and random effects yielded similar results for the NMOS transistors as was described in the previous section on PMOS transistors [9]. V. C ONCLUSION A compact array test structure was designed to enable characterization of very large numbers of transistors in wafer scribe lanes using standard parametric test equipment. The use of simple 2:1 multiplexers in the decoder circuitry allows for a very compact layout, consisting of only one transistor per basic cell, within the DUT array. Measured data on our 32k transistor arrays showed that random variations in transistor threshold voltage followed the expected normal distribution up to 4σ away from the mean. ACKNOWLEDGMENT C. S. Chen would like to thank Dr. K. Terada for discussions related to transistor variability and A. Kordesch and Dr. Y. Xu for providing feedback on this paper. R EFERENCES [1] M. Pelgrom, A. Duinmaijer, and A. Welbers, “Matching properties of MOS transistors,” IEEE J. Solid-State Circuits, vol. 24, no. 5, pp. 1433–1440, Oct. 1989. [2] P. G. Drennan and C. C. McAndrew, “Understanding MOSFET mismatch for analog design,” IEEE J. Solid-State Circuits, vol. 38, no. 3, pp. 450–456, Mar. 2003. [3] H. Tuinhout, N. Wils, and P. Adricciola, “Parametric mismatch characterization for mixed-signal technologies,” IEEE J. Solid-State Circuits, vol. 45, no. 9, pp. 1687–1696, Sep. 2010. [4] K. J. Kuhn et al., “Process technology variation,” IEEE Trans. Electron. Devices, vol. 58, no. 8, pp. 2197–2208, Aug. 2011. [5] X. Wang et al., “Statistical threshold-voltage variability in scaled decananometer bulk HKMG MOSFETs: A full-scale 3-D simulation scaling study,” IEEE Trans. Electron. Devices, vol. 58, no. 8, pp. 2293–2301, Aug. 2011. [6] X. Zhang et al., “Theory and experiments of the impact of work-function variability on threshold voltage variability in MOS devices,” IEEE Trans. Electron. Devices, vol. 59, no. 11, pp. 3124–3126, Nov. 2012. [7] T. Hiramoto et al., “Direct measurement of correlation between SRAM noise margin and individual cell transistor variability using device matrix array,” IEEE Trans. Electron. Devices, vol. 58, no. 8, pp. 2249–2256, Aug. 2011. [8] Y. Z. Xu, L. S. Liu, M. Chan, and J. T. Watt, “Process variation impact on FPGA configuration memory,” in Proc. IEEE ISQED, San Jose, CA, USA, 2009, pp. 613–616. [9] C. S. Chen et al., “A compact array for characterizing 32k transistors in wafer scribe lanes,” in Proc. IEEE ICMTS, Udine, Italy, 2014, pp. 227–232. [10] H. P. Tuinhout, “Electrical characterization of matched pairs for evaluation of integrated circuit technologies,” Ph.D. dissertation, Dept. Math. Comput. Sci., Delft Univ. Technol., Delft, The Netherlands, 2005. [11] H. Schmid and A. Huber, “Measuring a small number of samples and the 3σ fallacy,” IEEE Solid-State Circuits Mag., vol. 6, no. 2, pp. 52–58, Aug. 2014. [12] J. L. Devore, Probability and Statistics for Engineering and the Sciences, 8th ed. Boston, MA, USA: Brooks/Cole, 2012, p. 295.

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Christopher S. Chen (M’11) received the B.S. degree in electrical engineering and computer sciences from the University of California, Berkeley, in 2004 and the M.S. degree in electrical engineering from the University of California, Los Angeles, in 2006. Since 2006, he has been a Device Engineer with Altera Corporation, San Jose, CA, USA, where he has developed test structures and characterization methods to validate SPICE models for five generations of process technology. He has authored over ten publications and one pending patent related to device and circuit characterization.

Liping Li received the Ph.D. degree in physics from the University of Science and Technology of China, China, in 1991. In 1995, he joined Altera Corporation for semiconductor device characterization and SPICE model extraction and validation. His current interests are on the effects of layout, statistical, and reliability modeling of very deep submicrometer transistors.

Queennie Lim received the B.S. degree in microelectronics engineering from Universiti Kebangsaan Malaysia, in 2004 and the M.S. degree in science (majoring in microelectronics engineering) from Universiti Kebangsaan Malaysia, in 2005. From 2005 to 2006, she was a Device Modeling Engineer with Silterra (M) Sdn Bhd, Kulim, Malaysia. Since 2006, she has been a Device Engineer with Altera Corporation, Penang, Malaysia, and San Jose, CA. Her responsibilities include developing test structures and test circuits for device and process monitoring and validation.

Hong Hai Teh (M’13) received the B.S. degree in electrical engineering from the University Science of Malaysia, Penang, in 2009. Since 2009, he has been a Device Engineer with Altera Corporation, Bayan Lepas Technoplex, Penang, where he has drawn layout of test structures and developed test automation methods to validate SPICE models for over three generations of process technology.

Noor Fadillah Binti Omar was born in Sarawak, Malaysia, in 1984. She received the B.S. degree in electronic engineering and the M.S. degree in system design electronic from the University of Science, Malaysia, in 2007 and 2014, respectively. From 2007 to 2011, she was a Circuit Design Engineer specialized in microprocessor design with Intel Penang Design Centre. Since 2011, she has been a Device Engineer with Altera Corporation, Penang, where she has been working on test chips layouts and test programs improvements.

Chun-Lee Ler (S’05–M’08) was born in Johor, Malaysia, in 1981. He received the B.S. and Ph.D. degrees in electronics engineering from the University of Technology Malaysia, Johor, Malaysia, in 2005 and 2009, respectively. From 2005 to 2010, he was a Device Modeling Engineer with the Design Technology Department, Silterra Malaysia, Kulim, Malaysia. In 2010, he joined Altera Corporation, Penang, Malaysia, in 2010, where he is currently a Technical Staff Member with the Technology Department. His research interests include CMOS analog and RFIC design, device modeling, and characterization.

Jeffrey T. Watt (SM’01) received the B.S. degree from Queen’s University, Kingston, Canada, and the Ph.D. degree from Stanford University, both in electrical engineering. He was a Device Engineering Manager with Cypress Semiconductor where he led the development of transistor processes from 0.65 um to 90 nm technology nodes. He is currently a fellow with the Technology Department, Altera Corporation, San Jose, CA, USA, where he oversees development of compact models and onchip ESD protection solutions. He is a member of the Altera CTO Office, responsible for assessment and research of new process technologies. He has led the delivery of models and ESD solutions at Altera for six generations of process technology from 90 to 14 nm. He has driven the development and introduction of key new capabilities in the areas of statistical simulation, aging simulation, RF models, and test structures for model validation. He holds 50 U.S. patents in the areas of CMOS processing, device structures, circuits, and ESD protection. He has served on the Technical Program Committee of the VLSI Technology Symposium and the International Conference on Simulation of Semiconductor Processes and Devices. He was the Chairman of the Santa Clara Valley Chapter of the Electron Devices Society.