A Novel Self-Error Correction Pulse Width Modulator For A Class D ...

A Novel Self-Error Correction Pulse Width Modlulator for a Class D Amplifier for Hearing Instruments M.T. Tan, J.S. Chang, Z.H. Cheng and Y.C. Tong School of Electrical and Electronic Engineering Nanyang Technological University Singapore 639798

Abstract In this paper, we propose a novel self-error correction Pulse Width Modulator for a Class D amplifier for hearing aid applications. The self-error correction mechanisms based on Master-Slave architecture is realized by simple digital circuits and can be easily fabricated in a low cost digital CMOS process. The circuit consumes 24.6 FA from a 2.5V supply. Measurements on the prototype IC shows that the error at zero-input 50% duty cycle is less than 2% and the total harmonic distortion is 3.3%.

1.

Introduction

our architecture features a unique switching methodology that interchanges the functionality of the Master and Slave circuits, without disrupting the continuous operation of the amplifier. This PWM circuit further features a lower extemal component count by incorporating the input ac coupling capacitor on-chip and a more ideal carrier waveform generator (triangular waveform). In addition, due to its self-error correction, it does not require postfabrication trimming osr calibration. This self-error mechanism is realized b,y a simple digital circuit, allowing the entire Class D amplifier to be easily realized using a low-cost digital CMOS process (as opposed to BiCMOS).

In portable micropower low-voltage electro-acoustical instruments including auditory prostheses [ I ] and hearing instruments (hearing aids) [2-81, the Class D amplifier is often used as the final power amplifier. This is because Class D amplifiers feature high efficiency (typically >SO% over a large range of modulation indices (equivalent to signal swing)) [SI, low distortion comparable to Class A amplifiers [9] and is well suited for low voltage operation. The Class D amplifier as depicted in Figure 1 comprises a Pulse Width Modulation (PWM) circuit and a bridge output stage. Several Class D amplifiers have recently been reported in literature [3-61. The simplest and lowest power method for realizing the comparator in the PWM circuit would be a digital inverter [3]; the inverter is well-suited due to its high slew rate and current drive [lo]. In this comparator circuit, the input signal and carrier are summed and connected to the input terminal - the inverter compares this summed signal with its inherent threshold voltage (ideally % V,,>. However, as this inherent threshold voltage is process and temperature dependent, the zero-input duty cycle deviates from the ideal 50%. This results in a large dc bias current which in turn dissipates high power at the bridge output. Solutions to circumvent this problem include employing expensive post-fabrication trimming [3], a complex and slower (switching speed) differential-input comparator in a BiCMOS process (more expensive process) [4], and a complex differential approach [5,6]. In this paper, we propose a novel self-error correction PWM circuit based on a Master-Slave architecture. Master-Slave architectures are routinely used in continuous-time filters but their application to an amplifier design is novel. The novel PWM circuit design also includes an Adaptive Oscillator, a Dynamic Bias Circuit and a Digital Self-Error Correction Circuit. In each MastedSlave circuit, we employ the simple digital inverter as the comparator. To reduce the effect of component mismatch between the Master and Slave circuits,

0-7803-4455-3/98/$10.00 0 1998 IEEE

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Class D Output Stage

Figure 1 Block diagraim of a full-bridge output Class D power amplifier. The proposed Class D amplifier embodying the novel selferror correction Master-Slave PWM circuit and an output stage is fabricated using a 1.2 pm CMOS process. The prototype ICs met all design specifications, and is suitable for low voltage micropower applications including hearing instruments.

2. A Novel Self-Error Correction Pulse Width Modulator The Class D amplifier as depicted in Figure 1 comprises a PWM circuit and a fulll-bridge output stage. It can be shown [SI that the PWhA circuit dictates the output static bias current (ideally zero) and several other parameters including harmonic distortion, etc. The PWM circuit generates a PWM signal whose pulse width is proportional to the instantaneous value of the input signal. The output stage, on the other hand, dictates the power efficiency. The block diagram of the proposed PWM circuit is depicted in Figure 2. There are four functional blocks in the PWM circuit, namely (a) Master and Slave Circuits, (b) Bias Circuit, ( c ) Adaptive Oscillator, and (d) Error Detection and Correction Logic (EDCL).

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However, this matching requirement is not achievable with the current fabrication technology.

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Figure 2 Block diagram of the novel self-error correction

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PWM circuit.

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The Master circuit monitors the duty cycle of the zero-input PWM signal, whereas the Slave circuit is the actual processing circuit that generates the PWM signal. The Master comprising a Triangular Waveform Generator and a Comparator, is identical to the Slave except that its input is grounded while the input to the Slave is connected to the input signal, v,.

Slave

Figure 3 Schematic diagram of the Master and Slave circuits.

The comparator of the PWM circuit is a simple CMOS inverter whose inherent threshold voltage, VTHC, is process and temperature dependent, The EDCL is used to monitor the duty cycle of the PWM signal of the Master. Should thc zero-input duty cycle of the Master deviate from the ideal 50%, the EDCL will generate the control signals to modify the duty cycle of the Adaptive Oscillator to bias the dc level of the carrier to V,,,. The Adaptive Oscillator controls the charging and discharging cycles of the carrier in the Master and Slave circuits. The Adaptive Oscillator also generates the timing signals for the EDCL. The bias currents to all the functional blocks are biased by a Dynamic Bias Circuit. The self-error correction is achieved through an overall PWM circuit feedback mechanism and operates like a DC feedback loop. The details of the individual circuit blocks shall now be described.

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2.1 Proposed Master and Slave Circuits The schematic diagram of the novel Master/Slave PWM circuit is depicted in Figure 3. The carrier triangular waveform of the Master (Slave) circuit are generated by charging/discharging capacitor C (Cm) with constant current sources MP6' and MN6' (MP6 and MN6). The comparator of the Master (Slave) comprises MP8' and MN8' (MP8 and MN8). The remaining three inverters provide added drive. In these circuits, we can show [7] that due to the high output impedance (-1 OOMSZ) of the current sources, the matching accuracy of the current sources needs to be better than 0.02% to achieve a duty cycle error of less than 2% between the Master and Slave circuits; a 2% duty cycle error will result in a dc output bias current of -1OOpA ( V D ~ 3 V ) .

To alleviate the matching requirements, we propose a novel switching scheme to periodically interchange the functional roles of the Master and Slave circuits. This switching sequence is performed by 2 identical sets of four switches in the Master and Slave circuits, and controlled by qA - qD; refer to Figure 4. Based on computer

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simulations, by employing the proposed periodic role switching between the Master and Slave, a 1% mismatch between the Master and Slave would yield a duty cycle error of 1%; or equivalent to -50pA output dc bias current ( VDF~V). Hence, the high matching requirement is greatly reduced. This switching sequence also does not interrupt the operation of the entire circuit and is applicable to other circuit designs based on the Master-Slave architectures to reduce the matching requirements.

The horizontal line in the nin' circuit is not equal to Vn,. waveform is the threshold voltage, VTHC.The waveforms depicted in thin lines are the waveforms at the various nodes of the PWM should the EDCL be absent, whereas the waveform in bold lines are the waveforms at the various nodes when the I3DCL is functioning. In the latter case, the dc level of the carrier is self-adjusted to VTHC.

2.2 Adaptive Oscillator The schematic diagram of the proposed Adaptive Oscillator is depicted in Figure 5. It generates digital pulses to control the charging and discharging duty cycles of the Master and Slave circuits, and provides a time reference for the EDCL. bias-p

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Figure 6 A logic schernatic of the Error Detection and

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Correction Logic (EDCL). osc-in

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Figure 5 Schematic diagram of the Adaptive Oscillator. The oscillator utilizes the hysteresis of a Schmitt trigger [ 1 11 to realize oscillation. The duty cycle of the output can be easily varied by changing the charging or discharging rate of capacitor Cos, by means of the four input signals ctnl, ctn2, ctpl and ctp2 (from the EDCL). The three clock signals generated by the Adaptive Oscillator are then fed back to the EDCL. The duty cycle of the Adaptive Oscillator is made adaptive through the overall feedback mechanism between the EDCL, Adaptive Oscillator and Master Circuit; see Figure 1.

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2.3 Error Detection and Correction Logic (EDCL) The schematic diagram of the EDCL is depicted in Figure 6. Four input signals are monitored by the EDCL. The primary input signal is the PWM signal, out' from the Master circuit. The other three input signals, cp, cpl and Q, from the adaptive oscillator are used as reference signals to monitor the duty cycle of signal out'. Should there be any voltage difference between the dc level of the carrier triangular waveform and the threshold voltage VTHc, the zero-input duty cycle of signal out' will deviate from the ideal 50 %. The EDCL will detect this error based on the timing information from the four input signals and generate the necessary control signal (ctpl, ctp2, ctnl or ctn2) to dynamically adjust the duty cycle of the Adaptive Oscillator. Since the Slave has similar circuit elements as the Master, any correction to the Master would similarly apply to the Slave. Figure 7 shows a case example of how the EDCL dynamically adjusts the Adaptive Oscillator to achieve selferror correction when the carrier's dc level of the Master

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Figure 7 Waveforms at pertinent nodes showing how the Error Detection and Correction Logic works.

2.4 Dynamic Bias Circuit The schematic diagram of the Dynamic Bias Circuit is depicted in Figure 8. This circuit dynamically self-adjusts the dc bias of the carrier to the threshold voltage of the comparator. To dynamically self-adjust the bias circuit, an inverter comparator (identical to the Master and Slave) is used to monitor V&. To provide a means of monitoring the dc level of the carrier, a PMOS and an NMOS current sources (MPB4 and MNB4) of this bias circuit have their drain terminals tied together. Should there be any voltage difference between the dc level at node mpt and VTHC,this error voltage will be amplified by the comparator and fed back to node B to dynamically adjust the biasing of node mpt such that the error voltage is reduced (ideally to zero). In this manner, the dc level of the carrier will be approximately the same as VTHC,

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resulting in a reduced error correction from the self-error correction mechanism.

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This results therefore verifies the proposed PWM circuit for a micropower low-voltage Class D amplifier realization.

Current Sources

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We note that the results based on computer simulations agree well with the measurements on the prototype ICs, and meet all design specifications. The circuit draws 24.6 pA from a 2.5V power supply. The total harmonic distortion is 3.3%. Through the self-error correction mechanisms, the error at zero-input 50% duty cycle is 2%. This is achieved without any post fabrication trimming.

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Parameters ( VDe2.5V)

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Design Specifications 40 kHz

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Results Simulation I Measurement 40 kHz

Conclusion

We have presented a novel self-error correction pulse width modulator based on Master-Slave architecture. The novel PWM also includes an Adaptive Oscillator, a Dynamic Bias Circuit and a Digital Self-Error Correction Circuit. The PWM circuit can be realized in a low-cost digital CMOS process. The prototype IC met all design specifications, and is suitable for micropower low-voltage applications including hearing instruments.

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References

Y.C. Tong et al., “Two-component hearing sensations produced by two-electrode stimulation in the cochlea,” Science, 219, pp 993-994, 1983. J.S. Chang and Y.C. Tong, “A low-power timemultiplexed switched capacitor speech spectrum analyser,” IEEE J. Solid-state Circuits, ” 28, pp 40-48, 1993. M.C. Killion and G. Village, “Class D hearing aid amplifier,” US Patentfio. 4,689,819, 1987. I-1.A. Gurcan, “Class D BiCMQS hearing aid output amp,” US Patent No. 5,247,581, 1993. F. Callias et al., “A set of four IC’s CMOS technology for a programmable hearing aid,” IEEE J. Solid-state Circuits, 24, pp 301-312, 1989. J.F. Duque-Carrillo et al., “VERDI: An acoustically progr. & adjustable CMOS mixed-mode signal Proc. for hearing aid appl.,” IEEE J. Solid-state Circuits, 3 I , pp 634-645, 1996. Z.H. Cheng, “Analysis and design of a micropower low voltage Class D audio amplifier,” A4.Eng Thesis, Nanyang Technological University, Singapore, 1995. M.T. Tan et al., “Analysis and two proposed design methodologies for optimizing power efficiency of a Class D amp output stage,” to appear in IEEE Int. Symp. Circuits and Systems, 1998. 191 B. Attwood. “Desinn Darameters imDortant for the optimization of ve;)-&gh-fidelity PWM (Class D) audio amp,” J. Audio Eng. Soc., 31, pp 842-853, 1983. [ 101E.A. Vittoz, “Dynamic analog techniques,” in Design

of analog-digital VLSI circuits for telecom. and signal processing, Edit. Franca J. and Tsividis Y., Prentice 11311, pp 97-124, 1994.

[l 11 M. Filanovsky and H. Bakes, “CMOS schmitt trigger design,” IEEE Trans. Circuits Syst.-1:Fundamental Theory and Appl., 4 1, pp 46-49, 1994.

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