BSIM Model for Circuit Design Using Advanced Technologies. Chenming Hu, Fellow, IEEE. Dept. of EECS, University of Califomia at Berkeley, CA 94720, USA.
1-3(Invited) BSIM Model for Circuit Design Using Advanced Technologies Chenming Hu, Fellow, IEEE Dept. of EECS, University of Califomia at Berkeley, CA 94720, USA
Abstract BSIM (Berkeley Short-channel IGFET Model) enables circuit designers to accurately simulate CMOS circuits by including gate tunneling, quantum effect, and RF effects. BPTM(Berkeley Predictive Technology Model) provides circuit designers with customized model cards for future technologies for exploratory circuit design and research. Introduction A compact model is basically a set of equations that express the MOSFET DC currents and charges (capacitances) as functions of the terminal voltages. It would take about 20 pages to print out the BSIM equations. SPICE simulators such as HSPICE and SPECTRE use BSlM directly. Fast simulators such as TIMEMILL and STARSIM may use BSlM to generate tables for speedier simulations. Cell libraries and IP blocks are in tum designed by using the simulators. Accuracy of the compact model directly affects circuit/chip designs. BSIM3/4 may be freely downloaded[l]. The EIA Compact Model Council[2] supports BSIM3/4 as the standard MOSFET model for circuit simulation. Source-Drain Current Vt dependence on channel length/width and drainhody voltages are carefully modeled[3]. The sourcedrain current model starts with accurate experimental characterization and modeling of the channel charge as function of Vg as shown in Fig.1 [4]. Carrier mobility[5] and velocity saturation need to be accurately modeled to obtain Vdsat and Idsat[6]. Analog circuit simulation requires accurate modeling of the output resistance in the saturation region. Original research [7] revealed that channel length modulation and possibly impact ionization are present, but the peak Rout is determined by drain-induced barrier lowering as shown in Fig. 2. One set of model parameters can predict the current over a wide range of channel length. The elimination of binning is a significant accomplishment. Substrate Current Impact ionization current is modeled with a linear relationship between the peak channel field and VdVdsat[8]. Gate-Induced Drain current is also modeled. Tunneling Gate Current and Its Partition Accurate gate tunneling current modeling for power and performance simulations requires the consideration of electron tunneling, hole tunneling, and electron tunneling from valence band to conduction band as shown in Fig.3. Ig increases by one decade for every 0.15nm decrease in Tox as shown in Fig. 4 [8,9]. Effects of Vds on Ig and the partition of Ig between the drain and the source currents are also modeled[9]. The tunneling current between the gate and the body is particularly important to the modeling of floating-body SO1 devices [lo]. Quantum Mechanical Charge (Capacitance) Model The Schrodinger equation is solved to find the finite thickness of the inversion/accumulation layer. The result is captured with a universal function of (Vg+bVt)/Tox (shown in Fig. 5 ) to accurately model IV and the gate '
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(channel) charge, Qg, as a function of the terminal voltages [ll]. Partitioning Qg between Qd and Qs allows the calculation of the capacitive gate, drain and source currents (dQg/dt, dQd/dt and dQs/dt), which are added to the DC currents. For illustration purpose, CV curves are plotted in Fig. 6 to show the importance of including the quantum effect in the CV model of thin oxide devices. Intrinsic Input Resistance Model for RF/High-Speed Traditionally MOSFET compact models were inaccurate at RF frequencies. BSIM4[ 13 corrected this shortcoming so that RF circuits can now be. simulated using the same model and simulator as digital and other analog circuits. The key is to correctly model the reduction in the intemal vGsdue to the flow of (capacitive) i, through the resistive MOSFET channel. This voltage drop is modeled with the Intrinsic Input Resistance connected in series with the gate. Rii is a predictable function of L, Vgs and Vds[l2]. With 10% simulation-time premium, the model is accurate up to the transistor cutoff frequency (see Fig. 7) and accounts for the nonquasistatic effect[l3]. A substrate network also contributes to the RF model accuracy. Holistic Thermal Noise and Unified Flicker Noise Models BSIM4 filled another gaping hole with the new holistic thermal noise model that accounts for the channel noise with amplification by the front and back gates and the gate-induced current noise and their partial correlation. Excellent agreement with data is found (Fig. 8). R,, is noiseless. The I/f noise model unifies the number fluctuation and the mobility fluctuation hypotheses[ 141. One-Minute Model Cards for Advanced Technologies Berkeley Predictive Technology Model (BPTM) provides circuit design researchers with advanced In minutes, designers can technologies[ 15](Fig. 9). download BSIM model cards[l6] and start doing exploratory circuit design. Users may specify the technology node, Vt, Tox, Leddown to 30nm), and R,, or use the default values. Basic interconnect resistance, capacitance and inductance models are also provided. Acknowledgement: This work was supported by SRC, EIA Compact Model Council, TI, Conexant, IBM, Xilinx, Mentor, MICRO. All coauthors of the referenced papers are acknowledged. References: U1 e v i c e . z e c s . b z r l d ~ ~ ~ ~ ~ ~;Y.Cheng, ; - " ~ s ~ tC.Hu, r ~ ? ~ "MOSFET Modeling and BSIM3User's Guide", Kluwer Academic Pub. 1999. [2] hna:~li\~~~w.ei~ouu.orr:cmd [3] Z.H.Liu, et al, IEEE Tran. Electron Devices, p.86,1993. [4] Y. Cheng et al, IEEE Trans. CAD of Ics and Systems, p.641,1998. [5] K.Chen et a], Proc. Int. Semicon. Dev. Res. Conf p.607, 1995. [6] K.Y.Toh, P.Ko, R.Meyer, IEEE J. Solid State Circuits, Apr. 1988. [7] J.H. Huang Int. Electron Device Meeting p.569, 1992. [SI W C . Lee, C. Hu, Symp. On VLSl Technology,p.13,2000. [9] K.M. Cao, Int. Electron Device Meeting p.815,2000. [IO] P. Su et al, Custom IC Conf p. 197,2000. [I I] W. Liu et al, IEEE Trans. Electron Devices, p.1070, 1999. [I21 X. Jin et al, Int. Electron device Meeting, p.961, 1998. [I31 X. Jin et al, VLSl Tech. Symp. p.196,2000. [14] K.K.Hung et al, IEEE Trans. Electron Devices, p.1322, 1990. [I51 Y. Cao et al, Custom IC Conf. p.201.2000. [ 161 tittp ~\~~~.H.-dcvicc.Ercs.bcrkel~~,.rd~l~. ptnc
2001 Symposium on VLSl Circuits Digest of Technical Papers
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Fig. 8 The new holistic thermal noise model matches the data without unexolained "excess noise".
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Fig. 9 BSIM users may obtain customized model files for 0.180.07um CMOS technologies on-line within minutes.
2001 Symposium on VLSl Circuits Digest of Technical Papers
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