Automatic Synthesis of Low-Power Gated-Clock Finite-State Machines
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Automatic Synthesis of Low-Power Gated-Clock Finite-State Machines
machines (FSM's) with gated clocks relies on efficient algo- called guarded evaluation. rithms for .... be taken in detecting and eliminating timing violations that may arise when ... the FSM, when the machine does not perform state or output transitions. ... not propagate to the AND gate when the global clock is high. Moreover ...
