Synthesis of 3D Asynchronous State Machines 3

Synthesis of 3D Asynchronous State Machines Kenneth Y. Yun

David L. Dill

3

Steven M. Nowick

Computer Systems Laboratory Stanford University Stanford, CA 94305 Abstract We describe a new synthesis procedure for designing asynchronous controllers from burst-mode specifications, a class of specifications allowing multiple input change fundamental mode operation. Our implementation of burst-mode state machines uses standard combinational logic, generates low-latency outputs and guarantees freedom from hazards at the gate level. It requires no locally-synthesized clock and no storage elements. In addition, primary outputs as well as additional state variables are used as feedback variables. The state assignment technique is based on the construction of a three-dimensional next-state table.

1 Introduction As designers seek to improve the performance of hardware systems, there has been a renewed interest in asynchronous design. Asynchronous design methods promise to eliminate the penalties of synchronous design due to clock skew, worst-case delay assumptions, and resynchronization of asynchronous external inputs. In this paper, we describe a new, correct design method for asynchronous controllers. This method is an outgrowth of work on locally-clocked state machines [9, 8], which start with burstmode specifications, a class of specifications allowing multiple input change fundamental mode operation. The new method has a number of distinguishing features: it uses no local clock, it requires no storage elements, and its output variables are used as feedback variables (additional feedback variables are also used). Furthermore, the new method uses a state assignment technique based on the construction of a threedimensional next-state table. We therefore call them 3D asynchronous state machines. This work is part of an ongoing effort to produce a range of correct synthesis methods for asynchronous controllers. These methods use standard combinational logic, generate low-latency outputs and guarantee freedom from hazards at the gate level. Unlike many methods, these methods do not require state bits to be encoded in the original specification before synthesis can begin; cf. USC property [3, 6, 4, 7]. Background. There have been a number of asynchronous design styles in the past 30 years. Many are based on Petri-nets [3, 6, 4, 7] or high-level languages of concurrency [5]. These methods have proved successful for small, highly concurrent designs. However, they often lack flexibility in minimization and encoding of state and in the implementation of logic functions, and thus have difficulty taking advantage of global optimization techniques. Other methods based on asynchronous state machine specifications have been implemented in numerous styles, both with and without a locally-generated clock. Existing methods often allow only single-input changes or restricted multiple-input changes which impose timing constraints on inputs [11]. 3 This work was supported by the Semiconductor Research Corporation, Contract no. 91-DJ-205, and by the Stanford Center for Integrated Systems, Research Thrust in Synthesis and Verification of Multi-Module Systems. (Due to a clerical error, this research credit was omitted from the published version of this paper. We apologize for this oversight.)

2

Overview

An asynchronous state machine allowing multiple-input changes is specified by a state diagram [9]. A state diagram contains a finite set of states, a number of labelled arcs connecting pairs of states, and a start state. Arcs are labelled with possible transitions from one state to another. Each transition consists of a non-empty set of inputs (an input burst) and a set of outputs (an output burst). Note that every input burst must be non-empty; if no inputs change, the machine is stable. In a given state, when all the inputs in some input burst have changed value, the machine generates the corresponding output burst and moves to a new state. Only specified input changes may occur, and input transitions may arrive in arbitrary order; however, the next set of input transitions (the next input burst) may not arrive until the machine is stabilized (fundamental mode environmental assumption). There is an implicit restriction to such burst-mode specification — no input burst in a given state can be a subset of another. An example of a burst-mode specification is shown in figure 3. This specification describes a simple controller having 3 inputs (a; b; c) and 2 outputs (x; y). s + and s 0 denote 0–1 and 1–0 transitions of the signal s. 2.1 Implementation In all sequential machines, the machine output depends not only on the inputs but also on the state of the machine, a mechanism that keeps track of the history of input changes. In Huffmanmode state machines, the state of the machine is stored only in internal state variables — primary outputs do not store any state information. In our 3D machines, however, primary outputs as well as additional internal state variables are used to store the state of the machine. Formally, a 3D asynchronous finite state machine can be defined as a 4-tuple (X; Y; Z; ) where

   

Xis a set of primary input symbols; Y is a set of primary output symbols; Zis a (possibly empty) set of internal state variable symbols;

2 2 ! Y 2Zis a next-state function.

: X Y Z

input os qs

output machine

Two-Level AND-OR Network

output

state

state variable machine

Figure 1: 3D Asynchronous State Machine.

The hardware implementation of the 3D state machine (see figure 1) is a two-level AND-OR network where outputs (and additional state variables when necessary) are fed back as inputs to the network. There are no explicit storage elements such as latches, flip-flops or C-elements in a 3D machine; only static feedback is used to maintain memory. The 3D implementation of the burst-mode specification is obtained from the 3-dimensional function map called the next-state table, a 3-dimensional tabular representation of the next-state function . In general, the next-state table is incompletely specified; however, the next state of every “reachable” state must be completely specified. Input Bit Vector X

Output Bit Vector Y

State Bit Vector Z 1

2

3

monotonically to 11; thus the next xy entries for abcxy = 110xx are specified to be 11. When the outputs xy stabilize to 11, the machine is in state B . In state B, the machine waits for the input burst b 0 c+ . The next xy for abcxy = 11011, 11111 and 10011 is specified 11 so that the outputs xy remain unchanged until both b 0 and c + fire. The next xy for abcxy = 101x1 is specified 01 so that x changes monotonically to 0 once enabled. When x stabilizes to 0, the machine is in state C , where it awaits the input burst c 0 . When the input transition c0 fires, the outputs xy must change to 10 monotonically. Attempting to specify the next xy for abcxy = 100xx to be 10, we run into conflicts (see the top table in figure 3) because the next xy for abcxy = 10000 and 10011 had already been specified 00 (during A! B) and 11 (during B! C). The internal state of the machine must be changed to avoid the conflicts. Our strategy is to back up to the state following the last output burst (abcxy = 10101) and change the internal state (state burst q + ). Note that the new internal state corresponds to the new layer of the next-state table. When the state variable q stabilizes to 1, the machine is in state C. The same procedure is applied for the transitions from state C to D and Dto A. At this point, all “reachable” entries of the next-state table are specified; next-states of the remaining entries are considered to be don’t care.

4

abcxy = 00000

A 1 2 3 4

Last Stable State End of Input Burst End of Output Burst New Stable State

a+b+ / x+y+

Intermediate States Token

B b-c+ / x-

Figure 2: 3D Machine Operation. The operation of the 3D state machine is similar to a Mealymode synchronous state machine. A machine cycle consists of 3 phases (input burst followed by output burst followed by state burst). During the idle state, the machine waits for an input burst to occur. When the last input transition of the input burst arrives, an output burst takes place. The state burst, if required, immediately follows the output burst, completing the 3-phase machine cycle. We can visualize the operation of the machine in the following way. A token resides in the finite 3-dimensional space (see figure 2) in which the input bit vector determines the position of the token in the X dimension, the output bit vector its position in the Y dimension, and the state bit vector its position in the Z dimension. The position of the token reflects the state of the machine. Starting from a stable state, as the machine detects input signal changes, the token moves across the X direction. After the last input transition, it moves along the Y direction as outputs change. At the conclusion of the output burst, the token may settle in the same layer (in the Z dimension) as in the initial stable state or may move along the Z direction and settle in a different layer if the state change is required. A simple example is used to illustrate the synthesis and operation of a 3D machine (see figure 3). Starting from the initial state, the next-states of all “reachable” entries of the next-state table are specified. In state A, the machine is idle waiting for the input burst a+ b+ . During the input burst a+ b+ , abc changes from 000 to 110 via 010 or 100 depending on whether b + or a+ comes first. The next xy for abcxy = 00000, 01000 and 10000 is specified to be 00 because the burst-mode specification mandates that outputs remain unchanged until the final input transition of the input burst fires. Once both a and b go to 1, the outputs xy must change

C c- / x+yD a- / x-

abc 000 001 011 010 110 111 101 100 xy 00 00 00 A 00 11 01 11 C 01 11 11 11 01 11 B 10 11

D

10 10 10 10

Conflicts Conflicts during the table construction abc xy 000 001 011 010 110 111 101 100 00 00 A 00 00 11 01 11 01 q=0 11 B 11 11 01 11 10 11 10 11 01 00

00

00

10 10 01 10 10 D

C

q=1

Next-State Table for outputs xy

Figure 3: Example (Specification and Next-state Table).

3

Hazard-Free Implementation

In order to simplify the hazard analysis, we can decompose the 3D machine into two parts (see figure 1), each of which has a twophase machine cycle. The first part (output machine) produces the primary outputs, and the second part (state variable machine) outputs the internal state variables. Each part can be described as a machine with its outputs fed back as feedback variables — for the second part, the primary outputs of the 3D machine are the inputs, and the internal state variables of the 3D machine are the outputs. Thus the output burst of the 3D machine can be viewed as the input burst of the state variable machine, and the state burst of the 3D machine as the output burst of the state variable machine. Let us assume (for now) that output transitions of the 3D machine do not arrive at the network input until the preceding input burst is assimilated by the machine; likewise, state transitions do not arrive at the network input until the preceding output burst is absorbed by the network. Then the internal state variables of the 3D machine, fed back as the inputs to the output machine, remain constant during the 2-phase machine cycle of the output machine.

Similarly, the primary inputs of the 3D machine do not switch during the 2-phase machine cycle of the state variable machine. We will examine below the types of hazards that can arise in asynchronous state machines (Combinational Hazards, Critical Races and Essential Hazards) and the remedies applied in the 3D machines. 3.1 Combinational Hazards There are two types of hazards in combinational logic — function hazards and logic hazards. A function hazard emanates from the incompletely specified next-state table whereas a logic hazard arises despite the correct next-state function map due to the delay variations of the physical gates [9, 1, 2]. 3.1.1 Function Hazard Let us examine the possibility of function hazards in the example (see figure 3). Assume that the machine is idle in state B (abcxy = 11011) at some point in time. It is specified that firing of both b0 and c + enables the output transition x 0 , but y is to remain 0. Suppose the next xy entry for abcxy = 10011 were specified to be 10. Then y might change from 1 to 0 to 1 during the input burst b0 c+ , which is a deviation from the specification we classify as a function hazard. The burst-mode restriction allows us to generate the table so that there are no function hazards during the input burst — outputs are specified to remain unchanged until the last transition of the input burst fires; i.e., the next xy entries for abcxy = 11111 and abcxy = 10011 must be specified to be 11. Let us move on to the output burst. Assume that the machine in the example is in state A(abcxy = 00000). It is specified that the input burst a+ b+ enables the output burst x + y+ . During the input burst, outputs x and y remain at 0. The last transition of the input burst (a+ or b+ whichever arrives later in time) enables the output burst. Once enabled, both x and y must monotonically change to 1. Suppose that the next xy entries for abcxy = 11001 is 01. If output y changes to 1 before x, then the machine may become trapped in that state (abcxy = 11001). This is a case of function hazard during the output burst. In order to prevent function hazards during the output bursts, we require the transient states of an output burst to have the same next-state as the final stable state of the output burst. Consequently, the next xy entries for abcxy = 110xx must be specified 11. To summarize, the possibility of function hazards during the input and output burst is eliminated by correctly specifying the next-state of every “reachable” state during the bursts. 3.1.2 Logic Hazard The machine outputs may still exhibit glitches, even if the nextstate function is completely and correctly specified, unless we insure that the implementation is free of logic hazards. Requirements to insure hazard-free combinational logic during input bursts are presented in [1, 2, 8]. These requirements are applied to the state and output bursts of the 3D machine as well. The primary outputs of the 3D machine are to remain unchanged during the state burst. The state burst, thus, can be viewed as input burst enabling 0–0 or 1–1 transition of the outputs, assuming that subsequent primary input transitions do not arrive at the network inputs until the state burst is absorbed by the network. Likewise, if we assume that output transitions of the 3D machine do not arrive at the network input until the preceding input burst is assimilated by the machine, then the machine outputs can viewed as undergoing 1–1 or 0–0 transitions enabled by the output burst starting from the stable state (This condition will be met by inserting delays in the feedback path as necessary). We can, then, use the same set of covering requirements used in [1, 2, 8] to prevent logic hazards during each possible burst that can appear in a 3D machine cycle: input burst, output burst, and state burst. The following are the covering requirements for output logic (see figure 4 for the covering requirements in the example).

  

For a 0–1 transition of output: The output burst must be covered by a single cube. For a 1–1 transition of output: The input burst must be covered by a single cube; the output burst must be covered by a single cube. For a 1–0 transition of output: Suppose n input transitions constitute an input burst enabling 1–0 transition of an output. The input burst must be covered by n cubes, each of which contains exactly one literal that corresponds to a unique input in the input burst. Thus, each cube changes monotonically from 1 to 0 as the corresponding input transition fires. In addition, we require that any cube that intersects transient states of an input burst B in (states traversed during B in preceding the last transition of B in not including the stable start state) must also include the start state of B in if Bin enables a 1–0 transition of an output, for otherwise one such cube may glitch (0–1–0) and the glitch may propagate to the output (1–0–1–0 dynamic hazard).

The smallest cube that covers a 1–1 transition of an output is called essential. Similarly, a 1–0 transition of an output is covered by a set of essential cubes — the set consists of n essential cubes iff n input transitions enable the 1–0 transition of output. In figure 4, each solid circle represents an essential cube for a 1–1 transition; dotted circles constitute a set of essential cubes for a 1–0 transition. A logic hazard is present in an on-set cover if an essential cube is excluded from it. The essential cover for a logic function is a set of essential cubes. q=0 abc xy 000 001 011 010 110 111 101 100 0 0 1 00 0 1 0 01 1 1 0 1 11 10 1 1-1 Cover

q=1 000 001 011 010 110 111 101 100 0 1 0 1 1 1 0

Next x

1-0 Cover

Figure 4: Example (Karnaugh Map for output x). 3.2 Critical Race If a transition between layers requires multiple state bit changes, the machine traverses intermediate layers before it settles down to the final stable state. In traditional asynchronous state machines [11], a critical race is said to be present if the final stable state depends on the order of state bit change. In 3D machines, however, we say that a critical race is present if the transient states during a layer transition (state burst) have different next-states from the final stable state. We insure that the machine is free of critical races by encoding layers such that no input or output burst intersects the transient states of layer transitions and by forcing all transient states during a layer transition to have the same nextstates as the final stable state of the transition. In addition, we guarantee freedom from logic hazards during the state burst by satisfying the requirements of the previous section. 3.3 Essential Hazard It has been assumed up to this point that output changes are not fed back until an input burst is assimilated by the machine; likewise, no state variable changes are fed back until the preceding output burst is absorbed. However, if feedback delays are short, there may be situations in which one or more fed-back outputs (at the network input) change before an enabled output transition fires. The hazard that arises due to the race between the arrivals of input transitions and output (or state variable) transitions at the network input is called the essential hazard. Essential hazards can

be avoided simply by inserting sufficient delays in the feedback paths. The possibility of an essential hazard during a 0–0 transition of an output is illustrated in figure 5. During the input/output burst ( a+ b+ ! x+ ) , y is specified to remain 0. However, if x+ is fed back to the network input before a 0 goes low, then a 0–1–0 glitch may propagate to the y output. Thus, we need to make sure that the feedback delay (t out0os ) is sufficiently large to avoid essential hazards. b

a+b+ x+ ab 00 01 11 10 xy 00 00 00 10 00 01 11 11 10 11 10

a

t in-lit

a’

output burst) are stated below without proofs. Similar sufficient conditions exist for the 2-phase machine cycle (output burst ! state burst). Below, tx0y denotes the minimum delay from a transition of type x and a transition of type y, while T x0y denotes the maximum delay. Lemma 1 The output of a two-level AND-OR circuit is hazardfree during the 0 ! 0 transition enabled by an input burst if tin0out + tout0os > Tin0lit . Lemma 2 The output of a two-level AND-OR circuit is hazardfree during the 0 ! 1 transition enabled by an input burst if 1. the circuit contains a product term which covers the output burst and 2. tin0out + tout0os >T in0lit and 3. tin0out + tout0os + tos0prod >T in0prod .

t in-out + t out-os

x a’bx

Next xy y = a’bx + ...

glitch due to "fast" x

Figure 5: Essential Hazard. 3.4 Sufficient Conditions for Hazard Freedom It is desirable to minimize feedback delays because the delays in the feedback paths impose an additional constraint on when the next set of primary input transitions can arrive at the 3D machine inputs without causing circuit malfunctions. We propose to minimize the feedback delays with a simple set of one-sided timing constraints (see figure 6).

Lemma 3 The output of a two-level AND-OR circuit is hazardfree during the 1 ! 1 transition enabled by an input burst if 1. the circuit contains a product term which covers the input burst and 2. the circuit contains a product term which covers the output burst and 3. tin0out + tout0os + tos0prod >T in0prod . Lemma 4 The output of a two-level AND-OR circuit is hazardfree during the 1 ! 0 transition enabled by an input burst if 1. there exists a surjective mapping from a set of single burstliteral product terms with initial values of 1 to the input burst and 2. all the multiple burst-literal product terms initially 0 remain 0 during the input burst and 3. tin0out + tout0os >T in0lit .

t in-out t in-prod t in-lit input output os

4 state

t os-prod qs

t out-os (1)

T in-lit