Design and Implementation of Reversible Sequential Circuits - IJARCET

International Journal of Advanced Research in Computer Engineering & Technology (IJARCET) Volume 3 Issue 4, April 2014

Design and Implementation of Reversible Sequential Circuits Harish Naik KP, G.Jyothi, Dr.K.N.Murulidhara, Dr.M.Z.Kurian  Abstract— In this paper, the basic reversible logic gates are used for reversible operation and can be used for reversible sequential circuit designing. When we say reversible computing, we mean performing computation in such a way that any previous state of the computation can always be reconstructed given a description of the current state. In recent years, reversible logic has many applications in quantum computing, DNA computing and nanotechnology. This paper proposes a reversible D-latch.and also proposes the design of four bit asynchronous and synchronous counter using reversible T flip-flop. In this paper we have given the comparative analysis of our design with existing design. We hope this paper will initiate a new area of research in the field of reversible sequential circuit.

Index Terms—Reversible Logic, Reversible Logic Gate, D-latch, T Flip-Flop, Reversible Counter.

I. INTRODUCTION Reduction of power dissipation remains one of the major goals in the VLSI circuit design for many years. R.Landauer demonstrated in early 1960s, that irreversible hardware computation results in energy dissipation due to the information loss, regardless of its realization technique [2]. It is proved that the loss of each one bit of information dissipates at least KTln2 joules of energy (heat), where K is the Boltzmann’s constant and T is the absolute temperature at which operation is performed [2]. Reversible logic circuits have theoretically zero internal power dissipation since they do not lose information. Bennett showed that in order to avoid KTln2 joules of energy dissipation in a circuit, it must be built using reversible logic gates [3]. The applications of reversible logic are quantum computation [12], optical computing [13], ultra low power CMOS design [14] and nanotechnology [15]. This paper is organized as follows. Section II presents the literature survey. Section III presents the basic definitions pertaining to reversible logic. Section IV discusses the reversible logic gates. Section V applications and Section VI conclude/future work of the paper.

Manuscript received April, 2014. Harish Naik K P is currently pursuing M.Tech VLSI & Embedded Systems in dept of E&C from Sri Siddhartha Institute of Technology, Tumkur, India. G.Jyothi is currently working as a assistant professor in dept of E&C at Sri Siddhartha Institute of Technology, Tumkur, India. Dr.K.N.Murulidhara is currently working as a HOD & professor in dept of E&C at PESCE Mandya, India. Dr.M.Z.Kurian, is currently working as a Dean & HOD in dept of E&C at Sri Siddhartha Institute of Technology,Tumkur. India.

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II.

LITERATURE SURVEY

Landauer [1] determined that the amount of energy dissipated to erase each bit of information is at least kTln2 (where k is the Boltzmann constant i.e. 3 *10^12 joule at room temperature) during any computation the intermediate bits used to compute the final result are erased this erasure of bits is one of the main reason for the power dissipation. C. H. Bennett [2] in 1973 discovered that the power dissipation in any device can be made zero or negligible if the computation is done using reversible model. He proved his theory with the help of the turing machine which is a symbolic model for computation introduced by Turing. Bennett also showed that the computations that are performed on irreversible or classical machine can be performed with same efficiency on the reversible machine. Based on the above concept the research on the reversibility was started in 1980's. In the year 1994 Shor [3] did a remarkable research work in creating an algorithm using reversibility for factorizing large number with better efficiency when compared to the classical computing theory. After this the work on reversible computing was started by more people in different fields such as nanotechnology, quantum computers and CMOS VLSI. Edward Fredkin and Tommaso Toffoli [4, 5] based on the concept of reversibility they introduced new reversible gates known as Fredkin and Toffoli reversible gates. These gates have zero power dissipation and are used as universal gates in the reversible circuits. These gates have three input and three outputs, hence they are known as 3*3 reversible gates. Peres [6] introduced a new gate known as peres gate. Peres gate is also a 3*3 gate but it is not a universal gate like the Fredkin and Toffoli gate. Even though this gate is not universal gate it is widely used in many application because it has less quantum cost when compared to the universal gate. The quantum cost of the Peres gate is 4. H Thalpliyal and N Ranganathan [7] invented a reversible gate known as TR gate. The main objective of introducing this reversible gate was to reduce the garbage output in a reversible circuit. Using the combination of Fredkin and Feynman gate a new gate known as Sayem gate was developed by Sujata S. Chiwande Prashanth R. Yelekar [9] sayem gate is a 4*4 1 through reversible gate and is used in designing sequential reversible circuits. H Thapliyal and N Ranganathan [8] were the first people to introduce the reversible logic to sequential circuits. They were successful in implementing sequential circuit such as D-latch, JK latch, T latch and SR latch using Fredkin and

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International Journal of Advanced Research in Computer Engineering & Technology (IJARCET) Volume 3 Issue 4, April 2014 Feynman gate. After this many more research has been done on sequential circuits using reversible gates. M.L. Chuang and C.Y. Wang [10] the numbers of gates, the number of garbage output were reduced in implementing the Latches and when the results were compared [8] with 25% improvement were achieved. Based on the above research and work done, they are going to implement the reversible logic concept for sequential circuits such as D-flip-flop, T-flip-flop and the four bit asynchronous counters. A.V.Ananthalakshmi, G.F.Sudha [11] In this paper, they proposed a new 4x4 reversible gate and it is being used to realize the D-latch and D-flip-flop in the reversible domain. The transistor representation of the proposed reversible D-flip-flop is implemented using adiabatic logic. The proposed D-flip-flop can generate both the outputs Q and Q’. Md. Selim Al Mamun, B. K. Karmaker [12] they are presented a research work on the design and synthesis of sequential circuits and flip-flops that are available in digital arena; and describes a new synthesis design of reversible counter that is optimized in terms of quantum cost, delay and garbage outputs compared to the existing designs. They proposed a new model of reversible T flip-flop in designing reversible counter. Sujata S. Chiwande , Shilpa S. Katre, Sushmita S. Dalvi; Jyoti C Kolte[13] This paper presents the introduction of basics reversible logic gates used for reversible operation & one of the applications as Synchronous counter. In this paper, they proposed comparison of synchronous & asynchronous counter using Sayem reversible gate. In the comparative analysis they are compared the number of gate, garbage output & power dissipation. As this is new approach to sequential circuit design using reversible gate and they compare their design of different sequential circuit with respect to power dissipation factor. they observed that Synchronous up/down counter has less power dissipation as compared to the Asynchronous up/down counter[13]. Tehniat Banu, Manjunath Kounte [14] in recent years, there is a remarkable paradigm shift in computation effiency due to information lossless computation performed by the reversible gates. The reversible logic means performing computation in such a way that using the output the input can be constructed and the erasure of intermediate data and energy dissipation is eliminated. The power dissipation, a major problem due to scalability in the VLSI devices has been addressed by using reversible logic. In order to utilize the concept of reversible logic completely the VLSI engineers will have to face many challenges. As we know the reversibility is obtained along with the garbage output and the number garbage output increases for the complex circuit hence reduction of the number of garbage output remains an open problem [14]. V. Rajmohan, Dr. V. Ranganathan [16] they proposed a reversible T-Flip-flop. Design of reversible asynchronous and synchronous counters is also proposed in their paper. The key contribution of their paper is the reversible realization of 4-bit Asynchronous and synchronous counters by using proposed reversible gates and the existing one. The ISSN: 2278 – 1323

proposed counter designs have the applications in building reversible ALU, reversible processor etc. And this paper proposes a concept on efficient and optimized reversible sequential circuit design of asynchronous and synchronous counters. III.

BASIC DEFINITIONS PERTAINING TO

REVERSIBLE LOGIC A. Reversible function The multiple output Boolean function F(x1, x2,..., xn) of n Boolean variable is called reversible if: 1. The number of outputs is equal to the number of inputs. 2. Any output pattern has a unique pre-image. In other words, the reversible functions are those that perform permutations of the set of input vectors. B. Reversible Logic Gate A reversible gate is a logical cell that has the N number of inputs and N number of outputs with a one-to-one mapping between the input and output vector. For the logical cell to be reversible the following two conditions are not permitted. 1. Direct fan-outs from the reversible gates. 2. Feedback from a gate output directly to its input. The block diagram of irreversible XOR gate and reversible XOR gate is as shown in fig 1.

(a)

(b) Fig 1(a) Irreversible XOR gate (b) Reversible XOR gate

C. The number of Reversible gates (N) This refers to the number of reversible gates used in circuit. D. The number of constant inputs (CI) This refers to the number of inputs that are to be maintained constant at either 0 or 1 in order to synthesize the given logical function. E. The number of garbage outputs (GO) This refers to the number of unused outputs present in a reversible circuit. One cannot avoid the garbage outputs as these are very essential to achieve reversibility. F. Quantum cost (QC) This refers to the cost of the circuit in terms of the cost of a primitive gate. It is calculated by knowing the number of primitive reversible logic gates (1*1 or 2*2) required to realize the circuit.


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International Journal of Advanced Research in Computer Engineering & Technology (IJARCET) Volume 3 Issue 4, April 2014 G. Flexibility This refers to the universality of a reversible logic gate in realizing more functions.

A B

H. Gate Level This refers to the number of levels in the circuit which are required to realize the given logic functions. I. Hardware Complexity This refers to the total number of logic operation in a circuit. Means the total number of AND, OR and EXOR operation in a circuit. J. Design constraints for Reversible Logic circuits In the design of any reversible logic circuits the following points must be considered to achieve an optimized circuit. i. Fan-out is not permitted. ii. Minimum quantum cost. iii. Garbage outputs must be minimum. iv. Constant inputs must be minimum. v. Minimum number of logic depth or gate levels. vi. Minimum delay.

IV. REVERSIBLE LOGIC GATES A reversible logic gate has equal number of input and output terminals and there is one to one mapping between them. Again we can say, gate is reversible if we can determine input vector from output vector and vice-versa. Reversible gate should practically loose very little amount of energy. Fan-out is not allowed in reversible circuits however fan-out can be achieved using additional gates. In this paper we have discussed basic reversible gates like Feynman gate, Fredkin gate, Toffoli gate, Peres gate and Sayem gate. Which we have used in implementing reversible sequential circuits. A. Feynman Gate Feynman gate is a 2*2 one through reversible gate as shown in figure 2. The input vector is I(A, B) and the output vector is O(P, Q). The outputs are defined by P=A, Q=A XOR B. Quantum cost of a Feynman gate is 1. Feynman Gate (FG) can be used as a copying gate [19].

P=A Toffoli gate

C

R=AB xor C Fig 3 Toffoli gate

C. Fredkin Gate Fig 4 shows a 3*3 Fredkin gate. The input vector is I (A, B, C) and the output vector is O (P, Q, R). The output is defined by P=A, Q=AC XOR A′B and R=AB XOR A′C. Quantum cost of a Fredkin gate is 5[6]. A

P=A Fredkin gate

B C

B

Feynman gate

Fig 4 Fredkin gate

D. Peres Gate Fig 5 shows a 3*3 Peres gate. The input vector is I (A, B, C) and the output vector is O (P, Q, R). The output is defined by P = A, Q = A XOR B and R=AB XOR C. Quantum cost of a Peres gate is 4[20]. A

Q=A xor B R=AB xor C

C Fig 5 Peres gate

E. Sayem Gate Fig 6 shows 4x4 sayem gate. The input vector is I (A, B, C, D) and the output vector is O (P, Q, R, S). The output is defined by P=A, Q=A’B XOR AC, R=A’B XOR AC XOR D, S=AB XOR A’C XOR D [10].

B

Q=A xor B

C D

Fig 2 Feynman gate

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P=A

Peres gate

B

P=A

B. Toffoli Gate Fig 3 shows a 3*3 Toffoli gate. The input vector is I (A, B, C) and the output vector is O(P,Q,R). The outputs are given by P=A, Q=B, R=AB XOR C. Quantum cost of a Toffoli gate is 5[5].

Q=AC xor A’B R=AB xor A’C

A A

Q=B

Sayem gate

P= A Q=A’B xor AC R=A’B xor AC xor D S=AB xor A’C xor D

Fig 6 Sayem gate

F. SVS gate Fig 7 shows 4x4 SVS gate. The input vector is I (A, B, C, D) and the output vector is O (P, Q, R, S). The output is defined by P=A, Q=B’C XOR A’B XOR AB’C, R=B’C XOR A’B XOR AB’C XOR D, S=A’C XOR AB [18].


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Fig 7 SVS gate

V. REVERSIBLE SEQUENTIAL LOGIC CIRCUITS

Fig 10 results of D-Latch with output Q and Q+

B. Proposed Reversible Positive Edge Triggered T-flip flop

A. Latches Here we can use D-Latch or T-Latch depending upon choice that can be used in implementing reversible sequential circuit (counter) [21]. a. D-Latch The characteristic equation of D-Latch is Q+=DE+E’Q. It can be realized with one SG. It can be mapped with SG by giving E, Q, D and 0 respectively in 1st, 2nd, 3rd and 4th input of SG. Fig 7 shows the design of D-Latch with only Q output and Fig 8 shows the design of reversible D-Latch with both the output Q and Q+ .One FG is needed to copy and produce the complement of Q from SG for the design of Fig 7(b).

a. T flip-flop using SG and FG gate As the name suggests, this flip-flop circuit used to toggle the output when input is high (1) and retains the output when input is low (0), thus it does two operation, it either holds the last state or toggles the output. Essentially, it has a logical symmetry with Controlled NOT kind operation. Truth table of T flip flop shown in table I. Table I: Truth table of T flip-flop T Q t+1 0 Qt 1 Q t+ The reversible realization of T Flip-flop has two SG gates and one Feynman Gate is shown in fig 8. The comparison of proposed design with the existing is shown in table II.

Fig 7 Design of D-Latch with only output Q

Fig 11 Reversible Positive Edge Triggered T flip-flop

Fig 8 results of D-Latch with only output Q Fig 12 Reversible Positive Edge Triggered T flip-flop

Fig 9 Design of D-Latch with output Q and Q+

Fig 13 Results of Reversible Positive Edge Triggered T flip-flop

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International Journal of Advanced Research in Computer Engineering & Technology (IJARCET) Volume 3 Issue 4, April 2014 Table II Comparison of Different T Flip-Flops with Only Q Output

Existing [17] Existing [18] Existing [19] Existing [12] Proposed Design Improvement factor w.r.t [17] Improvement factor w.r.t [18] Improvement factor w.r.t [19] Improvement factor w.r.t [12]

No of gates 10 5 10 5 3

Garbage outputs 12 3 10 5 3

Constant inputs 10 2 10 1 2

3.33

4

5

1.66

1

1

3.33

3.33

5

1.66

1.66

2

b. T Flip-flop using SVS gate A flip flop is a bi-stable multivibrator. A flip flop has only two states. In this section we propose the realization of T flip flop using reversible SVS gate. The truth table of the T flip flop is given in table III. The reversible design is shown in fig 14. And corresponding block diagram is shown in fig 15. The reversible realization of T flip flop has one constant input and it produces the garbage outputs. The comparison of the design of T flip flop with existing designs is given in table IV based on 3 parameters. In table V we compared the existing design that is they used two SG gate and one FG gate to design a T flip flop but in our proposed design we used only the SVS gate to design a T flip flop and improvement factor also shown in table. Table III Positive Edge Triggered T Flip-Flop CLK

T

Q N-1

Q

0

0

0

0

1

0

0

0

0

0

1

1

1

0

1

1

0

1

0

0

1

1

0

1

0

1

1

1

1

1

1

0

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Fig 14 Reversible Positive Edge Triggered T Flip-Flop

Fig 15 Block Diagram of Proposed T Flip-Flop

Table IV Comparison of Different T Flip-Flops with Only Q Output No of Garbage Constant gates outputs inputs Existing [17] 10 12 10 Existing [18] 5 3 2 Existing [19] 10 10 10 Existing [10] 5 3 2 Existing [16] 3 3 2 Proposed Design 1 2 1 Improvement 10 6 10 factor w.r.t [17] Improvement 5 1.5 2 factor w.r.t [18] Improvement 10 5 10 factor w.r.t [19] Improvement 5 1.5 2 factor w.r.t [10] Improvement 3 1.5 2 factor w.r.t [16] Table V Comparison of T Flip-Flops designed by different reversible gate T flip flop No of Garbage Constant design gates outputs inputs Existing 3 3 2 [16](using SG and FG gate) Proposed 1 2 1 Design(using SVS gate) Improvement 3 1.5 2 factor w.r.t [16]


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International Journal of Advanced Research in Computer Engineering & Technology (IJARCET) Volume 3 Issue 4, April 2014 C. Design of Asynchronous Reversible Counters A counter, by function, is a sequential circuit consisting a set of flip flops connected in a suitable manner to count the sequence of the input pulse presented to it in digital form. In a asynchronous counters, the output transition of one flip flop serves as a source for triggering other flip flops. a. Proposed 4-bit Asynchronous up Counter The reversible design of the 4-bit asynchronous up counter is shown in fig 16. At the output of each reversible T flip flop, the Feynman gate is used for the complemented Q output with the input B=1, these complemented Q outputs of each T flip flop trigger the subsequent T flip flop and the reversible design performs the up counter design. The comparison of proposed design with the existing is shown in table VI.

Table VI Comparison between Existing and Proposed Reversible Asynchronous UP Counter Design No of Garbage Constant gates

outputs

inputs

Existing [13]

16

17

8

Existing [14]

15

12

11

Existing [15]

17

8

9

Existing [16]

15

12

11

Proposed design

7

8

7

Improvement

2.28

2.12

1.14

2.14

1.5

1.57

2.42

1

1.28

2.14

1.5

1.57

factor w.r.t [13] Improvement factor w.r.t [14] Improvement factor w.r.t [15] Improvement factor w.r.t [16]

Fig 16 Proposed 4-bit Reversible Asynchronous up Counter

b. Proposed 4-bit Asynchronous down Counter The reversible design of the 4-bit asynchronous up counter is shown in fig 17. At the output of each reversible T flip flop, the Feynman gate is used for the complemented Q output with the input B=0, these complemented Q outputs of each T flip flop trigger the subsequent T flip flop and the reversible design performs the up counter design. The comparison of proposed design with the existing is shown in table VII.

Fig 17 Results Proposed 4-bit Reversible Asynchronous up Counter

Fig 18 Proposed 4-bit Reversible Asynchronous down Counter

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Fig 20 Proposed 4-bit Reversible Asynchronous Up/down counter

Fig 19 Results Proposed 4-bit Reversible Asynchronous down Counter

Table VII Comparison between Existing and Proposed Reversible Asynchronous down Counter Design No of Garbage Constant gates

outputs

inputs

Existing [13]

16

17

8

Existing [14]

15

12

11

Existing [15]

17

8

9

Existing [16]

15

12

11

Proposed design

7

8

7

Improvement

2.28

2.12

1.14

2.14

1.5

1.57

2.42

1

1.28

2.14

1.5

1.57

factor w.r.t [13] Improvement factor w.r.t [14] Improvement factor w.r.t [15] Improvement factor w.r.t [16]

c. Proposed 4-bit Asynchronous up/down Counter The implementation of reversible asynchronous Up/Down Counter is shown in Fig. 18. The Up/Down operation of this reversible circuits is controlled by the control input UP/DOWN. For UP operation, the control input should be 1 and for down operation, the control input should be 0. The comparison of proposed design with the existing is shown in table VIII.

Fig 21 Results Proposed 4-bit Reversible Asynchronous up/down Counter

Table VIII Comparison between Existing and Proposed Reversible Asynchronous UP/DOWN Counter Design No of Garbage Constan gates

outputs

t inputs

Existing [16]

15

12

11

Existing [13]

19

20

8

Existing [14]

15

12

11

Proposed design

7

8

7

Improvement

2.14

1.5

1.57

2.71

2.5

1.14

2.14

1.5

1.57

factor w.r.t [16] Improvement factor w.r.t [13] Improvement factor w.r.t [14]

D. Design of Synchronous Reversible Counters An asynchronous counter below is simple but not very fast. If a counter with a large number of bits is constructed in this manner, then the delays caused by the cascaded clocking scheme may become too long to meet the desired performance requirements. In this project proposes a faster counter by clocking all flip flops at the same time presented

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International Journal of Advanced Research in Computer Engineering & Technology (IJARCET) Volume 3 Issue 4, April 2014 below. Synchronous counters have regular pattern and can be constructed using flip flops and gates. a. Proposed 4-bit Synchronous up Counter The reversible design of the 4-bit synchronous up counter is shown in fig19. The Toffoli gate is used to realize the AND function. Feynman gate is used for the fan-out of Q output with the input B=0.the comparison of the proposed design with the existing is shown in table IX.

Fig 22 Proposed 4-bit Reversible Synchronous Up counter

Table IX Comparison between Existing and Proposed Reversible Synchronous UP Counter Design No of Garbage Constant gates outputs inputs Existing [16] 15 12 13 Proposed Design Improvement factor w.r.t [16]

9

10

9

1.66

1.2

1.44

The proposed reversible counter design will have reduced number of gates, garbage outputs and constant inputs. And we have done a comparative analysis over the existing designs. These proposed designs have efficient and optimized reversible sequential circuit design of asynchronous and synchronous counters. And have various applications in reversible ALU, reversible processor etc. This work forms an important move in building large and complex reversible sequential circuits for quantum computers. The future work could be to develop efficient reversible counters and reversible controller circuits. ACKNOWLEDGMENT We would like to express our sincere thanks to the anonymous reviewers for their critical suggestions which helped in improving the manuscript and also we express our gratitude to our respective faculty and our parents for supporting this work. REFERENCES [1] [2] [3]

[4] [5] [6] [7]

[8]

VI. APPLICATIONS Reversible computing may have applications in computer security and transaction processing, but the main long-term benefit will be felt very well in those areas which require high energy efficiency, speed and performance .it include the area like  Low power CMOS.  Quantum computer.  Nanotechnology.  Optical computing.  DNA computing.  Computer graphics.  Communication.  Design of low power arithmetic and data path for digital signal processing (DSP).  Field Programmable Gate Arrays (FPGAs) in CMOS technology.

[9]

[10]

[11]

[12]

[13]

[14]

[15]

[16]

VII. CONLUSION AND FUTURE SCOPE This paper proposes designs of basic reversible sequential elements such as latches, flip-flop and counters. ISSN: 2278 – 1323

[17]

Landauer .R, ―Irreversibility and heat generation in the computing process‖, IBM J. Research and Development,Vol.5, Issue 3, July 1961. Bennett C.H., ―Logical reversibility of Computation‖, IBM J.Research and Development,Vol.14, Issuse 6, Nov 1973. P. Shor, ―Algorithms for quantum computation: discrete log and factoring‖, Proc. 35th Annual Symp. On Found. Of Computer Science , IEEE Computer Society, Los Alamitos, 1994. T. Toffoli., ―Reversible Computing‖, Tech memo MIT/LCS/TM-151, MIT Lab for Computer Science . 1980. E. Fredkin and T. Toffoli, ―Conservative logic‖, Int. J. Theor. Phys., vol. 21, 1982. A. Peres, ―Reversible Logic and Quantum Computers‖, Physical Review A, vol. 32, 1985. H Thapliyal and N Ranganathan, ―Design of Efficient Reversible Binary Subtractors Based on a New Reversible Gate‖, IEEE Proceedings of the Computer Society Annual Symposium on VLSI, 2009. H Thapliyal and N Ranganathan, ―Design of Reversible Latches Optimized for Quantum Cost, Delay and Garbage Outputs‖, Proceedings of Twenty Third International Conferences on VLSI Design, 2010. Sujata S. Chiwande and Prashanth R. Yelekar, ―Design of sequential circuit using reversible logic‖, IEEE-International Conference Advances in Engineering, Science and Management (ICAESM -2012) March30, 31, 2012. M. L. Chuang and C.Y. Wang, ―Synthesis of reversible sequential elements‖, ACM journal of Engineering Technologies in Computing Systems (JETC), vol. 3, no. 4, 2008. A.V.Ananthalakshmi, G.F.Sudha , Design of 4-Bit Reversible Shift Registers, Wseas Transactions on Circuits and Systems, Issue 12, Volume 12, December 2013. Md. Selim Al Mamun, B. K. Karmaker, ―Design of Reversible Counter‖, International Journal of Advanced Computer Science and Applications (IJACSA), Vol. 5, No. 1, 2014. Sujata S. Chiwande , Shilpa S. Katre, Sushmita S. Dalvi; Jyoti C Kolte, ―Performance Analysis of Sequential Circuits using reversible logic‖, International Journal of Engineering Science and Innovative Technology (IJESIT), Volume 2, Issue 1, January 2013. Tehniat Banu, Manjunath Kounte, ―Performance Analysis of Irreversible and Reversible Counter‖, Edition on Reconfigurable Computing Embedded, FPGA based, VLSI and ASIC Designs, June 2013. Majid Haghparast, 2Mohammad Samadi Gharajeh, ―Design of a Nanometric Reversible 4-Bit Binary Counter with Parallel Load‖, Australian Journal of Basic and Applied Sciences, 2011. V. Rajmohan, Dr. V. Ranganathan, ―Design of Counters Using Reversible Logic‖,IEEE 3rd International Conference of Electronics computer Technology (ICECT), Vol.5. 2011. Himanshu Thapliyal and M.B Srinivas, ―A Beginning in the Reversible Logic Synthesis of Sequential Circuits‖, Proceeding of Militarry and Aerospace Programming Logic Devices International Conferences.2005.


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International Journal of Advanced Research in Computer Engineering & Technology (IJARCET) Volume 3 Issue 4, April 2014 [18] SKS Har,V. Kamakoti, ―Efficient Building Blocks for Reversible Sequential Circuit Design‖, IEEE 49th International Midwest Symposium on Circuits and Systems, Vol.1,2006. [19] J. E. Rice, ―A New Look at Reversible Memory Elements‖,Proceeding of IEEE International Symposium on Circuits and Systems,Lethbridge univ.,Alta, May 2006. [20] Abu Sadat Md. Sayem, Masashi Ueda, ―Optimization of reversible sequential Circuits‖, Journal of Computing, Vol 2, Issue 6, june 2010. [21] KP, Harish Naik, G. Jyothi, K. N. Murulidhara, and M. Z. Kurian. "A Survey on Synchronous and Asynchronous Counters using Reversible Logic Gates."International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering (IJAREEIE),Vol.2, Issuse 3. Feb 2014..

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