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Detection and Classification of Single-Electron Jumps in Si Nanocrystal Memories Calogero Pace, Gino Giusi, Felice Crupi, and Salvatore A. Lombardo
Abstract—In this paper, we report a purposely designed instrumentation and a jump detection procedure for the measurement of single-electron phenomena in solid-state nonvolatile memories based on a silicon nanocrystal floating gate metal–oxide–semiconductor field-effect transistor. The stepwise evolution of the drain current of a memory cell after a “write” operation is monitored by means of a purposely designed low-noise acquisition system with a bandwidth of up to 10 kHz. The advantage of the measurement system background noise and bandwidth over a traditional semiconductor parameter analyzer performance is evident in the detection and classification of single-electron events. Index Terms—Low-noise amplifiers, low-noise bias circuits, MOSFET memory integrated circuits, nonvolatile memories, wafer-level measurements.
I. I NTRODUCTION
N
ANOCRYSTAL memories are an interesting approach in pushing the scaling limits of Flash devices [1]–[5]. These are, in fact, close in facing fundamental scaling issues that are mainly related to the generation of defects that are responsible for stress-induced leakage current (SILC) in tunnel oxides after extensive program/erase cycling. This parasitic but unavoidable effect forces to maintain the tunnel oxide thickness essentially unchanged, whereas lateral geometries have to be scaled, setting up an obstacle to go beyond the 50-nm node. For these reasons, nanocrystal memories (Fig. 1) appear promising, given their intrinsic robustness to SILC defects [6] and negligible capacitive couplings [7]. Moreover, with respect to other well-known discrete-trap memories such as the nitride-based memories (e.g., silicon– oxide–nitride–oxide–silicon memory and nitride read-only memory), they present the advantage of allowing the Fowler– Nordheim erase while maintaining a relatively thick bottom oxide (about 5 nm), which also permits reliability and retention at high temperatures [8]. A very important issue in these Manuscript received July 15, 2006; revised September 21, 2007. This work was supported in part by the Italian Ministry of Foreign Affairs under Project “RHESSA” and in part by the European Commission under Project “FINFLASH” IST-2005 16917. C. Pace and F. Crupi are with the Department of Electronics, Informatics, and Systems, University of Calabria, 87030 Rende, Italy, and also with the Institute for Microelectronics and Microsystems, National Research Center (CNR), 95121 Catania, Italy (e-mail:
[email protected];
[email protected]). G. Giusi is with the Department of Electronics, Informatics, and Systems, University of Calabria, 87030 Rende, Italy (e-mail:
[email protected]). S. A. Lombardo is with the Institute for Microelectronics and Microsystems, CNR, 95121 Catania, Italy (e-mail:
[email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIM.2007.909469
Fig. 1. Sketch of a nonvolatile memory cell based on a nanocrystal floatinggate metal–oxide–semiconductor field-effect transistor. The insulator fills the free space between the polysilicon control gate and the nanocrystal layer and that between the nanocrystal layer and the substrate.
devices is understanding their scaling ability, particularly with reference to the Si dot nucleation in the fabrication phase and its consequences on the threshold voltage shift distribution [5]. To study the characteristics of submicrometer nanocrystal memory cells, purposely designed devices [3] (2.5-nm tunnel oxide, 7-nm control oxide, and hemispherical silicon islands with a radius distributed at about 5 nm) have been tested. Such a thin tunnel oxide does not allow data retention for long time periods under a positive gate bias condition, but the scope of this device is competing with a dynamic random access memory, reaching similar programming speed while allowing much longer refresh times. Moreover, the slowing down of trapping and detrapping phenomena enables deeper investigations, at the level of the single-electron effect, on how the charge trapped in the Si nanocrystals affects the transconductance and the threshold voltage shift of the memory cell. II. D EVICE C HARACTERIZATION The so-called “quasi-nonvolatile” [9] memory cells have been first characterized by means of the semiconductor parameter analyzer Keithley 4200-SCS. Using the instrument software Keithley Interactive Test Environment, two interactive test modules have been written to erase or write the memory cell, with pulse durations of as short as 5 ms. These modules, together with a sampling test module, allow erase–sample or erase–write–sample measurements without a pulse generator and a switch matrix. First, the “erase” and “write” procedures have been optimized to obtain a repeatable and safe behavior of the memory cell. The erased-status ID –VGS characteristic is obtained in a reproducible way after the application of a 50-ms VGS = −4 V pulse starting from almost every nanocrystal charge condition. On the contrary, the written-status characteristic is very dependent on the pulse height and duration, and on the
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PACE et al.: DETECTION AND CLASSIFICATION OF SINGLE-ELECTRON JUMPS IN Si NANOCRYSTAL MEMORIES
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Fig. 2. Drain current versus gate voltage for a memory cell in the “erased” state and in the “written” state. The “written” curve is influenced by the bias voltage applied during the measurement.
Fig. 4. Block diagram of the instrument (gray inset) designed for the waferlevel characterization of nanocrystal memories and the experimental setup.
meaningful statistics on the threshold voltage shift and electron emission time.
Fig. 3. Transient evolution of the drain current after an erase–write cycle occurring at t = 0 s, which was measured using a semiconductor parameter analyzer.
previous charge condition. Thus, the written-status ID –VGS characteristic has been measured after an erase–write cycle, using a 50-ms VGS = 5 V for the second pulse. Moreover, the charge stored in the nanocrystal varies during the measurement even at low gate voltages, as shown in Fig. 2, where two ID –VGS measurements have been performed, starting from a different VGS value. A transient evolution measurement can now be executed by applying an erase–write sequence and sampling the ID for VDS = 100 mV and VGS = 1.5 V, as shown in Fig. 3. Soon after the write pulse, threshold voltage VT is high, and drain current ID for the given bias is low. Then, in the following tens of seconds, the detrapping of the electrons from the nanocrystals causes a progressive VT reduction, allowing ID to increase. The curve shows a stepwise trend, but the instrument sample rate (about 8 Hz at most, which reduces below 1 Hz at low current levels) makes the quantitative evaluation of the step height and time an infeasible task. The aim of this paper is to describe the custom instrumentation that we have designed and built to acquire the ID transients with adequate resolution and bandwidth to perform
III. I NSTRUMENT D ESIGN The block diagram of the proposed instrument is shown in Fig. 4 (gray inset). The core of this system is the batteryoperated low-noise section, which has been enclosed in a 12 × 16 × 8 cm3 metal box placed near the contacting probes on the probe station shelf. This section consists of two low-noise programmable voltage sources for biasing the gate and drain terminals, a low-noise transimpedance amplifier for monitoring the channel current, and an ac-coupled voltage amplifier. The dc output channel provides the drain current full information, whereas the ac-coupled (fC = 100 mHz) amplified output provides for a higher resolution of the fast current variations. Each low-noise programmable voltage source has been implemented (Fig. 5) by means of a 10-µF polyester capacitor, followed by a low-input-bias-current (1 pA) low-noise operational amplifier (op-amp, TLC2201) connected as a unity-gain buffer. By careful circuit assembly and cleaning and drying the box interior with some silica gel, stray currents can be reduced, and the bias voltage drift, after a few minutes of stabilization, has been measured to be less than 0.2 mV/min for a 1-V bias value. A noise level of below 1−16 V2 /Hz above 100 Hz has been obtained. To apply the write or erase pulses, the signal from an arbitrary waveform generator can be supplied to the gate terminal through the switch that is, afterward, manually commutated to the bias source.
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Fig. 7. Time evolution of the drain current for VGS = 1.2 V and VDS = 35 mV and of a memory device that was previously erased (VG = −4 V for 50 ms) and then written (VG = 5 V for 50 ms). Fig. 5. Low-noise programmable voltage bias source.
resistance values. On the other hand, in the presence of CF , the transimpedance amplifier bandwidth will be limited to fC =
1 . 2πCF RF
(2)
For these reasons, the CF value has to be optimized case by case whenever the measurement range or the experimental setup changes. Signals have been recorded using a 12-bit personal-computer-based analog-to-digital conversion system that is based on a PCI-MIO16-E multifunction board by National Instruments. IV. R ESULTS
Fig. 6. Self-biasing low-noise transimpedance amplifier.
The transimpedance amplifier has been designed following the classical scheme of Fig. 6. The feedback resistance– capacitance bipole has been kept interchangeable to obtain, for each measurement, the best tradeoff between the gain, bandwidth, and background noise. Once the transient of interest has been acquired with the parameter analyzer, the user can identify the maximum current ID max . This can be, for example, the value reached at the end of the charge-detrapping phenomenon when the equilibrium between trapping and detrapping is reached for the given bias conditions. Then, the feedback resistance can be chosen, so that op-amp saturation is never reached, i.e., |VOUT | = | −RF ID max | < VOM
(1)
where VOM is the op-amp maximum peak output voltage for the given supply voltage (VBATTERY − 0.3 V for the TLC2201). A feedback capacitor CF has to be added to the circuit. In fact, without it, the presence of the op-amp common-mode input capacitance, on the order of some tens of picofarads, and of the cable’s stray capacitance gives rise to a third pole (aside from the two main op-amp poles) in the open-loop gain transfer function, causing the risk of instability in case of very large
In the nanocrystal characterization experiment, a bandwidth of as high as 10 kHz has been obtained, thus allowing a time resolution that is significantly higher with respect to the source measure units of the semiconductor parameter analyzer. Moreover, because the system allows the synchronous acquisition of the dc and amplified ac components, we have obtained, for the fast current fluctuations, a resolution that is adequate for the extraction of the requested information about the current jumps. Fig. 7 shows a typical evolution of the drain current at VGS = 1.2 V and VDS = 35 mV for a memory cell that was previously erased with a gate pulse of −4 V for 50 ms and then written with a gate pulse of +5 V for 50 ms. The preamplifier transconductance gain has been selected to be RF = 107 V/A, and the bandwidth limited to be about 1 kHz, choosing CF = 12 pF. The current equivalent input background noise is, in this case, about 2 · 10−27 A2 /Hz above 100 Hz. According to the ID –VGS curves, the ID level during the measurement indicates that the device always operates in the subthreshold regime. A stepwise behavior is clearly observed (Fig. 7), with each step up corresponding to a single-electron emission from the Si nanocrystal to the substrate and with each step down corresponding to a single-electron capture from the substrate into the Si nanocrystal [10]. Jumps in the signal are detected through a threshold-based algorithm. The signal is scanned point by point to detect monotonous rising or falling sequences, which are defined as edges. The averages for n points before the edge and for m points after the edge are evaluated to obtain the relative change in the signal level. If the absolute value of the change exceeds the fixed threshold, the edge is classified
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Fig. 8. Expanded view of the time evolution shown in Fig. 7. The result of the jump detection algorithm is shown as a continuous line.
as a jump. The values of n and m are runtime adjusted by the algorithm to avoid erroneous jump detection. Fig. 8 shows an expanded view of the signal trace shown in Fig. 7. The detected jumps are shown with the continuous line. In this case, a relative threshold of 2% of the average current is used. Once the jump amplitude statistics is recorded, we can use the relationship between the drain current and the threshold voltage in the subthreshold region, i.e., ID ∝ e
q(VGS −VT ) mkT
(3)
where q is the elementary electron charge, k is the Boltzmann’s constant, T is the absolute temperature, and m is the bodyeffect coefficient, which can be extracted from Fig. 2 to obtain the threshold voltage statistics by using the following: ID2 mkT ∆VT = ln (4) q ID1 where ID2 is the signal level after the recognized jump, and ID1 is the signal level before the jump. The distribution of the threshold voltage shift is shown in Fig. 9. In this case, a zero threshold for the voltage shift was used to evaluate the best compromise between sensitivity and computational time, classifying the statistics of the whole fluctuations (even the smallest) in the signal. This choice gives rise to the central peak in the distribution. The elaboration has taken about 5 h but can be completed in about 20 s if the threshold is set to 2%. For higher ∆VT , two symmetrical peak pairs, centered around ±1.7 and ±4.3 mV, are clearly evidenced. From the analysis of the signal amplitude in the time domain (Fig. 7), we can identify “unidirectional” up jumps that correspond to a definitive loss of charge from some nanocrystals, and, between two unidirectional jumps, a series of “bidirectional” up–down jumps that corresponds to the charge exchange between the traps (nanocrystals or others) and the substrate. Because of the low relative number of unidirectional jumps, the distribution shown in Fig. 9 is almost symmetrical. The lobe pair for ∆VT = ±1.7 mV is comparable with the threshold voltage shift that is expected for a uniform floating gate metal–oxide–semiconductor field-effect transistor subject to a single-electron charge loss [4]. The nature of the other lobe pair is actually under investigation, together with the statistical evaluation of the jump duration and the correlation between the jump amplitude and the duration.
Fig. 9. Jump–amplitude distribution evaluated for the signal of Fig. 7 using a zero threshold value.
Several sets of current transients have been acquired and analyzed. The statistical properties of the threshold voltage shift and the emission time have been calculated, obtaining very promising results to understand the device physics and to develop a suitable model [11]. V. C ONCLUDING R EMARK This paper proposes a complete low-cost low-noise instrumentation solution for the wafer-level characterization of time-domain transients of electronic devices. The electronic instrument has been optimized for the investigation of the statistical properties of trapping and detrapping phenomena in Si nanocrystal memories. The reached sensitivity allowed the calculation of significant statistics on the acquired data, particularly on the threshold voltage shift caused by singleelectron capture and emission. ACKNOWLEDGMENT The authors would like to thank C. Gerardi of STMicroelectronics, R. Puglisi of the National Research Council (CNR), and B. De Salvo of the Laboratory for Electronics and Information Technology (LETI) for their fundamental contribution to the development of this paper. R EFERENCES [1] K. Yano, T. Ishii, T. Hashimoto, T. Kobayashi, F. Murai, and K. Seki, “Room-temperature single-electron memory,” IEEE Trans. Electron Devices, vol. 41, no. 9, pp. 1628–1638, Sep. 1994. [2] S. Tiwari, F. Rana, H. Hanafi, A. Hartstein, E. F. Crabbe, and K. Chan, “A silicon nanocrystal based memory,” Appl. Phys. Lett., vol. 68, no. 10, pp. 1377–1379, Mar. 1996. [3] B. De Salvo, C. Gerardi, S. Lombardo, T. Baron, L. Perniola, D. Mariolle, P. Mur, A. Toffoli, M. Gely, M. N. Semeria, S. Deleonibus, G. Ammendola, V. Ancarani, M. Melanotte, R. Bez, L. Baldi, D. Corso, I. Crupi, R. A. Puglisi, G. Nicotra, E. Rimini, F. Mazen, G. Ghibaudo, G. Pananakakis, C. Monzio Compagnoni, D. Ielmini, A. Lacaita, A. Spinelli, Y. M. Wan, and K. van der Jeugd, “How far will silicon nanocrystals push the scaling limits of NVMs technologies?” in IEDM Tech. Dig., H. J. Van Hilton, Ed., 2003, pp. 26.1.1-26.1.4. Inspec/Iee. [4] G. Molas, B. De Salvo, G. Ghibaudo, D. Mariolle, A. Toffoli, N. Buffet, R. Puglisi, S. Lombardo, and S. Deleonibus, “Single electron effects and structural effects in ultrascaled silicon nanocrystal floating-gate memories,” IEEE Trans. Nanotechnol., vol. 3, no. 1, pp. 42–48, Mar. 2004. [5] R. A. Puglisi, G. Nicotra, S. Lombardo, C. Spinella, G. Ammendola, and C. Gerardi, “Partial self-ordering observed in silicon nanoclusters deposited on silicon oxide substrates by chemical vapor deposition,” Phys. Rev. B, Condens. Matter, vol. 71, no. 12, p. 125 322, Mar. 2005.
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[6] I. Crupi, D. Corso, G. Ammendola, S. Lombardo, C. Gerardi, B. DeSalvo, G. Ghibaudo, E. Rimini, and M. Melanotte, “Peculiar aspects of nanocrystal memory cells: Data and extrapolations,” IEEE Trans. Nanotechnol., vol. 2, no. 4, pp. 319–323, Dec. 2003. [7] S. Lombardo, B. De Salvo, C. Gerardi, and T. Baron, “Silicon nanocrystal memories,” Microelectron. Eng., vol. 72, no. 1–4, pp. 388–394, Apr. 2004. [8] E. Spitale, D. Corso, I. Crupi, G. Nicotra, S. Lombardo, D. Deleruyelle, M. Gely, N. Buffet, B. De Salvo, and C. Gerardi, “Effect of high-k materials in the control dielectric stack of nanocrystal memories,” in Proc. 34th ESSDERC, 2004, pp. 161–164. [9] J. J. Lee, X. Wang, W. Bai, N. Lu, and D.-L. Kwong, “Theoretical and experimental investigation of Si nanocrystal memory device with HfO2 high-k tunneling dielectric,” IEEE Trans. Electron Devices, vol. 50, no. 10, pp. 2067–2072, Oct. 2003. [10] C. Pace, F. Crupi, S. Lombardo, C. Gerardi, and G. Cocorullo, “Roomtemperature single-electron effects in silicon nanocrystal memories,” Appl. Phys. Lett., vol. 87, no. 18, p. 182 106, Oct. 2005. [11] D. Corso, C. Pace, F. Crupi, and S. Lombardo, “Single-electron program/erase tunnel events in nanocrystal memories,” IEEE Trans. Nanotechnol., vol. 6, no. 1, pp. 35–42, Jan. 2007.
Calogero Pace received the M.Sc. and Ph.D. degrees in electronic engineering from the University of Palermo, Palermo, Italy, in 1990 and 1994, respectively. In 1996, he was with the University of Messina, Messina, Italy, as an Assistant Professor. In 2002, he joined the Department of Electronics, Informatics, and Systems, University of Calabria, Rende, Italy, where he is currently an Associate Professor of electronics. He is also with the Institute for Microelectronics and Microsystems, National Research Center (CNR), Catania, Italy. He is the Coordinator of the Italian Ministry of Foreign Affairs’ international project Reconstruccion de Hospitales y Extension de los Servicios de SAlud (RHESSA) on the radiation hardness of electronic devices and systems for space applications. He is a coauthor of more than 30 scientific and technical papers published in international refereed journals. He is currently involved in research projects on the design of low-noise electronic instrumentation, the design and characterization of electronic gas sensors, and the study of nanocrystal memory devices.
Gino Giusi received the M.Sc. and Ph.D. degrees in electronic engineering from the University of Messina, Messina, Italy, in 2002 and 2005, respectively. In 2005, he was a Visitor at the Interuniversity Microelectronics Center, Leuven, Belgium. In 2006, he was with the National Research Center (CNR), Catania, Italy. He is currently a Researcher with the Department of Electronics, Informatics, and Systems, University of Calabria, Rende, Italy. His research interests include the design of ultralownoise instrumentation, the characterization of devices through noise measurements, and the electrical characterization of modern complementary metal–oxide–semiconductor devices and memories.
Felice Crupi received the M.Sc. degree from the University of Messina, Messina, Italy, in 1997 and the Ph.D. degree from the University of Firenze, Firenze, Italy, in 2001, both in electronic engineering. Since 1998, he has been a repeat Visiting Scientist at the Interuniversity Microelectronics Center, Leuven, Belgium. In 2000, he was a Visiting Scientist at the IBM Thomas J. Watson Research Center, Yorktown Heights, NY. In 2006, he was a Visiting Scientist at the Autonomous University of Barcelona, Barcelona, Spain. In 2002, he joined the Department of Electronics, Informatics, and Systems, University of Calabria, Rende, Italy, where he is currently an Associate Professor of electronics. He is also with the Institute for Microelectronics and Microsystems, National Research Center (CNR), Catania, Italy. He has authored or coauthored more than 80 publications in international scientific journals and conference proceedings. His research interests include the reliability of very large scale integration complementary metal–oxide–semiconductor devices, electrical characterization techniques for solid-state electronic devices, and the design of ultralow-noise electronic instrumentation.
Salvatore A. Lombardo received the M.Sc. (cum laude) and Ph.D. degrees in physics from the University of Catania, Catania, Italy, in 1989 and 1994, respectively. In 1994, he became a Staff Research Scientist with the Institute for Microelectronics and Microsystems (IMM), National Research Council (CNR), Catania, where he has been a Senior Scientist since 2001. He is the author or coauthor of three review articles and about 150 scientific and technical papers published in international refereed journals. He is the holder of three patents. His research interests include the development and the electrical and structural characterization of semiconductor devices and of electronic materials. In these areas, he is the Coordinator for the IMM in several national and European projects.
