Diagnosing ADC nonlinearity at the bit level - IEEE Xplore

IEEE TRANSACTIONS ON INSTRUMENTATION A N D MEASUREMENT. VOL. 38, NO. 6. DECEMBER 1989

113Y

Short Papers Diagnosing ADC Nonlinearity at the Bit Level MAHMOUD FAWZY WAGDY,

SENIOR MEMBER, IEEE

sion. Only harmonics satisfying the sampling theorem are considered, i.e., 1 5 n 5 N/2. When the ADC most significant bit has failure, the nth harmonic after a DFT for the ith sequence where i = B - 1 is given by

Abstract-This paper discusses two methods for identifying analogto-digital converter (ADC) nonlinearity at the bit level. The integral nonlinearity (INL) is analyzed in the frequency domain using both DFT and Walsh transforms to determine which ADC bit is responsible for which harmonic or bin. It is shown that the effects of different bits on the outputs of either transform are separable. A 5-bit ADC example is investigated using both transforms to illustrate the implementation of the techniques.

I. INTRODUCTION The most famous methods for dynamic testing of analog-to-digita1 connecters (ADC’s) are the code density histogram test, and the spectral analysis FFT test. The histogram test is most sensitive to differential nonlinearity (DNL) errors, whereas the FFT test is most sensitive to integral nonlinearity (INL) errors [l]. The DFT output spectrum contains the input sine wave test signal, a noise floor caused by q u a n t i z a t h errors, and harmonic distortion caused by INL. A spectral averaging technique was proposed [2] to measure harmonic distortion and noise floor with the latter based on a closed form formula. A new method for measuring the ADC effective number of bits, based on spectral analysis, was also proposed [31. The INL has not been analyzed before using DFT to diagnose the ADC bits, i.e., determine which bit corresponds to which frequency bin. Therefore, a major intention of this paper is to fill this gap. A 5-bit ADC with failures in all bits is analyzed to illustrate the technique. The INL has been analyzed before using the Walsh transform [4] to identify the ADC nonlinearity at the bit level. This paper provides a general formula for the technique, and illustrates its implementation for a 5-bit ADC with failures in all bits.

+

...

Manuscript received November 6, 1988; revised July 10, 1989. The author was with the Department of Electrical Engineering, University of Lowell, Lowell, MA. He is now with the Department of Electrical Engineering, California State University-Long Beach, Long Beach, CA 90840.

IEEE Log Number 8930983.

e-~2rn(N/2-

1

I)lN

where SF is a scale factor equal to N / 2 for 1 for n = N/2. From a finite series table [6]:

(1) In


0

N n =2k

,B - 1

(5)

B. A 5-Bit ADC Example In this case, B = 5 and i is scanned from 0 through 4. By substituting these values into ( 5 ) , the resulting amplitudes corresponding to all harmonic indexes are shown in Table I. It is obvious that the failures of different ADC bits have separate effects on the DFT output spectrum. Thus in general, by studying the DFT spectrum of the INL caused by single-bit failures, it is possible to determine the amount of error associated with each bit. This can help error correction during ADC manufacturing, and circuit analysis based on actual specifications of the utilized ADC’s. However, by using the DFT, it may be very difficult to separate the effects of different bit failures when bit intermodulation (i.e., superposition error) occurs. For ADC’s with negligible superposition error, the DFT is perfectly suitable for bit diagnostics, and the harmonic components have more physical significance than those of any other transform.

0018-9456/89/1200-1139$01.00

0 1989 IEEE

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IEEE TRANSACTIONS ON INSTRUMENTATION A N D MEASUREMENT, VOL. 38, NO. 6, DECEMBER 1989

DU t

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I

/

I

INL

I

(bl

(b)

Fig. 1. (a) 4-bit ADC transfer characteristics. (b) Corresponding INL

TABLE I AMPLITUDE SPECTRUM OF INL OF 5-BIT ADC Harmonic Index kn

Harmonic Amplitude I y(kn) I

4

1

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3

0.215 q

4

5

0.133 q

4

7

0 099 q

4

9

0.081 4

4

11

0.071 E4

4

13

0.065 q

4

15

0.063 q

3

2

0.641 €3

3

6

0.225 E3

3

10

0.150 E3

14

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0.271 €2

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0.707 €1

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B. A 5-BitADC Example By scanning i , again, from 4 through 0, Walsh sequences 1, 3, 7, 15, and 31 are, respectively, used. The resulting transforms cor-

bit in error I

1

111. ANALYSIS OF INL USINGTHE WALSHTRANSFORM A . The General Case The Walsh functions have the same periodicity as the bit failure sequences, therefore, it is recommended for analyzing the INL data of ADC's [ 7 ] . The Walsh transform was fully described in [4]. Let us consider the INL plot of Fig. l(b). By using Wal( 1 , t ) and Wal(3, t ) shown in Fig. 2, there results

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Thus in general, it can be shown that for ADC bit i, using Wal(2 '-' - 1 , r ) results in an output transform y ( n ) given by

y(n)

=

y ( 2 ~ - i- 1 ) =

-5

i = 0, .

. ,B

-

1.

(7)

IEEE TRANSACTIONS ON INSTRUMENTATION A N D MEASUREMENT, VOL I

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38, NO. 6. DECEMBER 1989

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171 T. M. Souders, D. R. Flach, and B. A. Bell, “A calibration service for analog-to-digital and digital-to-analog converters,” Tech. Note 1145, Nat. Bur. Stand., July 1981.

-1

A Simple Technique for Analog Tuning of Frequency Synthesizers (b) Fig. 2. Walsh functions used for the INL of Fig. l(b). (a) Wal( 1, t). (b) Wal(3, t ) .

TABLE I1 WALSHTRANSFORM OF INL OF 5-BIT ADC bit in error

E2/2

15

0

31

responding to (7) are shown in Table 11. It is obvious that each bit failure corresponds to a unique Walsh output bin. Again, it may be very difficult to separate the effects of different bit failures when bit intermodulation occurs. However, with bit intermodulation, this transform describes the INL with the minimum possible meansquare error [7] for each bin.

IV. CONCLUSIONS The author tried to perform ADC bit diagnostics by directly using the FFT for the ADC output samples, but this turned out to be impossible. This is because each bit failure gives rise to odd harmonics, and for more than one bit failure the effects on frequency bins become inseparable. Therefore, ADC bit diagnostics should be based on the analysis of INL as opposed to the direct analysis of ADC output samples. The paper showed that there is no overlap of the contributions of the errors of different bits to the DFT of the INL. Thus groups of harmonics can be attributed to ADC individual bit failures based on a closed form formula. On the other hand, the Walsh transform gives only one output component corresponding to each bit failure which makes it easier for bit diagnostics. REFERENCES [l] J. Doemberg, H . 3 . Lee, and D. A. Hodges, “Full-speed testing of AID converters,” IEEE J. Solid-State Circuits, vol. SC-19, pp. 820827, Dec. 1984. [2] Y. C. Jeng, “Measuring harmonic distortion and noise floor of an AID converter using spectral averaging,” in IEEE Instrumentarion Measurement Technology Conf. Proc., pp. 212-215, Apr. 1988. [3] Y. C. Jeng and P. Crosby, “Sinewave parameter estimation algorithm with application to waveform digitizer effective bits measurement,” in IEEE Instrumentarion Measurement Technology Conf. Proc., pp. 218221, Apr. 1988. [4] M. Vanden Bossche, i. Schoukens, and J. Renneboog, “Dynamic testing and diagnostics of AID converters,” I€€€ Trans. Circuits Syst., vol. CAS-33, pp. 775-785, Aug. 1986. [5] A. Holland, “High resolution, high linearity interpolating AID converter,” in IEEE In?. Test Conf. Proc., pp. 96-104, 1984. [6] P. Z. Peebles, Jr., Probability, Random Variables, and Random Signal Principles. 2nd ed. New York: McGraw-Hill, 1987.

JAMES P. HAUSER Abs#rac#-An analog implementationof the fractional N phase-locked loop variable frequency synthesis technique is presented. In addition to its simplicity, this implementation allows tuning over ranges which exceed the reference frequency.

I. INTRODUCTION The frequency synthesizer to be described was developed in response to a need for a compact, low power, local oscillator for a swept heterodyne, low frequency, battery operated, portable spectrum analyzer. The resulting prototype synthesizer was constructed on a 4 X 4 in circuit board using standard CMOS integrated circuits. The total power requirements were +7 V at 8 mA and -7 V at 1 mA when operated in the 380-580-kHz frequency range. Further reductions in size may be expected from the use of surface mount devices. The spectral data presented later in this article are for the prototype circuit serving as the local oscillator in a prototype swept frequency spectrum analyzer. That is, instead of a spectral analysis of a fixed synthesizer frequency, the synthesizer was swept through a range of frequencies about a stable reference applied to the input of the prototype analyzer. Thus the results are conservative since they include the effects of noise coupled to the sweep voltage from other circuitry within the prototype analyzer. More significantly, this method of evaluation demonstrates one of the distinct advantages of this circuit. 11. BACKGROUND Fig. 1 is a block diagram of a typical fractional N frequency synthesizer. The circuitry outside the dashed lines is that of a classical phase-locked frequency synthesizer. The circuitry within those lines enables the synthesis of frequencies which are fractional multiples of the reference frequency [l]. This is accomplished by incrementing a digital accumulator by a value corresponding to a phase increment. The incrementing is performed during every reference frequency clock cycle. As the accumulator overflows, a cycle is deleted from the frequency feedback to the divide by the N module. This forces the voltage controlled oscillator to run at a frequency equal to the reference frequency times the feedback divide ratio N plus the overflow rate F,,,,( F,,, = F,, X N + Fuvr). Fig. 1 indicates the average frequenciesfwhich would be measured at various positions in the loop. It is important to note that the output from the divide by N module is only on average equal to the reference frequency. This results in the phase comparator generating unwanted phase correction voltages. To prevent these voltages from modulating the VCO, the output from the phase comparator is summed with a compensating analog voltage derived from the digital-to-analog conversion of the digital phase stored in the

Manuscript received June 5, 1989; revised August 28, 1989. The author was with the Aero Spectra Corporation, Boulder, Co. He is now with the Department of Aeronautics and Astronautics, Naval Postgraduate School, Monterey, CA 93943. IEEE Log Number 8931183.

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