A 100dB dynamic range CMOS image sensor with global shutter* Estelle Labonne, Gilles Sicard, Marc Renaudin
Pierre-Damien Berger
TIMA Laboratory 46 avenue Félix Viallet 38031 Grenoble, France
[email protected]
ATMEL Grenoble Avenue de Rochepleine 38521 Saint Egreve, France
[email protected]
Abstract— A 100dB dynamic range global shutter CMOS image sensor implementing an innovative fixed pattern noise (FPN) reduction method is presented. This image sensor uses global shutter pixel architecture in order to avoid distortion in imaging fast moving objects. To limit shutter leakage, a new PMOS pixel architecture is implemented. The high dynamic range is reach through a logarithmic architecture pixel. An onchip calibration method is implemented to reduce the FPN caused by process variations, weakness of this architecture. The basic principle is the calibration of each pixel against an inpixel reference current in place of the normal diode photocurrent. Two pixel levels corresponding to the photocurrent and a known reference current become available for every pixel. Then a double sampling technique allows to remove offsets due to threshold voltage variations. An innovation of this work consists in the implementation of the current calibration source inside the pixel. A 32x240 pixels test chip has been designed and fabricated in 0.18µm, 3.3V CMOS standard technology. Pixel measures 10x10µm² with a fill factor of 20%. The dynamic range is about 100dB with a frame rate up to 33 images per second and a 1.8%RMS FPN.
I. INTRODUCTION The CMOS image sensors currently present on the market have average performances such as: a dynamic range (DR) and a SNR about 60-70dB, a correct sensitivity (limited by the integration time and the small size of the photodiode) and a correction of the fixed pattern noise (FPN) carried out in the column amplifier [1]. However, a lot of applications such as automobile safety or monitoring require a greater dynamic range, often higher than 100dB to detect details at the same time in highlights and shadows of a scene. Researches are undertaken to increase this dynamic range. Main research axes are integration pixels (a long integration time [2], a variable integration time [3], multiple exposures [4], multi-gain [5]) and continuous operating pixels using a logarithmic photoreceptor [6]. Majors disadvantages of these integration pixels are a pixel area ten times higher compared to a standard integration pixel and a very long integration time (cumulative time). Continuous operating pixels have the advantage of being very simple (pixel with 3 transistors), providing an instantaneous high dynamic range but present the disadvantage of a high and difficult to compensate FPN [7] [8]. *This work is supported by the EU MEDEA+ project (PICS)
To avoid motion distortion in fast moving objects imaging or pulsed illuminated scenes imaging, the global shutter architecture is indicated. Due to the optical exposure of the in-pixel storage element, shutter leakage is critical. Some approaches [9] use separate wells in the pixel in cost of larger pixel area, other [10] use the skimming technology. Our global shutter pixel is implemented with PMOS transistors only, allowing a separate well and a low pixel pitch. To obtain a high dynamic range sensor, logarithmic photoreceptor architecture has been chosen. Our research concentrates on implementation of a FPN reduction method inside the pixel. The following sections present the main advantages and drawbacks of the logarithmic photoreceptor circuit. Then our FPN calibration method is explained in section III. Our global shutter architecture implementation is presented in section IV. Column amplifier function is explained in section V and an overview of our sensor is described in section VI. Next section reports experimental results and finally, conclusions and perspectives are drawn. II.
LOGARITHMIC PHOTORECEPTOR CIRCUIT
The logarithmic photoreceptor architecture has the advantage of providing a great dynamic range, about 120dB instead of 60-70dB for a standard integration CMOS sensor or 80dB for a CCD sensor. Continuous operating pixels transform the photocurrent into a corresponding voltage without using any integration process. A diode-connected MOS transistor operating in subthreshold mode (M1) is used to create an output voltage that is a logarithmic function of the photocurrent (Figure 1) Major drawback of logarithmic photoreceptor architecture is in its sensitivity to CMOS devices parameter variations. The most critical parameter is the variation of the transistors threshold voltage (due to the fabrication process). These threshold voltage variations induce a high pixel fixed pattern noise (FPN) that deteriorates the image quality. Some interesting techniques to remove the pixel FPN are published [7] [8] where the effect of threshold voltage variations in pixels is cancelled. An integrated analog calibration method for continuously working logarithmic sensors significantly reducing the FPN directly in the pixel is presented in [7].
In-pixel current source is controlled by Vcal signal. During normal acquisition phase, Ysel is set to low and Vcal is set to high. The output voltage can be approximated as
Vph
Ibias Vdd Ysel
M1
Vdd
Vout
Vph Iph
Gnd 100fA
PMOS logarithmic pixel
1pA 10pA
100pA 1nA
10nA 100nA
Iph
Logarithmic phototransduction curve
Figure 1. Logarithmic photoreceptor architecture and curve.
This method consists on supplying to the pixels a correction voltage, calculated for each pixel during a calibration phase through an external current reference. This calibration method allows to reduce significantly the FPN but its implementation implies a relatively large pixel size due to a high number of transistors (eight) and an additional capacitor. Another approach [8] carries out an on-chip calibration where the effect of threshold voltage variations in pixel is cancelled. The calibration is performed by sampling two pixel output levels, a level corresponding to the photocurrent and a level corresponding to the reference current. By subtracting these two levels, a significant suppression of FPN is achieved. The key advantage of this method is that offsets are suppressed while the transistors count per pixel is kept low (five transistors). Major drawback of these both methods is the need of a pixel external current source, one on each column. This reference current has to cover the whole pixel array, and degrades itself through capacitive and resistive paths. III.
PIXEL FPN CANCELLATION METHOD
In this work a sensor with on-chip in-pixel calibration is presented. The FPN cancellation is performed through an on-pixel current source. The advantage of this method is a better calibration current precision while the transistor count per pixel is kept low (four transistors). The FPN calibration method consists on two phases: pixel readout and pixel calibration. Pixel readout phase allows to measure the photodiode current through the output voltage. Pixel calibration allows to obtain a reference output voltage. Offset due to the threshold voltage variation is removed by subtracting the reference output voltage to this photocurrent output voltage. This operation is performed by the column amplifier. Compared [7] [8], pixel presented in this work includes the calibration current source. As illustrated in Figure 2, our calibration method is implement with one PMOS transistor more, M2. The control signals Ysel and Vcal are connected to all pixels on the same line. Each column is biased by the current source Ibias. pixel
Ibias
Vdd M1 M2
Vcal
Ysel Vph
M4
Iph Vout = Vph + Vth3 = Vdd − n Ut ln + Vth3 Io
where Vth3 is the threshold voltage of M3, n and Io are process dependent parameters, Ut is the thermal voltage kT/q. During calibration phase, Ysel is maintaining low and Vcal is activated, resetting the photodiode. The new output voltage become Vout, cal = Vph, cal + Vth3 = Vdd + Vth3 (2) where Ical is the drain current of M2. These two voltages are subtracted by the column amplifier. This operation is illustrated in Fig. 4. The result of this subtraction is Vout − Vout, cal = Vph − Vph, cal (3) where the threshold voltage of transistors M3, most important source of FPN, is removed. This operation is done by the column amplifier. Vout Vout,cal
Vout,cal - Vout1
Vout1
Vout,cal – Vout2
Vout2
100f
1p
10p
100p 1n
10n
100n
Iph (A)
Figure 3. Differential measurement to reduce FPN effects on the 120dB dynamic range.
IV. GLOBAL SHUTTER IMPLEMENTATION For imaging fast moving objects or pulsed illuminated scenes, the traditional method, rolling shutter, is not suitable since it leads to motion distortion. These applications require image sensor with global shutter architecture (figure 4). This method allows the simultaneous exposure of all the pixels, contrary to the rolling shutter approach which exposes pixels line by line. Global shutter pixel includes a sample-and-hold switch with an analog storage in each pixel. Due to the optical exposure of the in-pixel storage element, shutter leakage is critical. Some approaches [9] use separate wells in the pixel to isolate the storage node from the photodiode. These pixels allow good shutter efficiency but present a bad responsitivity and large pixel area. NMOS-only pixel with a global shutter presented by [10] uses the skimming technology, based on the subthreshold operation of the shutter transistor. GS OUT
Out
M3
Iph
Figure 4. Global shutter pixel architecture block diagram Figure 2. Implementation of the current calibration method inside the pixel
(1)
Critical to the shutter efficiency are charges generated outside the photodiode area. These charges can be collected either by the photodiode and by the drain of the shutter transistor and therefore add to the sampled signal. In order to avoid collecting these charges, a PMOS transistors only pixel has been implemented. In order to isolate the storage node from the photodiode node, two amplifiers have been added. The first amplifier allows to protect the photodiode node from the switching effects of the shutter transistor and to avoid a shutter leakage current in the photodiode.
to the pixel calibration signal. This structure allows two techniques of reduction of noise. The non-Correlated Double Sampling (CDS) eliminates the offset due to the first amplifier current fluctuation as well as the offset due to the capacitive coupling of the two storage capacities. This technique consists in sample and hold two levels and subtracting them. Read_pixel 2 Pixel output
1
Read_calibration
Out
Amplifier 1
Sample&hold stage
Amplifier 2
Figure 5. Our PMOS-only global shutter pixel schematic
During the image acquisition, all the pixels are activated, Vcal is set high and GS is set low, allowing the storage of the pixel value in the capacitance. At the end of the capture, all the global shutter transistors are opened. Pixel readout is done according to the classical method, line by line. In first step, the capacitance level is read and next the calibration is done and the calibration level is read. A timing diagram (Figure 6) illustrates these different steps. Ysel_line_i GS_line_i Vcal_line_i Global Shutter
line_i selection shutter level readout
Vcal
Figure 7. Column amplifier block diagram
Ysel
GS
calibration level readout
Figure 6. Simplified timing diagram of the global shutter, the sample and the calibration signals for the acquisition of one image.
V. COLUMN AMPLIFIER Column amplifiers are pixel readout circuits located at the bottom of each column. In our case, column amplifiers have to sample and hold the two pixel levels corresponding to the photocurrent output level and the calibration output level. A special care has to be carry in its design because column amplifiers are a source of fixed pattern noise (FPN). The column FPN results in vertical lines on the output image produced by an absolutely homogeneous input scene. This column FPN is due to the process variations of the amplifiers. To reduce this offset variation, our column amplifiers use a traditional structure described initially by [1], illustrated by the figure 7. The first amplifier collects the pixel output. During the pixel readout phase, the pixel output is sample and hold in the read-pixel capacitance. During the calibration phase, pixel output is sample and hold in the read-calibration capacitance. The two following amplifiers generate two voltages, Vpixel and Vcal, corresponding to the pixel signal and
The Delta Doubles Sampling (DDS) technique eliminates the offset between the both amplifiers 2 and 3. This technique consists in short-circuiting the two capacitances, C1 and C2 to obtain only the difference between the two amplifiers. The major drawback of DDS is the frame rate divided by two. These techniques correct the main dispersion source, the offset variations of the amplifiers. VI. ARCHITECTURE OF THE SENSOR The image sensor, illustrated in figure 8, consists of a pixels array, its drivers and its column amplifier. The sensor array is composed of 32x240 pixels. Column amplifiers have been carefully designed to minimize additional offsets. Vertical address decoder “Y” and horizontal address decoder “X” drive respectively the array rows and the column amplifiers. A test chip circuit has been designed in 0.18µm, 3.3V standard CMOS technology to validate the system performance. The pixel size is 10µm x 10µm, including a 5µm x 4 µm N+/P-well photodiode, seven PMOS transistors and a 20fF MOS capacitance. Y adress decoder
Vdiode Vcal
DDS 3
Vpol
Vpixel
32x240 pixels array
column amplifiers
Vpixel Vcal
X decoder
Figure 8. Block diagram of our sensor
VII. EXPERIMENTAL RESULTS This section presents the measurement and the characteristics of images taken in global shutter mode, with a 33,3ms frame rate. The output level range varies between 1mV to 530mV according to the illumination. The dynamic range of this sensor is illustrated in Figure 9. This curve presents a 100dB dynamic range but can be enlarge with higher illumination (measures have been limited by the 800lux maximum light supply). At very low illumination, sensor output varies between 1 and 70mV according to an exponential curve. At
high illumination, sensor response corresponds to a logarithmic curve. At medium illumination, sensor output presents a linear curve with a high slope. This is due to the logarithmic transistor biasing, the logarithmic transistor source voltage is lower than the supply voltage. This low Vdiode voltage is mandatory in order to avoid a saturation of the both amplifiers. This Vdiode voltage results in a modification of the logarithmic relation of the photodiode node and of the phototransduction curve. 600
straight line with high slope
Output level (mV)
500 400
logarithmic curve
300
« exponential » type curve
200 100
lux
0 0,01
0,1
1
10
100
1000
Figure 9. Sensor output according the illumination.
FPN varies between 1mV to 25mV (Figure 10). A higher FPN is observed between 1 and 10 lux, region where the logarithmic transistor is more sensitive to illumination, but too more sensitive to offset variations. Column FPN is 0,4% of the total signal swing while the total FPN is 1.8% (excepted in the range of 1 to 10 lux where the FPN become higher, about 4,7%). FPN, major drawback of logarithmic architecture is reduced, lower than 1.8% in the region where the logarithmic transistor works regularly. But a quite high FPN is observed in the low illumination area where the logarithmic transistor presents a high sensitivity. Its characteristic is tradeoff by a high output voltage swing.
Prototype Chip summary Technology Number of pixels Pixel size Photodetector
3,3V
Vdiode
1.25V
Frame per second Dynamic range FPN
530mV > 30 fps up to 100dB 1.8%rms of the total signal swing
Figure 12. Scene taken with a lamp on and off and a chip summary.
VIII. CONCLUSIONS AND PERSPECTIVES This paper presents global shutter image sensor with a high dynamic range. A 100dB DR is reach through logarithmic photoreceptor architecture, with a high sensitivity at low illumination. A new calibration method implementation (internal current source) is presented to remove pixel FPN. Global shutter architecture has been implemented, with an analog memory inside the pixel. A 32x240 pixels sensor has been fabricated (0.18µm, 3.3V CMOS standard technology) and characterized. The pixel presents a 10µm pitch with a 20% fill factor. The dynamic range is about 100dB with an output signal swing of 530mV, and a high sensitivity in low luminosity. Calibration method allows to reduce the FPN about 1,8% excepted in medium illumination region where a better tradeoff have to be found between the output level swing and the FPN. IX.
ACKNOWLEDGEMENTS
We would like to thank the ATMEL Grenoble CMOS Sensor Development Team for fabrication and characterisation access. REFERENCES
FPN (mV)
[1]
20
15
10
5
lux 0,1
1
10
100
1000
Figure 10. FPN curve according to the illumination
The shutter leak has been observed by illuminating the matrix with a uniform illumination and by measuring the average outputs of the 32 column amplifiers outputs for each of the 200 matrix lines. We observe a signal lost between the first lines readout and the last lines readout. This shutter leak is illustrated by Figure 11. This signal degradation varies according to the output level and to readout time. readout level (mV)
350
3,5 lux illumination
300 250 200 150
1,5 lux illumination
100
line
50
0
32x240 pixels 10µm x 10µm 20µm² N+-P photodiode
Power supply Output pixel swing
25
0 0,01
0,18µm CMOS
50
100
150
200
Figure 11. Global shutter leak effects for two different illuminations
Images presented in Figure 12 illustrate our sensor dynamic range capabilities.
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