JOURNAL OF ELECTRONIC TESTING: Theory and Applications 17, 139–147, 2001 c 2001 Kluwer Academic Publishers. Manufactured in The Netherlands.
A Low-Cost BIST Architecture for Linear Histogram Testing of ADCs F. AZA¨IS, S. BERNARD, Y. BERTRAND AND M. RENOVELL Laboratoire d’Informatique Robotique Micro´electronique de Montpellier (LIRMM), Universit´e de Montpellier II: Sciences et Techniques du Languedoc, 161, rue Ada-34392 Montpellier Cedex 5, France
[email protected] [email protected] [email protected] [email protected]
Received November 30, 2000; Revised February 6, 2001 Editor: V.H. Champac and M. Lubaszewski
Abstract. This paper investigates the viability of an ADC BIST scheme for implementing the histogram test technique. An original approach is developed to extract the ADC parameters from the histogram with a minimum area overhead. In particular, it is shown that the choice of a triangle-wave input signal combined with an appropriate time decomposition technique of the test procedure permits to drastically reduce the required on-chip hardware circuitry. Keywords: analog and mixed-signal testing, ADC test, Built-In Self-Test (BIST) 1.
Introduction
With the advance on mixed-signal integrated circuits, faster and more complex test equipment is required to meet ever more severe test specifications. An attractive alternative to simplify the test equipment is to move some or all the tester functions onto the chip itself. The use of Built-In-Self-Test (BIST) for high volume production of mixed-signal ICs is desirable to reduce the cost per chip during production-time. Mixed-signal ICs usually include Analog-to-Digital Converters (ADC), Digital-to-Analog Converters (DAC) or both. In the past few years, many published papers have been concerned with the definition of BIST techniques for analog or mixed-signal circuits [1–3, 6, 7, 10–13]. Some of them are more directly concerned with the definition of BIST techniques for ADC and DAC [1, 10–13]. A very classical ADC test technique used to determine the offset, gain error and non-linearity is the histogram method [4]. On this basis, an interesting approach has been recently reported [5]. The histogram
method involves the application of a given signal to the ADC input and the record of the number of times each code appears on the ADC outputs. The histogram method is widely used for the external testing of ADCs but histogram-based BIST with complete on-chip determination of the ADC parameters is usually not considered as a viable solution because of the huge amount of required additional circuitry. The objective of this paper is to discuss the viability of such histogram-based BIST by evaluating and minimizing the hardware resources required for complete on-chip determination of the ADC parameters. The ADC BIST scheme presented here has received a patent [8].
2. 2.1.
ADC Testing ADC Parameters
The basic function of an ADC corresponds to the quantization of the analog input voltage into a given number
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Fig. 1. ADC transfer function: (a) ideal case, (b) offset error, (c) gain error, (d) non-linearity errors.
parameters are actually defined to characterize the converter linearity. The differential non-linearity (DNL) measures the deviation of each actual code width from the ideal value of 1 LSB. The integral non-linearity (INL) measures the deviation of each output code from the ideal straight line.
of digital output codes over the full scale range (FS) of the converter. In an ideal ADC, each code has an equal width of 1 LSB and the transfer characteristic can be simply symbolized by a straight line joining every code transition. As an illustration, the ideal transfer characteristic of a 3-bit converter is givenin Fig. 1(a). Real ADCs show some minor or major deviations from the ideal transfer characteristic. These deviations are usually classified into three different types of error:
2.2.
• An offset error corresponds to a deviation of the actual first code transition from the ideal one. The straight line symbolizing the transfer function is therefore translated of this offset error as shown in Fig. 1(b). • A gain error corresponds to the deviation of the actual last code transition from the ideal one. The slope of the straight line symbolizing the transfer function is therefore modified according to this gain error as shown in Fig. 1(c). • Non-linearity errors may affect each code of the converter and basically correspond to a modification of the individual code width. As shown in Fig. 1(d), two
The specification of an ADC includes the determination of the 4 characteristic parameters, namely offset, gain, DNL and INL. The histogram test technique is widely in use in the industrial context to determine these parameters. This technique involves the application on the ADC input of a test signal with a known probability density function (usually a triangle or a sine-wave) and the record of the number of times each digital output code appears on the ADC output. These recorded samples form the measured histogram, which is characteristic of the ADC specifications. Consequently, comparing this measured histogram to the ideal one permits to extract the ADC parameters.
Histogram Test Technique
Low-Cost BIST Architecture
Fig. 2.
Quantized output signal and its histogram: (a) triangle wave input, (b) sine wave input.
As an illustration, Fig. 2 shows the quantized output signal of an ideal converter together with the resulting histogram in case of a triangle or sine-wave input signal. It can be observed that a uniform distribution of all code counts is obtained in the linear case, except for the extreme codes because an overloaded triangle-wave is used to ensure a full coverage of all ADC codes. At the opposite, a non-uniform distribution of the code counts is obtained in the sinusoidal case, reflecting the variable slope of the sine-wave input signal. 3.
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ADC Histogram-Based BIST
In the context of a BIST solution, the extraction of the ADC parameters from the histogram requires some hardware resources in terms of memory for the accumulation and storage of data and computing capabilities for the extraction of the parameters. More precisely, the first step consists in accumulating the measured histogram corresponding to the converter under test. A memory of 2n words is therefore required for storing the code counts of a n-bit converter. Then, this histogram has to be compared to the ideal one, implying
another memory of 2n words for the storage of the ideal code counts. Finally, comparison results have to be processed in order to extract the ADC parameters. In the general case, these computations are somewhat complex implying the use of a DSP or a microprocessor. Beside these resources, a block performing code detection for the construction of the measured histogram and a control unit to manage the test process are also required. The complete BIST architecture is illustrated in Fig. 3. It can be noticed that from a general point of view, a complete BIST scheme requires the definition of both the input stimulus generator and the output response analyzer. However, solutions can be found in the literature for on-chip generation of analog test stimuli [9]. Hence, we focus in this paper on the problem of defining the digital output response analyzer able to implement the histogram test technique. 4.
BIST Resource Optimization
The basic BIST architecture presented in the previous section represents a huge amount of additional circuitry if memory and DSP capabilities are not already
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Indeed, the exploitation of a sinusoidal histogram is much more difficult due to the non-uniform distribution of the code count. It actually exists some complex trigonometric relations between the ADC parameters and the histogram. As an example, the offset can be evaluated in the sinusoidal case using the following expression: π H (1) π H (2 ) FS cos NT − cos NT · Offset = n 2 cos π HN (1) + cos π HN(2 ) T T n
Fig. 3.
General BIST architecture.
available on-chip. It is the aim of this paper to present a new architecture for implementing the histogram test technique with minimal hardware resources. 4.1.
(1)
Choice of the Input Waveform
The first point we consider to minimize the required extra circuitry concerns the choice of the input waveform. Classically, either a triangle or sine wave is used as input signal to build up the histogram. Any of these two techniques may be used to extract the ADC parameters. However, the linear histogram technique presents a very interesting feature concerning memory saving for the storage of the ideal histogram. Indeed in the sinusoidal case, the code count varies from one code to another because of the variable slope of the input signal. The resulting ideal histogram exhibits a nonuniform distribution. Consequently, 2n memory words are really required to store the different code counts of the 2n codes. On the other hand in the linear case, the code count remains constant for every code in the converter because of the constant slope of the input signal. The resulting histogram exhibits a uniform distribution. Consequently, it is not necessary to use 2n memory words but a single one to store the ideal count corresponding to each one of the 2n codes. So we can obtain a drastic reduction of the required memory for the storage of the ideal histogram choosing the linear histogram rather than the sinusoidal one. However, note that in practice an overloaded input signal is usually applied to the converter resulting in a higher code count for the two extreme codes. Hence, 2 memory words are actually required to store the complete histogram, one for the ideal count of any non-extreme code (Hideal ) and one for the ideal count of the extreme codes (Hextreme ). Another advantage of the linear histogram technique concerns the calculation of the ADC parameters.
where H (1) and H (2n ) corresponds to the measured counts for the first and last code, FS is the full scale amplitude of the converter and NT the total number of samples. When using a linear input signal, every code in the converter should exhibit an equal density. Because of this uniform distribution, it exists simple linear relations between the ADC parameters and the histogram. Details on the computations required to evaluate the different parameters are given below. Offset Computation. An offset error is defined on the ADC transfer characteristic as the deviation of the actual first code transition from the ideal one. In other words, the code width of the first code is augmented of this error and the code width of the last code is reduced of the same quantity (Fig. 1(b)). Since the measured count of each code is directly proportional to the code width due to the input signal linearity, the resulting histogram presents a misbalance between the counts of the two extreme codes as illustrated in Fig. 4(b).The offset error can be estimated using any of these counts. Indeed, the offset error simply corresponds to the deviation of the measured count with respect to the expected one (Hextreme ), normalized by the ideal count (Hideal ) to get the value in LSB: H (1) − Hextreme H (2n ) − Hextreme =− Hideal Hideal (2) It is also possible to estimate the offset using the difference between the measured counts of the two extreme codes using the following expression: Offset =
Offset =
H (1) − H (2n ) 2.Hideal
(3)
The interest of this expression is that the expected count of the extreme codes is no longer required and only the
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Fig. 4. ADC linear histogram: (a) ideal case, (b) offset error, (c) gain error, (d) non-linearity errors.
ideal count is used. It is this latter expression that we choose to implement. Gain Computation. A gain error is defined on the ADC transfer characteristic as the deviation of the actual last code transition from the ideal one. In this case, all codes (except the extreme ones) have an equal width, but different from the ideal width of 1 LSB (Fig. 1(c)). Because the measured counts are directly proportional to the code widths, the resulting histogram still present a uniform distribution as illustrated in Fig. 4(c). However for any non-extreme code, the measured count is different from the ideal one. The gain error (in % of FS) can be simply evaluated using any of these codes as the ratio between ideal and measured counts: Gain =
Hideal H (i)
(4)
However for real measurements, the count may varies from one code to another due to regularity defects in the sample distribution for instance. To overcome this drawback, we propose to average the measurement on a number of codes. Considering m central codes, we
obtain the following expression for the ADC gain: Gain−1 =
nl+m 1 H (i) m · Hideal i=nl
(5)
DNL & INL Computation. The DNL of a each code is defined on the ADC transfer characteristic as deviation of each actual code width from the ideal value of 1 LSB (Fig. 1(d)). The resulting histogram including non-linearity errors is shown in Fig. 4(d). Because of the proportionality relation between the code width and the code count, the DNL can be simply estimated from the histogram as the relative deviation of the measured code count with respect to the ideal one: DNL(i) =
H (i) − Hideal Hideal
(6)
Such DNL errors can accumulate over a series of codes and cause of global deviation of the transfer characteristic from the ideal transfer curve. These accumulated DNL errors form the INL that can be simply expressed from the histogram as the cumulative
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sum of the DNL of all preceding codes: i INL(i) = DNL( j)
(7)
j=1
Summary of Required Operative Resources. As a summary, let us evaluate more precisely the hardware operative resources required for implementing the ADC parameters calculation. The analysis of the different parameter expressions reveals that: • the offset calculation demands a subtracter and a divider, • the gain calculation demands an adder and a divider, • the DNL and INL calculation demands a subtracter, a divider and an adder. Finally, it clearly appears that only elementary operators are required and the DSP used in the general case can be replaced by a much simpler operative unit. 4.2.
Time Decomposition Technique
The previous section has shown how the choice of the linear histogram technique permits to drastically reduce the amount of required additional circuitry. Due to the linear nature of the input signal, simple relations between the histogram and the ADC parameters have been established allowing the use of a simple operative unit instead of a DSP. In addition, the linear nature of the input signal also results in an ideal histogram with a uniform distribution, which permits to minimize the memory resources dedicated to the storage of the ideal histogram. Only the ideal count Hideal is involved in the computation of the ADC parameters and consequently, only this count has to be stored in a single memory word. The resulting architecture of the digital response analyzer is depicted in Fig. 5. This new architecture now presents very reduced resources for the computation of the ADC parameters and the storage of the ideal histogram but still comprises a large memory of 2n words for the storage of the measured histogram. This memory is obviously too large in terms of silicon area for a viable BIST structure. We have to define an alternative approach to reduce this area. Our fundamental idea is based on time decomposition concept. We actually suggest to use this time decomposition at two different levels: • at the higher level, the global test procedure is decomposed in different test phases, each phase dedicated to the determination of one ADC parameter,
Fig. 5.
BIST architecture optimization.
• at the lower level, every test phase is decomposed in different sequential steps, each step using only the measured count of one code. This time decomposition procedure is illustrated in Fig. 6. The main idea is to replace concurrent calculations by sequential calculations so that the same hardware resources are reused. For instance, we have established in the previous section that a subtracter is required for offset, DNL and INL calculations. Adopting a phase after phase approach, it is possible to use the same subtracter in the offset, DNL and INL calculation phases. In the same way, the adder and the divider required for the gain calculation can be reused in the DNL and INL calculation phases. So, applying the time decomposition at the higher level permits to further minimize the required operative resources. The same approach can be adopted inside each test phase in order to minimize the memory resources dedicated to the storage of the measured histogram. At this lower level, the idea is to process the histogram code after code so that a single code count has to be
Fig. 6.
Time decomposition technique.
Low-Cost BIST Architecture
stored at a given step of the procedure. The implementation of this approach is detailed in the following for the different parameter calculation phases. Offset Calculation Phase. The offset has to be computed as the difference between the counts of the first and last code (Eq. (3)). Consequently, two sequential steps are defined according to the code after code approach. In the first step, only the first code is processed. We actually suggest to accumulate the count of this code in a dedicated register by incrementing this register each time the code appears on the ADC output. By the end of this step, the register holds the count of the first code. Then in the second step, only the last code is processed. The subtraction between the code counts can be simply implemented by decrementing the register each time the last code appears on the ADC output. By the end of this second step, the register holds the difference between the two code counts and the offset can be evaluated. Such a procedure is illustrated on the pseudo-code given below. Algorithm 1. Offset calculation procedure
DNL Calculation Phase. The DNL has to be evaluated for each one of the 2n codes (Eq. (6)). Consequently, 2n sequential steps are therefore defined. At each step, the register is first initialized and then incremented each time the code under process appears on the ADC output. Dividing the register content by the ideal count and subtracting 1 at the end of each step gives the DNL value. The procedure is illustrated on the pseudo-code given below. Algorithm 3.
Algorithm 2. Gain calculation procedure
DNL calculation procedure
INL Calculation Phase. The INL has to be evaluated for each one of the 2n codes and basically corresponds to the cumulative sum of the DNL of all preceding codes (Eq. (7)). So the calculation procedure is basically the same than for DNL calculation, but the register is initialized only once at the beginning in order to implement the cumulative sum. The procedure is illustrated on the pseudo-code given below. Algorithm 4.
Gain Calculation Phase. The gain has to be evaluated using the counts of m central codes (Eq. (5)). Consequently, m sequential steps are defined according to the code after code approach. At each step, only one code is processed and the register is incremented each time this code appears on the ADC output. Since the register is initialized only once at the beginning, the register holds the cumulative sum of the m code counts by the end of the m steps. The gain can then be simply evaluated as illustrated on the pseudo-code given below.
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4.3.
INL calculation procedure
Optimized BIST Structure
In order to optimize the required hardware resources, the final BIST architecture combines linear histogram with an original time decomposition technique. Indeed, it has been demonstrated that the choice of the linear histogram technique permits to reduce the memory dedicated to the storage of the ideal histogram and simplify the calculation of the ADC parameters. Moreover, the time decomposition concept applied to the histogram technique permits to reduce both the operative resources and the memory dedicated to the storage of the measured histogram. The previous section has shown that the calculation of the ADC parameters can
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Fig. 7.
Optimized BIST architecture.
be performed using a single register for the storage of measured data and only one adder/subtracter and one divider for parameter computation. The final BIST architecture is given in Fig. 7.This architecture corresponds to a drastic reduction of the hardware circuitry compared to the original architecture comprising two memory of 2n words and DSP capabilities.
5.
Conclusion
The histogram test method for ADC is usually invoked in the context of external testing because of the important resources required for its implementation: two large memories and DSP capabilities. To make the histogram test method acceptable in the context of BIST, this paper analyzes in detail the technique and proposes two minimizations. It is shown that an adequate choice of the input stimulus causes a significant reduction of the memory required for the storage of the ideal histogram as well as a simplification of the computations for parameter estimation. Then, an original timing decomposition scheme is introduced allowing a reduction of the area overhead by means of hardware resource reuse. This applies not only for the memory resources dedicated to the storage of the measured histogram but also for the operative resources implementing the parameter computation. As a result, the final BIST architecture only comprises two memory words, an adder/subtracter and a divider. This extra circuitry appears quite negligible when compared to usual ADCs.
References 1. K. Arabi and B. Kaminska, “Efficient and Accurate Testing of Analog-to-Digital Converters Using Oscillation-Test Method,” Proc. European Design & Test Conference, 1997, pp. 348–352.
2. K. Arabi and B. Kaminska, “Oscillation Built-In Self-Test (OBIST) Scheme for Functional and Structural Testing of Analog and Mixed-Signal Integrated Circuits,” Proc. International Test Conference, 1997, pp. 786–795. 3. K. Damm and W. Anheier, “HBIST of Nonlinear Analog Building Blocks in Mixed-Signal Circuits,” Proc. International Mixed Signal Testing Workshop, 1995, pp. 257–262. 4. A. Frish and T. Almy, “HABIST: Histogram-Based Analog Built-In Self-Test,” Proc. International Test Conference, 1997, pp. 760–767. 5. M. Mahoney, DSP-Based Testing of Analog and Mixed-Signal Integrated Circuits, IEEE Computer Society Press, 1987. 6. N. Nagi, A. Chatterjee, and J. Abraham, “A Signature Analyser for Analog and Mixed-Signal Circuits,” Proc. International Conference on Computer Design, 1994, pp. 284–287. 7. M.J. Ohletz, “Hybrid Built-In Self-Test (HBIST) for Mixed Analog/Digital Integrated Circuits,” Proc. European Test Conference, 1991, pp. 307–316. 8. M. Renovell, F. Aza¨ıs, S. Bernard, and Y. Bertrand “Proc´ed´e et dispositif de test int´egr´e pour un CAN,” CNRS, Fr. Patent 9911304, filed Sept. 9, 1999. 9. G.W. Roberts and A.K. Lu, Analog Signal Generation for Built-In Self-Test of Mixed-Signal Integrated Circuits, Kluwer Academic Publishers, ISBN 0-7923-9564-6, 1995. 10. S. Sunter and N. Nagi, “A Simplified Polynomial-Fitting Algorithm for DAC and ADC BIST,” Proc. International Test Conference, 1997, pp. 389–395. 11. E. Teraoca, T. Kengaku, I. Yasui, K. Ishikawa, and T. Matsuo, “A Built-In Self-Test for ADC and DAC in a Single-Chip Speech CODEC,” Proc. International Test Conference, 1993, pp. 791– 796. 12. M.F. Toner and G.W. Roberts, “A BIST Scheme for a SNR, Gain Tracking and Frequency Response Test of a Sigma-Delta ADC,” IEEE Trans. Circuits & Systems II, vol. 42, pp. 1–15, 1995. 13. R. de Vries, T. Zwemstra, E. Bruls, and P. Regtien, “Built-In Self-Test Methodology for A/D Converters,” Proc. European Design & Test Conference, 1997, pp. 353–358. Florence Aza¨ıs received the MS and PhD degrees in electrical engineering both from the University of Montpellier, France. She is currently working in the Microelectronics Department of the Laboratory of Computer Science, Robotics and Microelectronics of Montpellier (LIRMM) as a Researcher of the National Council of Scientific Research (CNRS). Since 1993, she has been interested in the testing domain. Her main research interests include Analog and Mixed-Signal Circuit Testing and Fault Modeling. Serge Bernard received the MS degree in Electrical Engineering from the University of Paris XI, France. He is currently working in the Microelectronics Department of the Laboratory of Computer Science, Robotics and Microelectronics of Montpellier (LIRMM) where he is doing a PhD. His main research interests include Test, DesignFor-Testability and Built-In-Selt-Test for mixed-signal circuits. Yves Bertrand is a professor at the University of Montpellier (France). He works at the Microelectronics Department of the Laboratory of Computer Science, Robotics and Microelectronics of Montpellier (LIRMM). Previously, Yves BERTRAND worked in the field of solid-state physics and published several papers, especially on the photoemission of the semiconductors under synchrotron radiation. He joins the LIRMM in 1988. His research interests are principally
Low-Cost BIST Architecture
Fault Modeling, Design-For-Test and Built-In Self-Test for digital and mixed-signal Integrated Circuits and Design & Test of Microsystems. He is author or co-author of more than 100 papers in the the field of solid-state physics and microelectronics. He is presently responsible for the CRTC (Test Resource Center of CNFM). Michel Renovell received his MS and PhD in applied physics both from the University of Montpellier, France. He is a researcher
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at LIRMM (Lab of Computer Science, Robotics, and Microelectronics of Montpellier) and cohead of the Microelectronics Department. He has been Vice-chair of the Technical Activity Group of the IEEE Computer Society Test Technology Technical Committee and he is now Chair of the TTTC Communication Group. His research interests include analog and mixedsignalcircuit testing, fault modeling, and reconfigurable-circuit testing.
