A Non-ILP Based Threshold Logic Synthesis Methodology - CiteSeerX

A Non-ILP Based Threshold Logic Synthesis Methodology Tejaswi Gowda, Sarma Vrudhula, and Goran Konjevod School of Computing and Informatics, Arizona State University, Tempe AZ {tejaswi, vrudhula, goran}@asu.edu Abstract— Threshold logic is a powerful alternative to Boolean logic. Recently there has been renewed interest in the synthesis of threshold networks that implement logic functions. Until now, different heuristics have been proposed to generate threshold networks starting from the Boolean network of a function. These methods are essentially recombination of nodes of the Boolean network. We propose a new methodology for the synthesis of threshold networks starting from the factored form of the function. Two versions of the algorithm are proposed. One of them is shown to be optimal for a specific type of factored form. We compare our results against the previous approaches and on an average get a gate reduction of 14.14% and a delay reduction of 24%. The novelty in the work is the elimination of the use of the ILP formulation, that is extensively used by all the previous methods to detect threshold networks and to assign feasible weights.

I. I NTRODUCTION With the advancements in electronic materials and devices, it is now possible to create nano-scale devices, that have structure and properties different from those of existing devices [14]. These devices have some novel properties, which can be harnessed to improve the compactness and speed of VLSI circuits [10]. Boolean gates were suited to be implemented in CMOS, whereas it is more advantageous to implement threshold gates in nano devices. One of the reasons for the current dominance of CMOS is the availability of a mature and stable methodology to design, synthesize and test these circuits. This was possible because when CMOS was in the early stages of development, researchers began developing CAD methodologies [13]. We are in a similar juncture of time, as far as the nano devices are concerned. According to the Semiconductor Industries Association (SIA) roadmap’s prediction CMOS will continue to be the most dominant device technology for another 10-15 years[1]. It is our belief that nano-devices can become popular if good design automation techniques are developed. At present, a good amount of research has been done in the design of nano gates. Three, resonant tunneling diodes (RTDs) [11], quantum cellular automata (QCA) [3], and single electron transistors (SET) [8], are of special interest as they can be used to implement threshold gates efficiently. While there is a large body of literature, there is little work on the synthesis of multi-level threshold networks [13]. In this work, we address the problem of synthesis of multi-level threshold circuits. Most previous methods [13], [16] use a synthesized Boolean network as a starting point for the synthesis of the threshold network. We present a method to synthesize a multi-level threshold network, that starts from a functional representation of the Boolean function. An algorithm for generating a minimum gate network, using three input threshold gates is presented. Using the insight gained from generating the three input threshold networks, a heuristic for generating a network of n-input gates is given.

The method presented in the paper identifies patterns within a factored form to infer whether or not a function can be implemented as a threshold gate. We first present an algorithm that generates a threshold network, under the restriction that every node in the network has a fanin of at most three. We prove that the procedure produces a minimal gate threshold network given a maximally factored, non-extractable form of the Boolean function. Then we present a heuristic, using the same ideas, with a fanin restriction on the gates in the synthesized network. All earlier methods use ILP formulation to determine whether or not a function is a threshold function. As far as we are aware this is the first algorithm to use a non-ILP based method to determine the threshold nature of a function of any input size. II. BACKGROUND A function f (x1 , x2 , x3 , ...., xn ) is said to be positive in a variable xi , if there exists a disjunctive or conjunctive expression for the function in which xi appears only in the uncomplemented form. Similarly, f (x1 , x2 , x3 , ...., xn ) is said to be negative in xi if there exists a disjunctive or conjunctive expression for f in which xi appears only in the complemented form. If f is either positive or negative in xi then it is said to be unate in xi . If a function f (x1 , x2 , x3 , ...., xn ) is unate in each of it’s variables then it is called unate function [6]. A non-unate function is called a binate function. A Boolean expression can be algebraically factored to reduce the number of literals. [6] gives a comprehensive survey of the different algorithms that can be used to generate a maximally factored form, starting with a Boolean SOP expression of the function. Example: Consider a Boolean SOP: abcde! +de! f +dt! +s! . This form of the function has 11 literals. The same function can be written as d((abc+f )e! +t)+s! , which has 8 literals. The second form is called the factored form and there is a vast body of literature on factorization techniques. The problem of generating factored forms can be done by either algebraic or Boolean methods[6]. Algebraic factorization ignores Boolean properties of the function. Different approaches can be used to generate algebraically factored forms and each will generate different factored forms. A threshold element or gate has n two valued inputs, x1 , · · · , xn , and a single two valued output, y. It’s internal parameters are a threshold T and weights w1 , · · · wn , where each weight wi is associated with a particular input variable xi . The values of the threshold T and the weights wi (i = 1, · · · , n) may be any real, finite, positive or negative numbers. The input output relation of a threshold gate is defined as: y=

!

"n 1 if i=0 wi xi ≥ T 0 otherwise

(1)

where the sum product are the conventional arithmetic "and n ones. The sum i=0 wi xi is called the weighted sum of the threshold element. Example: Figure 1 shows a threshold gate implementing the function y = a! (b + c). Inputs a, b, c are assigned the weights −2, 1 and 1 respectively and the threshold of this gate (T ) is 1. The gate’s output will be 1 when the weighted sum of inputs is at least 1 (= T ), and will be 0 otherwise.

Fig. 1.

A threshold element implementing the function y = a! (b + c)

Even though threshold gates are more powerful than Boolean gates (e.g: a single 4-input threshold gate can implement the function ab(c + d) + (a + b)cd), they cannot implement all functions. In [9], it is shown that a binate function can’t be implemented by any threshold gate. Although all threshold functions are known to be unate[7], not all unate functions are threshold (threshold functions are those that can be implemented by a threshold element). The function ab + cd cannot be implemented by a threshold gate even though it is unate. These limitations make the problem of synthesizing a multi-level threshold network more complex, as each node of the synthesized network must now be a threshold function. Majority/minority functions are a a subset of threshold functions. Some recent work is focussed on synthesizing circuits in which the gates implement the majority or minority functions [12]. But the true potential of devices that can implement threshold gates will not be realized if we restrict the gates to be majority/minority gates. III. P REVIOUS W ORK There is a vast amount of literature dating back to the 1950’s, on threshold logic. Here we cite only a few [4] [9] [15]. In [9], a Linear Programming (LP) formulation is used to determine the threshold nature of a function, the feasible assignments of inputs, and the threshold weights. In [7], a method for recognizing threshold functions and synthesizing two-level threshold circuits is discussed. These methods are computationally expensive. The problem of synthesis of multi-level threshold networks did not receive much attention until recently. This was mainly because in the 1960s there was very little work being done in generating algebraic factored forms of Boolean expressions. Another reason was that there were no good physical implementations available for implementing threshold circuits. In recent years there has been increased research in the design of QCAs, SET and RTD gates. These devices inherently implement threshold elements. This has created renewed interest in the synthesis of multi-level threshold networks. In [13], a new methodology for the synthesis of threshold networks using a synthesized Boolean network is proposed. As stated earlier, a naive method to obtain a threshold network would be to replace each Boolean gate by it’s threshold

counterpart. This is called one-to-one mapping. A motivational example in [13] shows that this simple direct mapping results in sub-optimal networks. The method in [13] restructures a given logic network by merging nodes whenever possible. This is determined by solving the ILP. The results were a significant improvement in the gate count when compared to a network generated by one-to-one mapping. The method of [13] was improved by Li Zhang et. al. [16]. They propose four different heuristics to generate threshold networks starting from a threshold network obtained by oneto-one mapping of a Boolean network. The differences among the heuristics are in the way the network is traversed, and how the nodes are merged. The results are significantly better than those obtained by one-to-one mapping. However there is no consistent advantage of one heuristic over another. These recent efforts to generate an a multi-level threshold network use the ILP formulation intensively to determine the threshold nature and to get a set of feasible weights for the inputs and threshold. These methods rely on the Boolean network and hence will generate networks that are sub-optimal to a method that uses the factored form representation of the function as input. IV. P ROBLEM F ORMULATION Pattern: A pattern is a sequence of literals, parentheses and operators, which when they occur as a sub-string in a factored form, can be implemented as a threshold gate and the gate’s output can be replaced in place of this sub-string, without altering the function. Eg: ab + c is a pattern that can be implemented as a single three input gate (a, b, c are different literals). Now x+yz can be implemented as a gate in u+x+yz, but not in ux + yz. Maximally Factored Factor Form: A factored form is Maximally Factored, if: 1. For every sum of products, there are no syntactically equivalent factors in the product. 2. For every product of sums, there are no two syntactically eqivalent factors in the sums. A Maximal Sum of Product (MSOP) is a SOP which is not contained in any other SOP[6]. Eg. Consider the function H = abc(x + y + z + d) + e. Here x + y is not a MSOP, since it is part of x + y + z and x + y + z + d, but x + y + z + d is a MSOP. A Maximal Product of Sum (MPOS) is a POS which is not contained in any other POS. Eg. Referring to the previous example, we notice that abc(x + y + z + d) is a MPOS in H. Non-Extractable Factored Form: A non-extractable factored form is one in which no syntactically equivalent non-trivial factor1 occurs more than once in the factored form. Eg: (a + b)cd + ce is a non-extractable factored form. (a + b + c)d + (a + b)e is not non-extractable, as factor a + b occurs more than once. Three Input Threshold (Gate) Network (3ITN): A network of threshold gates in which each gate has a fan-in restriction of three. 1A

non trivial factor is a factor with more than one literal

A Factor Tree is a tree in which each node represents a MSOP or PSOP. The children of each SOP (POS) node are the POS (SOP) that make up the function of the node. A Trivial SOP has a pattern a or a + b. A Trivial POS has a pattern a or ab. The leaves of a factor tree represent either a trivial SOP or a trivial POS. Using the simplify command is SIS[5], Boolean combinational optimization is performed on the given function to generate a network of nodes. Then the print factor command is used to generate a maximally factored form for the function at each of these nodes. Use of the factored form as the input to generate the threshold network allows us to explore a larger solution space than a method that uses a Boolean network as input. Using the factored form as input, a threshold network that implements the function is generated. Two algorithms are proposed to generate a multi-level threshold network of any function. The first algorithm generates a 3ITN, using the factored form of the function at each node of the network generated by simplify. We show that this algorithm generates a gate optimal 3ITN for a single output function if a maximally factored, non-extractable factored form is used as input. The second algorithm uses a heuristic to generate a threshold network using gates of any size. Both of the above approaches rely on the identifying patterns in the factored form to detect threshold functions and to assign feasible weights to the inputs. This offers a significant improvement in computation complexity over the previous methods which use the ILP formulation for this purpose.

A factored form can be represented as a directed tree T (see Figure 2). Each node in T is either a MSOP node (represents a maximal SOP) or a MPOS node (represents a maximal POS). MSOP node and MPOS nodes alternate along any path from the root to a leaf. The leaf nodes are trivial SOPs (a+b and a) or trivial POSs (ab and a). By observing the allowable patterns, it is clear that each MPOS or MSOP must be reduced2 to one of the trivial forms before the parent node can be processed. We now explain the algorithm by means of an example. The algorithm traverses through the factor tree and processes the nodes in a bottom-up order. At each node, the algorithm synthesizes some threshold gates, reducing the function represented by its inputs to either a single literal or a pair of literals. The pair (a, b) can either represent the function (a + b) or ab depending on the kind of node at which it occurs as input. The algorithm can work on a node only when all of its inputs are either single literals or literal pairs. Initially, the nodes whose children are all leaves have this structure. The algorithm hence processes these nodes first. The algorithm deals with all the children of a node before working on the node itself. The algorithm can thus be designed to work recursively.

V. T HE 3ITN A LGORITHM The generate3ITN algorithm takes a factored form (which is not a trivial POS or a trivial SOP) as input and generates a 3ITN that will implement the factored form. The design of the algorithm is based on the observation that there are only seven different patterns of factored forms that can be implemented as a three input threshold gate. These allowable patterns are: abc, a+b+c, (a+b)c, a+bc, a(b + c) + bc, ab, a+b There are five patterns that have a support set of three, and two patterns with a support set of two. Here a, b and c are individual literals that occur in positive or negative form. It is straightforward to obtain the weights for negated literals by use of Throrem 5.1.6 in [9] (page 58).

Fig. 2.

Factor Tree of a Factored Form

Fig. 3.

The factor tree for m = (v ! + u + w)(g ! h! (f ! + i) + ef g)

Consider the function, m = (v ! +u+w)(g ! h! (f ! +i)+ef g). The factor tree for this factor form is shown in figure 3. It has 5 non-leaf nodes – P, S1 , S2 , P1 and P2 . Node P2 has three children, each of which is a single literal. P2 represents a product node ef g. A threshold gate implementing the function ef g is synthesized. The output of this gate (say A), becomes an input to node S2 . Node P1 has inputs g ! , h! and (f ! + i). A gate is synthesized to implement h! (f ! + i) (call the output of this gate B). The pair (B, g ! ) becomes an input to the node S2 . The inputs at node S2 are (B, g ! ) and A. These are combined, and a gate is synthesized for the function Bg ! + A. The output of this gate (C) is propagated to the parent node P . At node S1 a gate is synthesized for the function v ! + u + w and the output of this gate (D) is propagated to node P . At node P C and D are combined to generate a gate for function CD. 2 Reducing a node means to synthesize a 3ITN that will implement the function of the node. When a gate is synthesized, we replace the function of the new gate by a unique new literal in the factored form. This literal can be thought of as the output of the newly synthesized gate.

Since only seven patterns of literals can be mapped to a threshold gate, the weight assignment to each gate can be done trivially by pre-calculation of input weights and threshold. No ILP formulation is needed to calculate the feasible weights. The algorithm is listed for reference. The only detail in the working of the algorithm that the example doesn’t illustrate is the mapping of gates for pattern a(b + c) + bc. These patterns are identified in every maximal SOP and mapped to a gate (refer to 3-5, Algorithm 2). The SOPTGSyn and POSTGSyn call each other recursively and generate the 3ITN that implements the given factored form. The Synthesize function creates a gate for the function that is given as input, and assigns a unique symbol to the output of this gate. This symbol (literal) is returned to the calling function. Two lists listofOnes and listOfPairs is maintained by SOPTGSyn and POSTGSyn. The function addToList adds the input function to one of the two lists after checking how many literals it has. If the function has two literals then addToList adds it to the listOfPairs list, otherwise it adds it to the listOfOnes list. The combineLists function takes in the fuction φ as an input. This can either be AND or OR. This function is used to reduce the inputs of a node to either a single literal or a pair of literals. Algorithm 1 generate3ITN: Algorithm to generate a 3ITN from a factored form 1: INPUT: FF, a non-trivial factored form, of the function. 2: listOfOnes = [ ], listOfPairs = [ ] 3: if FF is a POS then 4: returnFF = POSTGSyn(FF) 5: else 6: returnFF = SOPTGSyn(FF) 7: end if 8: if noofLiterals(returnFF) = 2 then 9: returnFF = Synthesize(returnFF) 10: end if 11: return returnFF Algorithm 2 SOPTGSyn 1: INPUT: S, a Sum-of-Product 2: listOfOnes = [ ] listOfPairs = [ ] 3: for all Patterns X(a + b) + ab is S (where X is a factored form) do 4: Y = Synthesize(generate3ITN(X)(a + b) + ab) 5: Replace X(a + b) + ab in S, by Y. 6: end for 7: for all MPOS, P in S do 8: if P is a trivial POS then 9: addToList(P). 10: else 11: addToList(POSTGSyn(P)) 12: end if 13: end for 14: return combineLists(listOfOnes, listOfPairs, OR)

Algorithm 3 POSTGSyn 1: INPUT: P, a Product-of-Sums 2: listOfOnes = [ ], listOfPairs = [ ] 3: for all MSOP, S in P do 4: if S is a trivial SOP then 5: addToList(S). 6: else 7: addToList(SOPTGSyn(S)) 8: end if 9: end for 10: return combineLists(listOfOnes, listOfPairs, AND) Algorithm 4 combineLists 1: INPUT: listOfOnes, listOfPairs, φ 2: while Both lists are not empty do 3: if size(listOfOnes) = 1 and size(listOfPairs) = 0 then 4: return (listOfOnes.pop()) 5: else if size(listOfOnes) = 2 and size(listOfPairs) = 0 then 6: return (φ(listOfOnes.pop(), listOfOnes.pop()) 7: else if size(listOfOnes) = 0 then 8: addToList(Synthesize(listOfPair.pop()) 9: else if size(listOfPairs) = 0 then 10: Pop the top three elements of listOfOnes 11: addToList(Synthesize(φ (the three elements poped))) 12: else 13: addToList(Synthesize(φ(listOfOnes.pop(), listOfPairs.pop()))). 14: end if 15: end while We use SIS[5] to perform combinational optimization of the input network and to generate a multi-node network. Each node in this network represents a Boolean function. Using a maximally factored form for the function of each node, we apply the generate3ITN algorithm to get a 3ITN for each of them. Thus we can generate a 3ITN that will implement any multi-output function, when generate3ITN is used in conjunction with the optimization algorithms of SIS. VI. P ROOF OF G ATE O PTIMALITY The algorithm generate3ITN produces a minimal gate 3ITN that implements the given MFNE factored form. The algorithm first identifies all patterns of the type X(a + b) + ab (call it Pattern V . In Pattern V , X is any factored form and a and b are literals.) and generates 3ITNs for them. To do this, a 3ITN is generated for X, and the output of this network is used as an input to a three-input gate. The other two inputs to the gate are a and b, and the gate implements the function X(a + b) + ab. We first prove that any network that implements the MFNE factored form and ignores this pattern can be transformed to a network that will synthesize a gate for this pattern without increasing the number of gates. Consider a network that ignores at least one pattern V . Consider the pair of nodes S and P in T (Refer to Figure 4),

Fig. 4.

Pattern V in a factor tree.

in which the pattern X(a + b) + ab occurs, but is ignored. Let S and P be such that no other such pattern occurs in P. Now the node P outputs either a pair of literals or a single literal as input to S. If we choose to ignore (a + b), then we can get the same output pattern at the output of P, with one less three input gate. This is because in an optimal network, the number of two-input gates needed depends only on the number of single literal inputs to P (Appendix I). Thus we get the same effect with one less gate. If P outputs a pair, then to reduce it to a single literal we need an extra gate. The previously saved gate will compensate for this extra gate, thus so far our network transformation has not yielded any extra gates. Now the single literal output of P can be combined with the cube ab and a + b to implement X(a + b)ab in a single gate. Now we’ve used an extra gate, but also eliminated the gate to which ab was input. Thus, in transforming the optimal network into another one that uses pattern V , we preserve optimality. This can be done repeatedly to each pair P and S. Hence there exists an optimal network that uses all V that occur in the factored form. Our algorithm generates a network that maps all patterns of the type V . Now it is enough to prove that for a factored form that is independent of pattern V , our algorithm will still find the optimal mapping. A. Preliminaries From now on we consider MFNE factored forms that do not have pattern V . Each network that implements a factored form generates a labeling of the edges of the factor tree. We define the labeling as follows: If the MSOP or MPOS of the node is reduced to a single literal, then the output edge of the node is labeled as S (single). Otherwise, it is labeled as P (pair). If an edge is connected to a leaf, then the number of literals in the function of the leaf determines the label of the edge. If the leaf node is either pattern ab or (a + b) the edge label is P. Otherwise, it is S. Now consider an optimal network O and its corresponding labeling Lo . Our solution (call it A), generates a labeling La . An edge is said good if its labels in Lo and La are the same, otherwise it is said to be bad. We now define a coloring of the nodes of the factor tree as follows: A node in a factor tree is colored white if its input edges are good but the output edge is bad. If at least one input edge and the output edge are bad, then the node is colored grey. If all input edges are good, but the output edge is bad, then the node is colored black. All the nodes that are uncolored are the ones whose input and output edges are both good. Each node

also has a label N2 , which is the number of two input gates used to reduce the input at the node to the output at the node. For the nodes that are not colored it can be seen that A uses the exact same number of N2 nodes as O (The minimum N2 for optimal mapping is given in Appendix I). Therefore for the uncolored nodes N2O − N2A = 0. Now we uncolor all of the nodes by a series of transformations, thus transforming O to A. To show that A generates an optimal network, it is now enough to show that each of the intermediate networks generated by the transformation is not sub-optimal. This construction will prove that A will have no more two-input gates than O. But since O is optimal, by Theorem 1, A is also optimal. The network transformation done to uncolor nodes is explained in the next section. B. Network Transformations The colored nodes of the factor tree form a forest of trees. A typical tree is shown in Figure 5.

Fig. 5.

Coloring of the nodes of a factor tree.

Choose from any tree a subtree S, such that its root node has more than one child and all other non-leaf nodes have only one child. If no such sub-trees exist then all the trees in the forest are just simple paths, having the black node at one end, zero or more gray nodes, and a single white node at the other end. Consider a path of only grey nodes and a white node at the end (call it a grey-white path). From Appendix II, we know that for a white node the difference between the numbers of two input gates used for O and the number of two input gates used by A is 1. i.e if ON2 and AN2 are the number of two input gates synthesized by O and A respectively, then for a white node: ON2 − AN2 = 1. Similarly, it is shown in Appendix III that for a grey node: ON2 −AN2 = 2 or ON2 −AN2 = 0. Note that: ON2 −AN2 ≥ 0 for a grey node. For a grey-white path: ON2 − AN2 ≥ 1. It can be seen that the root of S has these grey-white paths as children. If each of these grey-white paths is replaced by the implementation of A (i.e for each node of these paths synthesize the gates as done by A), this will lead to a savings ≥ n in the number of two input gates. But such a replacement will change the input edge labels of the root node of S(which is either a black or grey node). But from Appendix I, it can be seen that from any input configuration, to get any form of output, we’ll never need more than 2 two-input gates. Now

replace the root of S, by an optimal implementation, that will result in the same output form as before. This will not take more than 2 extra two-input gates. Savings in 2-input gates by the replacement = n − 2. But n ≥ 2, thus savings in two input gates ≥ 0. This replacement will yield an implementation that as good or better than O. So far we’ve shown how to replace the entire sub-tree S, but not change the rest of the implementation. This replacement will uncolor3 the grey (non-root) and white nodes of S. If the root node was grey, it’s turned into white, and if the root node of S was black, then it gets uncolored. We can continue to replace the sub-trees of the form S. Such replacements will yield networks that implement the same function, but are no less optimal than O. After all the subtrees of the form S are processed and replaced we are only left with simple paths. These paths have a white node, a set of zero or more grey nodes and a black node at the end (a black-grey-white path). From Appendix IV, we know that a black node will not take more than one extra two-input node, if it’s made to align its implementation to that of A. i.e AN2 − ON2 ≤ −1, or ON2 − AN2 ≥ −1. For the rest of the grey-white path, we know: ON2 − AN2 ≥ 1. Hence for the entire black-grey-white path: ON2 − AN2 ≥ 0. This implies that replacing all of the nodes in the blackgrey-white path, by making them the same as the corresponding nodes of A, we are not sacrificing the gate optimality of the 3ITN. Such replacement can be viewed as uncoloring the nodes of the black-grey-white path. VII. T HE N -I NPUT G ATE H EURISTIC Based on the generate3ITN algorithm, we propose a heuristic to generate a threshold network using gates of any size. This algorithm recognizes threshold functions from the factored form using the following properties of threshold functions. 1) Boolean AND and OR functions are threshold. 2) If a Boolean function f (x1 , · · · , xn ) is threshold, then the function g(x1 , · · · , xn+k ) = f (x1 , · · · , xn )+xn+1 + xn+2 + · · · + xn+k is also threshold. 3) If Boolean function f (x1 , · · · , xn ) is threshold, then the function h(x1 , x2 , · · · , xn+k ) = f (x1 , x2 , · · · , xn ).xn+1 .xn+2 · · · xn+k is also threshold. We again use our previous example to illustrate how the generic n-input heuristic works. We assume a six-input restriction on the gates. The difference in the construction of the factor tree from the three input case is that we allow only literals to be the leaves of the tree. The factor tree for the function (v ! +u+w)(g ! h! (f ! +i)+ef g) is shown in Figure 6. Node S3 has f ! and i as inputs. This is a threshold function (a Boolean OR). Since this function has only two literals (less than the gate input restriction), no gate is synthesized and the function is propagated to node P1 . Node P2 propagates the threshold function ef g to node S2 . Node P1 has inputs g ! , h! and (f ! + i). The threshold function g ! h! (f ! + i) becomes an 3 An uncolored node is one whose incoming and outgoing edges have the same labels for both networks O and A.

Fig. 6.

The factor tree for m = (v ! + u + w)(g ! h! (f ! + i) + ef g)

input to the node S2 . The inputs at node S2 are (ef g) and (g ! h! (f ! + i). A gate is synthesized to implement g ! h! (f ! + i). The output of this gate is called A. The function A + ef g is propagated to node P . At node P two gates are synthesized to implement ef g + A (the output of this gate is B) and B(v ! + u + w). The calculation of weights for these threshold gates can be done by using the property used to identify them. See [13] (proof of Theorem 2) where calculation of weights for one such threshold function is given. Calculation of input weights is done in steps for each function. Thus this method does not use the ILP formulation to detect threshold functions or to calculate weights for the threshold gates synthesized. Example: In the above example, we show how weight assignment for the function B = ef g + A is done. At the node P2 weight assignment for function ef g is determined to be [1, 1, 1; 3] (here 1 is the weight associated with every input and 3 is the threshold). Now A is assigned a weight of 3 and the threshold still remains at 3. Thus the weight assignment for A + ef g is [3, 1, 1, 1; 3] (i.e wA = 3, we = 1, wf = 1, wg = 1, T = 3). VIII. E XPERIMENTAL R ESULTS Our experimental results are presented in this section. The experiments were run on a 1.42 GHz PowerPC G4 Apple iBook G4 with 1GB RAM running Mac OS X 10.4. We ran our experiments on approximately 50 MCNC benchmarks and compared our results with those of the previous work[13]. Table VIII contains a representative set of results. Our approach took less that one second to generate each of these circuits. The method in [2] which generates feed forward threshold circuits takes more than a minute to synthesize even small circuits of two threshold gates. Runtime is not reported for the method in [16] and the method in [13] takes about a second for each of the benchmark circuits. For the 13 benchmark circuits,

we obtained a gate count improvement of 14.14% and a level improvement of 24%. The level can be further improved by improving the heuristic and making it delay sensitive. TABLE I C OMPARISON WITH PREVIOUS RESULTS Benchmark b1 cm42a decod cm82a majority parity x2 cm85a cm151a cm162a cu cm163a cmb

R Zhang et. al Gates Levels 8 3 13 3 24 3 12 4 1 2 45 9 15 4 14 5 12 5 26 8 24 4 25 6 27 6

6-Input Heuristic Gates Levels 5 4 10 1 16 1 12 2 4 3 30 2 25 5 17 5 16 5 18 4 23 3 19 6 20 9

Difference Gates Levels -3 -1 -3 2 -8 2 0 2 3 -1 -15 7 10 -1 3 0 4 0 -8 4 -1 1 -6 0 -7 -3

Next we compare our implementation (six-input gate) with the heuristics proposed in [16]. The comparison is again not fair as the metric used for gate area in the two methods are different. We use a metric of input size for gate area, whereas Zhang et. al.[16] use sum-of-weights (SOW) as a metric for gate area. However, it can be seen from Table VIII, that the results are comparable. TABLE II C OMPARISON WITH PREVIOUS RESULTS Benchmark b1 cm42a decod cm82a majority parity cm163a cu

L Zhang et. al (SOW < 100) Gates + Inverters Levels (9, 10, 9, 9) (2, 2, 2, 2) (10, 10, 10, 10) (1, 1, 1, 1) (16, 16, 16, 16) (1, 1, 1, 1) (11, 11, 8, 8) (3, 3, 3, 3) (1, 7, 1, 1) (1, 2, 1, 1) (31, 40, 23, 30) (5, 5, 5, 5) (17, 20, 17, 17) (2, 3, 3, 2) (22, 25, 20, 22) (3, 3, 3, 2)

6-Input Heuristic Gates Levels 5 4 10 1 16 1 12 2 4 3 30 2 19 6 23 3

The approach proposed in [16] has four different heuristics. The table gives the result of execution of all four heuristics. IX. C ONCLUSION In this paper, we propose a new methodology for the synthesis of threshold networks. We give two versions of the algorithm. One algorithm is for the synthesis of 3ITN, and another for the synthesis of threshold networks using gates of any size. The generate3ITN algorithm is shown to synthesize a minimal gate network for a single output function having a maximally factored, non-extractable factor form. The heuristic n-gate algorithm is compared with the previous algorithms that synthesize threshold networks. The uniqueness of this approach is in the use of a non-ILP based method to detect threshold networks and to assign weights to threshold gates. As compared to [13] we get a 14.14% improvement in gate count and a 24% improvement in delay. The heuristic can be improved to look for a greater variety of patterns that represent threshold gates. Right now, the focus is on reducing the gate count. The heuristic can be extended to generate delay optimal networks and solutions with area-delay trade-offs.

A PPENDIX I This section lists the minimum number of two input gates required to reduce different inputs that can occur at any node of the factored tree to one of the two output forms (single literal or pair). The different configurations of input and output forms are listed in Table IX. The number (minimum) of two input gates that will be required for each case is enumerated. TABLE III N UMBER OF N2 S REQUIRED FOR OPTIMAL IMPLEMENTATION n4 Odd Odd Even Even (n ≥ 2) Even (n = 0)

Output Form Single Literal Literal Pair Single Literal Literal Pair Literal Pair

N2min 5 0 1 1 0 2

A PPENDIX II This section investigates the difference in the number of two-input gates of O and A (ON2 − AN2 ) for the different input combinations that occur at a white node of a factor tree. Let n be the number of single literal inputs at the node, and m be the number of inputs to the node that occur as pairs. CASE 1: n = 0. A will reduce the output to the form a, and will use one two input gate. O will reduce the output of the node to a pair (this is because in a white node the output format of A and O are different). For this O will use two two-input gates. Thus, ON2 − AN2 = 1. CASE 2: n > 0, n is even. A will reduce the output to a pair of literals, and will not use any two input gates. O will reduce the output of the node to a single literal form. For this O will use one two-input gate. Thus, ON2 − AN2 = 1. CASE 3: n > 0, n is odd. In this case, A will reduce the output to a single literal, and will not use any two input gate. O will reduce the output of the node to a pair and will use one two-input gate. Thus, ON2 − AN2 = 1. A PPENDIX III This section investigates the difference in the number of two-input gates of O and A (ON2 − AN2 ) for the different input and output combinations that can occur at a grey node of the factored tree. In all of the following cases, the value of n specified describes the input configuration that occurred for A. In O, this value of n will change by ±1. CASE 1: n = 0. A will reduce the output to a single literal, using one two-input gate. O will get an input with n = 1, and will reduce it to a pair of literals using one two input gate. For this case: ON2 − AN2 = 0. CASE 2: n = 1. A will reduce the output to a single literal, without using any two-input gate. O will: a. Get an input configuration, with n = 2 and reduce it to a pair of literals using zero two input gates. For this case: ON2 − AN2 = 0. 4 Number

and nature of single literal inputs (n). number of two input gates required.

5 Minimum

b. Get an input configuration with n = 0 and reduce it to a pair of literals using two two-input gates. For this case: ON2 − AN2 = 2. CASE 3: n ≥ 2. n is odd. A will reduce the output to a single literal, without using any two-input gates, O will now get an input where n is even and will reduce the function of the node to a pair of literals without using any two-input gates. For this case: ON2 − AN2 = 0. CASE 4: n ≥ 2. n is even. A will reduce the output of this node to a pair of literals, without using two-input gates. O will get an input where n is odd and reduce the function of the node to a single literal without using any two-input gates. For this case: ON2 − AN2 = 0. A PPENDIX IV This section finds the difference in the number of two-input gates that get synthesized by O and A (ON2 − AN2 ) for the different input combinations that can occur at a black node of the factored tree. CASE 1: Output form is single literal. Refer to Appendix I. If A gets an input with n being odd, A will take no two-input gate to reduce it the output to a single literal form (AN2 = 0). Now, O will get an input where n is even, and will reduce it to a single literal output. In this case ON2 = 1, and so ON2 − AN2 = 1. If A gets an input with n being even, then ON2 −AN2 = −1 CASE 2: Output form is a literal pair. If A gets an input with odd n, then A will take one two-input gate to reduce the output to a literal pair (AN2 = 1). Now, O will get an input where n is even with either: a. n = 0 or b. n > 0 In the first case ON2 = 2, and ON2 − AN2 = 1. If the reverse happens, i.e A gets an input with n = 0 and O gets an input with odd n, then ON2 − AN2 = −1. In the second case, ON2 = 0 ∴ ON2 − AN2 = −1. If the reverse happens, i.e A gets an input with even n, and n > 0 and O gets an input, with odd n, then ON2 − AN2 = 1. Thus for a black node, ON2 − AN2 = ±1. A PPENDIX V Consider a MFNE factored form that is free of the patterns of the form a(b + c) + bc. The following properties hold for all the 3ITNs that implement such a factored form: Lemma 1: For a 3ITN, having N2 two-input and N3 threeinput gates, implementing a MFNE factored form of " literals: N2 + 2N3 = " − 1. Proof: A three input gate reduces the number of literals in the factored form by 2, and a two input gate reduces the number of literals by 1. The function in its factored form has " inputs, and this is reduced to one output literal by the network. Hence the statement of the lemma is true. Theorem 1: Any gate optimal 3ITN implementing a MFNE factored form has the minimal number of two input gates among all 3ITNs implementing the same factored form. Proof: Let N2 and N3 be the number of two input and three input gates respectively in a gate optimal 3ITN that has Kmin gates. Now, N2 + 2N3 = " − 1, where " is the number

of literals in the factored form [From theorem 1]. Consider another minimal gate network that has atleast one less two input gate. Assume it has N2 − 2a two input gates6 , where a > 0. Then, it should have N3 +a three input gates (Obtained by using Lemma 1). The total number of gates in this second network is thus N2 −2a+N3 +a = N2 +N3 −a = Kmin −a. This second network has fewer gates than the optimal 3ITN, which is a contradition. Thus our assumption that there can be a network with fewer two input gates than the optimal gate network is not true. Thus the gate optimal 3ITN has a minimum number of two input gates among all 3ITNs implementing the same factored form. Corollary 1: The threshold network that implements a MFNE factored form and has the least number of two-input gates is a gate optimal network. R EFERENCES [1] Semiconductor Industries Association Roadmap. [2] M. Avedillo and J. Quintana. A Threshold Logic Synthesis Tool for RTD Circuits. In Euromicro Symposium on Digital System Design, 2004. [3] E. P. Blair and C. S. Lent. Quantum-dot cellular automata: an architecture for molecular computing. In Proc. of SISPAD 2003. [4] M. Dertouzos. Threshold Logic: A Synthesis Approach. MIT Press, 1965. [5] E. M. Sentovich et al. SIS: A System for Sequential Circuit Synthesis. Technical Report UCB/ERL M92/41, Dept. of EECS, UCB, 1992. [6] G. D. Hachtel and F. Somenzi. Logic Synthesis and Verification Algorithms. Boston: Kluwer Academic Publishers, 1996. [7] Z. Kohavi. Switching and Finite Automata Theory. New York: McGrawHill Book Company, 1970. [8] K. K. Likharev. Single-electron devices and their applications. Proceedings of the IEEE, 87(4):606–632, 1999. [9] S. Muroga. Threshold Logic and Its Applications. New York: WILEYINTERSCIENCE, 1971. [10] P. Celinski et al. State of the art in CMOS threshold logic VLSI gate implementations and systems. In Proc. of the SPIE, pages 53–64, 2003. [11] P. Mazumder et al. Digital circuit applications of resonant tunneling devices. Proceedings of the IEEE, 86(4):664–686, 1998. [12] R. Zhang et al. Synthesis of Majority and Minority Networks and Its Applications to QCA, TPL and SET Based Nanotechnologies. In VLSID’05, pages 229–234, 2005. [13] R. Zhang et al. Threshold Network Synthesis and Optimization and Its Application to Nanotechnologies. In IEEE Transactions on CAD, 2005. [14] S. K. Shukla and I. R. Bahar. Nano, Quantum and Molecular Computing. Kluwer Academic Publishers, Norwell, MA, USA, 2004. [15] R. O. Winder. Threshold Logic. PhD thesis, Princeton University, 1965. [16] L. Zhang. Threshold Logic Network Synthesis Suite. Master’s thesis, Delft University of Technology, 2005.

6 The difference between N ’s in any two gate optimal networks can’t be 2 odd. Proof: Let N2a and N3a are the number of two and three input gates for an optimal network, and N2b and N3b are the number of two and three input gates for another optimal network. From the first Lemma: N2a + 2N3a = !−1 and N2b +2N3b = !−1. Subtracting the two equations, and reordering, we get. N2a − N2b = 2(N3b − N3a ) The right hand side is an even number and hence the left hand side is also even.