A novel class of serial-parallel redundant signed-digit ... - IEEE Xplore

A NOVEL CLASS OF SERIAL-PARALLEL REDUNDANT SIGNED-DIGIT MULTIPLIERS

G. Privat Centre National d'Etudes des Tilicommunicntians CNET-Grenable, B P 98, 38243 Meylnn Cedex, FRANCE ABSTRACT

New digit-serial multiplier structures, operating most significant digit first with a redundant radix 2 representation, are introduced. They achieve optimal performance with regard to the latencythroughput tradeoff. Their hardware complexity is shown to be lower than classical multipliers operating least significant bit first. A general derivation shows them to be the only canonical structures having these properties. I. INTRODUCTION

The benefits of digit-serial operation in the context of digital signal processing fixed-function VLSI architectures have been widely publicized [1,21 : fine-grain operators, easily pipelined down to the bitlevel, making a high degree of functional parallelism possible, with reduced on-chip communication cost, enhanced testability and faulttolerance. Another less frequently emphasized advantage of bit-serial is the possibility to overcome the feedback loop bottleneck in computational structures where the maximum throuhgput is strictly limited by an iteration bound [31, as is the case in recursive digital filtering [4,5,6]. Consider a loop in a signal flow graph architecture, with d word delays (z-l), and k operators, each with a critical path of p cascade elements and a latency of q. A total of kp delays are needed to fully pipeline the loop. In bit-parallel, only d-kq delays are available, whereas in bitserial we have wd-kq, if w is the original word-length. If wd