A Simple Method for Capacitor Voltages Balancing of ... - IEEE Xplore

A Simple Method for Capacitor Voltages Balancing of Diode-Clamped Multilevel Converters Using Space Vector Modulation Mehdi Narimani1, Venkata Yaramasu1, Bin Wu1, Navid Zargari2, George Cheng2, Gerry Moschopoulos3 1 Ryerson University, Toronto, Canada 2 Medium Voltage R&D Department, Rockwell Automation, Canada 3 University of Western Ontario, London, Canada Abstract— This paper presents a new and simple method for capacitor voltages balancing of an n-level diode-clamped multilevel converters using space vector modulation (SVM). The proposed method introduces a generalized approach to calculate dc-link capacitor currents without the use of look-up tables for an n-level diode-clamped converter. This approach balances dc-link capacitor voltages based on minimum energy property. The performance of the proposed method has been studied for a three-level, four-level and five-level diode-clamped converter in MATLAB/Simulink environment. Keywords—multilevel converter; diode-clamped converter; dc–ac power conversion, space vector modulation (SVM).

I. INTRODUCTION The multilevel voltage source converters are the most suitable converters for medium voltage, high power applications, because of many attractive features, such as; high voltage capability, reduced common mode voltages, near sinusoidal outputs, low dv/dt’s, and smaller output filters [1][6]. Various modulation strategies have been developed and studied for multilevel inverter topologies [7]-[14]. Since the multilevel converters are intended to be used in highpower/high voltage applications; there are two major challenges in selection of modulation strategies; high power quality and minimum switching frequency. One of the modulation strategies that are more preferred for high power multilevel converters is space vector modulation (SVM). The SVM method has flexibility in selecting and optimizing switching states for both harmonic minimization and dc-link capacitor voltage balancing [9]-[14]. Several SVM algorithms with simplified calculations have been proposed in the technical literatures [9]-[11]. A common characteristic to all SVM-based schemes is that the modulation algorithm is divided into the following steps; transform the reference or modulating vector into α-β coordinate systems, identify the sector where the reference vector is located, determine the adjacent switching vectors, duty-cycle calculation, determine of redundant switching state combinations, select the best switching states based on defined cost function and finally generate the gating signals for the nlevel converter. By selecting suitable cost function and gating signals pattern, this approach can be extended to n-level multilevel converter.

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For an n-level diode-clamped multilevel converter, as shown in Fig. 1, the main aim of the cost function is to select the best switching states to generate the output voltages and at the same time keep the voltage of dc-link capacitors to be balanced. The work in [10] demonstrate the balancing of the dc-link capacitor voltages for a five-level diode clamped converter using SVM and based on minimum energy property of the dc-link capacitors. In order to minimize the cost function to balance dc-link capacitors, the current of dc-link capacitors should be measured. However, to reduce the cost and complexity associated with the current sensors, the authors in [10] proposed to use the dc-side intermediate branch currents instead of capacitor currents for a five-level diode-clamped converter. In this method, the relationship between the dc-side intermediate branch currents and the output currents has been obtained based on a table defined for different switching states. For a given five-level diode-clamped converter, with 32 switching states and three dc-side intermediate branch currents, the dimension of this table is 32×3. If the number of level increases, the number of dc-side intermediate branches and number of switching states will increase. For an n-level diode clamped converter, the dimension of that table is 2 × − 1 and thus, the complexity of the dc-link current calculations increases significantly. In this paper, a new, simple and generalized method is proposed to calculate the dc-link capacitor currents for an nlevel diode-clamped converter. The proposed approach eliminates the use of look-up tables, and thus greatly reduces the complexity of the control algorithm. Instead of estimating the intermediate dc-currents, the proposed method calculates the dc-link capacitor currents. The performance of the proposed method has been studied for a three-level, four-level and five-level diode-clamped converter in MATLAB/Simulink environment. II. REVIEW OF SVM FOR AN n-LEVEL DIODE-CLAMPED MULTILEVEL CONVERTER In this section, the procedure for the implementation the SVM strategy for an n-level multilevel converter is summarized based on works in [3], [9], [10]. This procedure has the following steps;

310

Fig. 1. A Three-Phase n-Level Diode-Clamped Converter.

A. Determine the location of the reference vector: The first step is to determine the location of reference vector in α-β coordinate systems, as shown in Fig. 2. A voltage reference vector that is to be synthesized with the help of switching vectors can be presented in the following vector form; sin +! 2" − $3 + ! & (1) | sin = =| sin − 4"$3 + !

'

'=

√3 ). 2

,-

where, m is the modulation index and . is the input voltage. In order to find out the closest switching vectors to the reference vector, the following transformation should be done;

1 0 0 0 0 /

1 1 0.5 : 3 9 0 4 9 = 0 −0.5= 59 0 −1 69 0 −0.5 / 0.5 78

2

−0.5 0.5 1 0.5 −0.5 −1

−0.5 −1 : 9 =−0.59 0.5 9 1 9 0.5 8

(2)

The largest > and the second largest > , k=1,2,…,6 uniquely specify the two space voltage vectors adjacent to the . For example, if the two largest > 's, are ? and ?@2 , (as shown in Fig. 3) the two switching vectors which synthesize the output voltage are ? and ?@2 . The corresponding indices of ? and ?@2 specify the sector number in which the tip of

Fig. 2. Space vector diagram of an n-level converter

is located within, as shown in Fig. 2. For triangle identification, reference vector is projected on the axes of 60ocoordinate system, as shown in Fig. 3. ? and ?@2 can be obtained as follow; 2 −1 2 ? − ?@2 ? = 3 . (3) 2 −1 − ? + 2 ?@2 ?@2 = 3 .

311

Table I: RELATIONSHIP BETWEEN SWITCHING STATES IN SECTORS I TO VI

Sector I II III IV V VI

Phase A i -j + (n-1) k -i + (n-1) j -k + (n-1)

Phase B j -k + (n-1) i -j + (n-1) k -i+ (n-1)

Phase C k -i + (n-1) j -k + (n-1) i -j + (n-1)

C. Determination of switching states corresponding switching vectors: For a given switching vector E = F2 , F3 , the available switching states can be determined by; Fig. 3. Finding the triangle which

is located within

The reference vector VBCD lies in a parallelogram formed by vertices A,B,C, and D, (Fig. 3) and, E = F2 , F3 H = F2 + 1, F3 (4) I = F2 , F3 + 1 J = F2 + 1, F3 + 1 where; F2 = KLMMN ? (5) F3 = KLMMN ?@2 and KLMMN . is a lower rounded integer function. The following criterion determines if the reference vector is located in a triangle formed by either A,B, and C or B,C, and D vertices. where n is the number of levels.

is in ∆ ABC if: is in ∆ BCD if:

?

?

+ +

?@2

?@2

+ H ,H + I ,I = ,E + ,H + ,I = X

X

(7)

where T is the switching period and ,E , ,H and ,I are the duty-cycles of switching vectors E , H and I . Thus [10]; ,H = c ? − F2 dX , =c (8) ?@2 − F3 dX ,E = X − ,H − , and if the tip of the reference voltage vector lies in the BCD triangle; ,H = cF3 + 1 − ?@2 dX , = cF2 + 1 − (9) ? dX ,J = X − ,H − ,

(10)

D. DC-capacitors voltage balancing based on minimum energy property: Eq. (10) shows that for a given switching vector, there are redundant switching states. Redundant switching states can be used to carry out dc-link capacitor voltages balancing task for an n-level diode-clamped converter. In an n-level diode clamped converter, the total energy of (n-1) capacitor can be calculated by [10]; p2

1 o 2 ?

mI = n

< F2 + F3 + 1 ≥ F2 + F3 + 1 (6)

B. Duty cycle calculation: If the tip of the reference voltage vector lies in the ABC triangle formed by E , H and I , the three switching vectors adjacent to the reference voltage vector, therefore, E ,E

e, f, g = ℎ, ℎ − F1 , ℎ − F1 − F2

ℎ, ℎ − F1 , ℎ − F1 − F2 ∈ j0,1,2, … , − 1l The determined switching states are based on the switching states of sector I. For the other sectors, the switching states can be determined simply by interchanging the switching states of sector I to other sectors based on Table I.

where;

.I

?q2

p2

= n ?q2

I?

3

(11)

I?

If all the dc-link capacitors are identical and are equal to C, based on minimum energy property of a balanced n-level diode-clamped converter, the total energy mI has its minimum of p2 (12) 1 . 3 n o 2 −1 ?q2

In order to achieve voltage balancing, the cost function J can be defined; p2 (13) 1 r = n o ∆ 3? 2 ∆

where;

?q2

=

−

.

−1 The mathematical condition to minimize J is;

312

p2

,r = n o∆ , ?q2

I?

I?

, I? =n ∆ I? , p2

?q2

I ? eI ?

≤0

(14)

(15)

where eI ? is the current of capacitor o? . Applying the averaging operator over one sampling period to (14) results in; p2

where, ∆

I?

n ∆ ?q2

I?

g eI ? g ≤ 0

(16)

g is the voltage drift of o? at sampling period k,

and eI? g is the averaged value of the ith capacitor. It has been shown in [10] that for a five-level diode-clamped inverter, condition (16) can be written as; 4

where, ∆

I?

n∆ ?q2

I?

4

g n et g tq?

≥0

(17)

g is the voltage drift of o? at sampling period k,

and et g is the averaged value of the ith dc-side intermediate branch. The current et g for u = 1,2,3 can be calculated based contributions of switching states to the ac-side currents, ia, ib, and ic which can be obtained based on a table as shown in [10]. The condition (17) can be generalized for any n-level diode-clamped converter, however, calculation of et g for u = 1,2, … , − 2 (as shown in Fig. 1) based on contributions of switching states to the ac-side currents is not an easy task, even for a five-level converter. This paper proposes to use directly capacitor currents instead of dc-side intermediate currents and also proposes a generalized method to calculate capacitor currents without the use of trigonometric calculations or look-up tables for an nlevel diode-clamped converter. It should be noted that if the dc-link capacitor currents can be calculated for different combinations of adjacent redundant switching states over a sampling period, the best combination which minimize (16) should be chosen to achieve dc-link capacitor voltages balancing. In the next Section, calculation of dc-link capacitor currents will be explained. III. CALCULATION OF DC-LINK CAPACITOR CURRENTS FOR AN N-LEVEL DIODE-CLAMPED CONVERTER Assume a three-level diode-clamped inverter as shown in Fig. 4. Based on kirchhoff’s law; ev + e2 + e3 = 0 (18) e 3 = e. − e3 e 2 = e 3 − e2 =e. − e3 − e2 The common current, e. , through all capacitors is not considered in the process since it does not contribute to voltage drift of capacitors. Therefore, (18) can be simplified as (19); e 3 = −e3 (19) e 2 = −e3 − e2 The relationship between ew , e2 , and e3 and output currents e , e , and e can be written as follow; ew = x w e +x w e + x w e e2 = x 2 e +x 2 e + x 2 e (20) e3 = x 3 e +x 3 e + x 3 e

Fig. 4. Schematic of a three-level diode-clamped converter.

where; x defined as;

?

, x ? , and x ? ∈ j0,1l , e = 0,1,2 and can be 1 xt? = y 0

eK

t

eK

t

=e ≠e

=

(21)

u = {, |, - and , e = 0,1,2 is the voltage level of the phase x, based on switching t states, as shown in Table II. By substituting (20) in (19), the relationship between capacitor currents and output current can be written as follow; eI2 = }2 e +}2 e + }2 e eI3 = }3 e +}3 e + }3 e

(22)

where }3 , }3 , and }3 ∈ j0, −1l and these values can be determined based on the voltage level of the phase x, ( t as shown in Table II. These coefficients can be written as;

}2t = ~e• 0 − t }3t = ~e• 1 − t . ~e• t (23) u = {, |, where; ~e• . function is; −1 eK € < 0 ~e• € = y 0 eK € = 0 = (24) 1 eK € > 0 Finally, currents of dc-link capacitors for a three-level diode-clamp converter can be written as; e e ‚ I3 ƒ = „4… t e (25) eI2 e

313

TABLE II RELATIONSHIP BETWEEN VOLTAGE LEVEL, SWITCHING STATES AND CAPACITOR CURRENTS Voltage Level Vx , (x=a,b,c) 2 1 0

Sx1

Sx2

VxN

K2x

K1x

1 0 0

1 1 0

Vc1+Vc2 Vc1 0

-1 0 0

-1 -1 0

where the elements of „

} }3 }3 „4… t = ‚ 3 ƒ (26) }2 }2 }2 and the elements of „4… can be calculated by (23). As can be seen, capacitor currents can be calculated just based on distribution of voltage level of each phase on output currents. In order to calculate the average value of capacitor currents, the averaging operator over one sampling period should be applied to (25) results in;

where;

eI3 ‡= eI2 (27) e e e „4… E e ,E + „4… H e ,H@ „4… I e ,I e e e where, eI3 and eI2 are the average value of capacitor currents and ,E , ,H and ,I are the duty cycles of three adjacent switching vectors , , and respectively. ,E , ,H and ,I can be calculated based on (8) or (9). , , and can be determined from (4). Therefore, the dc-link capacitor currents can be calculated for different combinations of adjacent redundant switching states over a sampling period based on (27), (26) and (23) without the need of any table. The best combination which minimizes (16), should be selected to balance dc-link capacitor voltages. This procedure can be generalized for an n-level diodeclamped converter and the relationship between capacitor currents and output currents can be written as;

e „… E e e where; „ … is; „

…

t

} p2 1 0} p3 =0 ⋮ 0 }3 / }2

} }

p2

p3

⋮ }3 }2

…

} }

I p2

p3

⋮ }3 }2

IV. SIMULATION STUDIES In order to show the performance of the proposed method, simulation studies have been done in MATLAB/Simulink environment. The simulation studies demonstrate the effectiveness of the developed SVM strategy to balance the voltages of dc-link capacitors. The performance of the proposed method has been studied for a three-level, four-level and five-level diode-clamped converter with parameters shown in Table III. These simulations are shown in Fig. 5 to7. The simulation results validate the proposed strategy. V. CONCLUSION

(28)

e e e

,I

: 9 9 9 8

This paper presents a new and simple method for capacitor voltages balancing of n-level diode-clamped multilevel converters using space vector modulation (SVM). TABLE III PARAMETERS OF THE STUDY SYSTEM

(29)

}2t = ~e•

}3t = ~e• 1 −

} }

p3 t p2 t

= ~e• = ~e•

can be calculated by (30).

Finally, the proposed approach to implement dc-link capacitor voltages balancing for an n-level diode clamped converter has the following steps; • Identify the sector and triangle where reference vector is located in α-β coordinate system; Eq. (1)-(6). • Determine the adjacent switching vectors; Eq. (4),(6). • Duty-cycle calculation; Eq. (8) or (9). • Determine of redundant switching state combinations; Eq. (10). • Calculate the average capacitor currents; Eq. (28)-(30). • Select the best switching states based on minimization of Eq. (16). • Generate the gating signals for the n-level converter. This procedure simplifies the implementation of SVM strategy for an n-level diode clamped converter and there is no need to have any look-up tables.

†

1 eI p2 : 0 eI p3 9 0 ⋮ 9= 0 9 0 eI3 9 / eI2 8 e ,E + „ … H e ,H@ „ e

…

}4t = ~e• 2 − −3 − −2 −

t t

. ~e• . ~e•

t

. ~e•

⋮

t t

0− t

. ~e• . ~e•

u = {, |, 314

Converter Parameters Converter Rating DC-Link Capacitors Input DC voltage Output frequency t

. ~e• t

. ~e• t t

t

t

−1

− 1 . … ~e• − 1 . … ~e•

t t

− −

Values 50 KVA 2200 µF 1800 V 60 Hz

−3 −2

(30)

Inverter Line Voltages (V)

2000 1000 0 -1000 -2000

0.02

0.03

0.04

0.05

0.06

0.07

0.08

(a) inverter output voltage (Vab) DC-Link Capacitor Voltages (V)

1000 950

VI. REFERENCES

900

[1]

850 800

0.02

0.03

0.04

0.05

0.06

0.07

0.08

(b) voltage of dc-link capacitors (VC1, VC2) Fig. 5. Three-level diode-clamped converter. Inverter Line Voltages (V)

2000 1000 0 -1000 -2000

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.07

0.08

DC-Link Capacitor Voltages (V)

(a) inverter output voltage (Vab) 700 650 600 550 500

0.02

0.03

0.04

0.05

0.06

(b) voltage of dc-link capacitors (VC1, VC2, VC3) Fig. 6. Four-level diode-clamped converter. Inverter Line Voltages (V)

2000 1000 0 -1000 -2000

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.07

0.08

(a) inverter output voltage (Vab) DC-Link Capacitor Voltages (V)

The proposed method uses minimum energy property to balance dc-link capacitors of an n-level diode-clamped converter. Unlike the conventional method, the proposed method does not need to calculate dc-side intermediate branch currents. The proposed method introduces a generalized approach to calculate directly dc-link capacitor currents without the use of look-up tables. The performance of the proposed method has been studied for three, four, and fivelevel diode-clamped converter in MATLAB/Simulink environment. The proposed strategy can be easily extended to any n-level diode-clamped multilevel inverter.

550 500 450 400 350

0.02

0.03

0.04

0.05

0.06

(b) voltage of dc-link capacitors (VC1, VC2, VC3, VC4) Fig. 7. Five-level diode-clamped converter.

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