Characterization of radiation-induced SRAM and logic soft errors from ...

Characterization of Radiation-Induced SRAM and Logic Soft Errors from 0.33V to 1.0V in 65nm CMOS Robert Pawlowski1, Joseph Crop1, Minki Cho2, James Tschanz2, Vivek De2, Thomas Fairbanks3, Heather Quinn3, Shekhar Borkar2 and Patrick Yin Chiang1 1

School of EECS, Oregon State University, Corvallis, OR, USA; 2Intel Corporation, Hillsboro, OR, 3 USA; Los Alamos National Laboratory, Los Alamos, NM, USA

Abstract — This work details a process-portable test chip, fabricated in 65nm CMOS, specifically designed to measure radiation-induced soft error rate (SER) during operation at near-threshold. A variety of SRAM, register file (RF), and digital logic test structures are included that provide a comprehensive assessment of circuit sensitivities to radiation at low VDD. Neutron irradiation measurements of SRAM/RF show a 6.45x increase in SER when VDD is lowered from 1.0V to 0.33V, and a 2.6x increase in multi-bit upsets. Alpha bombardment of digital logic tests demonstrates the effectiveness of this test chip platform in characterizing the relationship between SER and different circuit characteristics when operating at low VDD. Index Terms — logic, memory, near-threshold, reliability, soft errors.

I. INTRODUCTION Operating integrated circuits in the near-threshold regime has become a viable design consideration, due to the significant improvement in energy efficiency [1]. Many applications, such as biomedical devices and unmanned drones, demand low power and therefore could benefit from near-threshold operation. These devices also require the highest level of reliability, as unexpected errors could produce devastating results. Disadvantages of low VDD operation, such as decreased performance and increased sensitivity to variation, are well known. However, little prior work has been performed to quantify and explain the correlation between radiation-induced soft error rate (SER) and low VDD operation. While the basic approach to the relationship between SER and VDD is linear, many simulation models show more complexity based on the circuit response [2]. The non-linear operation of the transistor at low voltage could further complicate its soft error susceptibility and the resulting simulation model. The goal of this work is to characterize and understand the relationship between near-threshold operation and radiation-induced soft errors. Custom test circuits have been developed and tested under neutron and alpha radiation, with memory and logic measurement results that show SER versus VDD that have not been previously performed. This test platform, portable to future advanced processes, can help inform future IC designers about the

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design tradeoffs between circuit design, technology, low VDD operation, and SER.

process

II. BACKGROUND A. Related Work As previously mentioned, limited work has been done to specifically understand the relationship of VDD on soft errors. Researchers in [3] have done a thorough investigation of neutron-induced SER in SRAM. They find an 18% increase in 90nm SRAM SER for every 10% decrease in VDD down to 0.7V, staying well above the threshold voltage. An in-depth experiment in [4] of a 10T sub-threshold SRAM in 65nm finds a 7.8X increase in SER after scaling VDD from 1.0V down to 0.3V. Even less experimental research has been presented for combinational logic SER. Existing work indicates that logic SER compared with FF SER at nominal VDD may range from ~10% in 180nm [5] to 1% in 32nm [6]. This discrepancy, combined with a significant lack of research on low-VDD logic SER and the simulated prediction of a logic SER increase with process scaling [7], explains the need for experimental combinational logic SER data across both process and voltage. B. Soft Error vs. VDD Simulations To better understand how circuits respond to a radiation-induced current pulse as VDD scales, SPICE simulations were performed on post-layout netlists of the 6T SRAM bitcell and a chain of 8 inverters. The setups (Fig. 1) use an independent current source to act as a ‘strike’ on the off NMOS in both test cases. Fig. 1 shows the trend of upset-inducing pulse duration vs. VDD for 5 different current magnitudes. For the SRAM (Fig. 1a), a long (~200ps), low (5 µA) pulse can induce an upset at VDD=0.3V. As VDD increases, the required pulse duration increases to overcome the cross-coupled inverter feedback. The switching threshold of the inverters also increases to the point where the magnitude of the current pulse is insufficient to induce an upset at any pulse duration. Upsets do not occur at VDD=1V until the current pulse reaches 40µA, with a 300ps duration.

A variety of unique logic chains were implemented onchip to isolate and analyze the VDD vs. SER relationship of different circuit characteristics. These characteristics include: inverter static noise margin (SNM); NAND vs. NOR-based logic, focusing on differences in the cell design that can lead to higher SER; and inverter size vs. transient pulse propagation. (a) (b) Fig. 1. Pulse duration Vs. VDD simulations for 5 current magnitudes on a 6T bitcell (a) and chain of 8 inverters (b).

At VDD=0.3V, the minimum pulse duration required to generate a transient propagation for a least 8 inverter stages (Fig. 1b) is ~2x smaller than an upset-inducing pulse in SRAM. As VDD increases, the strength of the inverter driving the sensitive node and a rise in logic switching threshold prevent errors from occurring. While a 5µA pulse can still cause an error at VDD=0.3V, a 40µA pulse cannot induce a transient error above VDD=0.75V, showing that combinational logic experiences a significant increase in soft error sensitivity as VDD decreases. III. RADIATION TEST CHIP IMPLEMENTATION The full chip implementation is shown in Fig. 2. The test-chip includes both 6T and 8T [8] memory cell arrays with address decoders that utilize logical masking to prevent unexpected cell access due to a radiation event. The output of each individual digital logic test is levelshifted to 1V and monitored with a 5-bit counter, hardened through the use of DICE latches [9]. All tests use their own scan-interface for input/output, with triple modular redundancy to detect any errors that may have occurred during scan-out.

(a)

Fig. 3. Static noise margin test chains (a) and simulated switching thresholds (b).

Fig. 3a shows the SNM test implementation. Each chain consists of 32 inverters symmetrically sized to maintain identical switching thresholds within each node of the chain. The margins tested ranged from 20%-80%, in increments of 15%. The simulated input thresholds for each test are shown in Fig. 3b. The details of the NAND/NOR tests are shown in Fig. 4. Each test is 32 gates, with one input held static to emulate the functionality of an inverter chain. Nodes that are sensitive to a particle strike (the drain of an ‘off’ transistor) at any point within the chain are identified and highlighted in red.

Fig. 4. nodes.

Fig. 2.

Full test-chip architecture.

(b)

NAND and NOR test chains and radiation sensitive

Comparison of the NAND and NOR-X chains focuses on the differences in node capacitance and diffusion area of the sensitive nodes. Assessing the NOR-X and NOR-Y tests looks at the different locations of sensitive nodes for different gates throughout the chain. The final logic test observes the effect of inverter size on pulse propagation at low VDD. Separate chains of length 2, 4, 8, 16, 24, and 32 each for sizes of 1X, 4X, and 8X inverters were implemented. Pulse propagation length was determined for each inverter size by monitoring the error rate vs. chain length trends.

IV. MEASUREMENT RESULTS AND ANALYSIS Fig. 5 shows the die photo and design summary of the 2mmx2mm test chip, fabricated in a 65nm CMOS process. The chip contains 107.5 kb of standard 6T cells and 88.7 kb of 8T RF cells, both with a custom layout. There are 26 unique logic tests, each duplicated 10 times for efficient data collection. 65nm CMOS 2mm x 2mm 0.33-1.0V ~3.3 million Memory Cell Size Array Size 0.849µm 2 107520 bits 1.173µm 2 88704 bits Digital Logic

Process Node Die Size VDD # of Transistors Cell 6T 8T # of Tests Block Size

(a) Fig. 5.

neutron and alpha radiation, respectively. A sharp increase in SER is shown once the threshold voltage is crossed (VTH~0.35V). This is likely a result of the transistors entering the weak-inversion region, where ION has an exponential response to any change in gate voltage. The neutron-induced multi-bit upset (MBU) rate vs. VDD (Fig. 7) shows a 2.6x increase when VDD scales from 1.0V to 0.33V, with no triple-bit upsets occurring until VDD=0.5V. Note that the custom SRAM cell size obeys logic design rules, such that the area is considerably larger than a commercial memory and will likely exhibit less MBU’s.

26*10=260 750µm x 1160µm

(b)

Die photo (a) and design summary (b).

Neutron experiments were conducted at the Los Alamos Neutron Science Center (LANSCE), while alpha experiments were held at the Oregon State University radiation center. 24 chips were irradiated in the neutron beam at LANSCE to maximize data collection over a limited testing time of 7 days. Alpha tests, run on a single chip, utilized an AM-241 source for over 3 months of data collection. Memory results are presented from both the neutron and alpha experiments. Combinational logic results and analysis are given for the alpha test data.

Fig. 7.

Further analysis shows that MBU’s are heavily dependent on the physical layout. 98% of MBU’s were adjacent bits on a horizontal word-line with sensitive nodes 0.37µm apart. The other 2% (shared bit-line) were separated by 0.8µm. 90% of shared word-line MBU’s occurred over a mirrored column orientation where the sensitive areas of adjacent bits were NMOS drain nodes. Column orientations with adjacent PMOS drain nodes were not as sensitive due to being 2x farther apart.

Fig. 8. Fig. 6. SRAM/RF SER vs. VDD for (a) neutron and (b) alpha radiation.

Fig. 6 shows the trend of SER vs. VDD for the 6T and 8T memory arrays. From VDD=1V down to VDD=0.33V, SER increases on average by 6.45x and 2.5x for accelerated

SRAM MBU rate vs. VDD under neutron irradiation.

Static noise margin test error rates vs. VDD.

Fig. 8 shows the measured soft error rates for each SNM test where VDD= 0.35V-0.5V. Error rates are first captured and then normalized for capacitive load using layoutextracted node capacitance, allowing for a strict assessment of the effect of only SNM on error rate. A

decrease in SNM from 50% to 20% results in a 3x error rate increase. At any VDD, no errors occurred for tests with an input threshold above 50%, showing that increased SNM in logic is an effective way to protect against radiation-induced transients at low VDD.

V. CONCLUSION This work details a test chip designed for near-threshold soft error characterization in 65nm CMOS. A variety of circuit-level test structures for both memory and logic have been described. Measurement results from neutron experiments were presented for the memory tests, showing a 6.45X increase in SRAM SER and a 2.6x increase in MBUs as VDD scales from 1.0V to 0.33V. Alpha particle experimental results show that circuit design decisions such as static noise margin, NAND vs. NOR based static logic, and inverter size have a strong effect on combinational logic SER, particularly at low VDD. ACKNOWLEDGEMENTS

Fig. 9.

NAND and NOR test error rates vs. VDD.

Fig. 9 shows the results of the NAND/NOR tests. The top plot compares NAND to NOR-X, where only the output node of each gate is sensitive. The NAND test shows ~1.5x higher error rates due to increased collection area from the larger devices on the sensitive node. A comparison between the NOR-X and NOR-Y tests shows that the soft error rate can increase based upon which input is set low, due to multiple sensitive drain nodes within a single logic gate, as described in Fig. 4. Error rate vs. inverter chain length is shown in Fig. 10. For chains consisting of inverters sized at 1X and 4X, errors continued to increase as the chain length increased. This implies that transient errors could continue to propagate through a chain length as long 32 gates. However, for the 8X chain, the error rate plateaus after a chain length of 8, leading to the conclusion that transient errors no longer propagate through more than 8 inverters.

Fig. 10. SRAM/RF SER vs. VDD for (a) neutron and (b) alpha radiation.

This research was, in part, funded by the U.S. Government (DARPA), Department of Energy Early CAREER program, and the NSF-CAREER program (ECCS-1151225). The views and conclusions contained in this document are those of the authors and should not be interpreted as representing the official policies, either expressed or implied, of the U.S. government. The authors would like to thank N. Siefert, P. Rech, S. Menn, and J. Darrough for their assistance. REFERENCES [1] Dreslinski, R.G., et. al, “Near-Threshold Computing: Reclaiming Moore’s Law Through Energy Efficient Integrated Circuits,” Proceedings of the IEEE. Feb. 2010. [2] Naseer, R, et. al,, "Critical Charge Characterization for Soft Error Rate Modeling in 90nm SRAM," ISCAS 2007, pp.1879-1882, 27-30 May 2007. [3] Hazucha, P.,et. al, "Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-μm to 90-nm generation," IEDM '03, pp. 21.5.121.5.4, 8-10 Dec. 2003. [4] Fuketa, H, et. al, "Neutron-induced soft errors and multiple cell upsets in 65-nm 10T subthreshold SRAM," IEEE Trans. Nuclear Science, pp.2907-2102, Aug. 2011. [5] Gadlage, M. et. al., “Digital Device Error Rate Trends in Advances CMOS Technologies”. IEEE Trans. Nuclear Science, vol. 54, no. 6, pp. 3466-3471. [6] Gill, B. et al, "Comparison of alpha-particle and neutroninduced combinational and sequential logic error rates at the 32nm technology node," IRPS, pp.199,205, April 2009. [7] Shivakumar, P., et. al, ”Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic,” in IEEE DSN, pp. 389-398, June 2002. [8] Chang, L. et. al, "An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches," JSSC, vol.43, no.4, pp.956,963, April 2008. [9] Calin, T. et. al, “Upset hardened memory design for submicron CMOS technology”. NSREC, July 1996