Comparison of Compaction Techniques in VLSI Physical Design

ISSN : 2229-6093

Chetan Sharma,Shobhit Jaiswal, Int. J. Comp. Tech. Appl., Vol 2 (1), 160-164

COMPARISON OF COMPACTION TECHNIQUES IN VLSI PHYSICAL DESIGN

Chetan Sharma1 & Shobhit Jaiswal2 (M.Tech-VLSI Department, JSS Academy of Technical Education, Noida) 1

( [email protected] ) &

2

( [email protected] )

Abstract: The rapid growth in integration

design, physical design, design verification,

technology has been made possible by the

fabrication,

automation of various steps involved in the

debugging. The physical design is important

design and fabrication of VLSI chips. The

step in the chip designing.

main factors which decide the quality of any

The process of converting the specification

chip are power consumption, area and

of an electrical circuit into a layout is called

performance of the chip. The demand of

the

light weighted & compact chip is increase

extremely small size of the individual

day by day. This paper reviewed the

components, physical design is an extremely

different techniques of compaction of any

tedious and error prone process. Almost all

chip and comparison among them because

phases of physical design extensively use

different techniques have different tradeoffs.

Computer Aided Design (CAD) tools,

The appropriate technique is used depending

means steps are partially or fully automated.

upon requirements.

The main steps in VLSI physical design are

Keywords:

partitioning,

rules,

CAD Tool, Layout design

Shadow

propagation,

Scanline,

Flooring.

physical

packaging,

design

testing

process.

placement,

Due

routing

and

to

and

compaction. Compaction is very important step in the physical design due to the incereasively need of small size chips.

Introduction: In the VLSI design cycle

The operation of layout area minimization

there are many steps: System specification,

without violating the design rules and

functional design, logic design, circuit

without altering the original functionality of

160

Chetan Sharma,Shobhit Jaiswal, Int. J. Comp. Tech. Appl., Vol 2 (1), 160-164

ISSN : 2229-6093

layout is called as compaction. The input of

Design style specific compaction

compaction is layout and output is also

problem:

layout but by minimizing area. Compaction is done by three ways: (a) By reducing space between blocks without violating design space rule.(b) By reducing size of each block without violating design size rule.(c) By reducing shape of blocks without violating electrical characteristics of blocks. Therefore compaction is very complex process because this process requires the knowledge of all design rules. Due to the use of strategies compaction algorithms are divided into one-dimensional algorithms

The scope and impact of compaction is different on different design styles: (a)Full custom style: There are large scope of compaction in full custom design style because of randomly sizes of block and random space between blocks. (b) Standard cell design style: In this style height of blocks are fixed. Therefore scope is limited to channel compaction. (c) Gate array design style: In the gate array design style position of gate is fixed so scope is limited to optimizing wiring.

(either in x-dimension or y-dimension), two dimensional

algorithms

(both

in

x-

dimension and y-dimension) and topological algorithm

(moving

of

separate

cells

according to routing constraints)

Compaction Techniques: There are different compaction techniques as shown in fig (a) 3/2 -Dimensional

Problem formulation: Given: Layout consists of set of geometrical feature M = {M1, M2, M3,….Mn ) Each Mi has minimum size = s (Mi)

Compaction Techniques

Hierarchical compaction

Minimum space between Mi & Mj = d (Mi, Mj)

Scan line Algorith m

where 1