Defect-Oriented Fault Simulation and Test Generation in ... - CiteSeerX

Defect-Oriented Fault Simulation and Test Generation in Digital Circuits W.Kuzmicz1, W.Pleskacz1, J.Raik2, R.Ubar2 1

Warsaw University of Technology, 2Tallinn Technical University

Abstract. A generalized approach is presented to fault simulation and test generation based on a uniform functional fault model for different system representation levels. The fault model allows to represent the defects in components and defects in the communication network of components by the same technique. Physical defects are modeled as parameters in generalized differential equations. Solutions of these equations give the conditions at which defects are locally activated. The defect activation conditions are used as functional fault models for the higher level fault simulation purposes. In such a way, the functional fault model can be regarded as interface for mapping faults from one system level to another, helping to carry out hierarchical fault simulation and test generation in digital systems. A methodology is proposed which allows to find the types of faults that may occur in a real circuit, to determine their probabilities, and to find the input test patterns that detect these faults. Experimental data of the hierarchical defect-oriented simulation for ISCASÕ85 benchmarks are presented, which show that classical stuck-at fault based simulation and the test coverage calculation based on counting defects without considering defect probabilities may lead to considerable overestimation of results.

1. Introduction Testing and diagnosis of VLSI circuits and digital systems have faced a lot of problems produced by continuous emerging of new technologies and.by growing complexity of circuits and systems. The efficiency of test generation (test quality, generation speed) is highly depending on the system description and fault models. Since traditional low-level test generation methods and tools for complex VLSI systems have lost their importance, other approaches based mainly on functional, behavioral, or hierarchical methods are gaining more and more popularity [1-2]. The advantage of hierarchical test generation approaches compared to the functional ones lies in the possibility of constructing test plans at higher functional levels, and modeling faults at lower levels.

Traditionally used very popular stuck-at fault (SAF) model has not withstood the test of time. It has been shown that high SAF coverage cannot quarantee high quality of testing, for example, for CMOS integrated circuits [3-5]. The reason is that the SAF model ignores the actual behaviour of digital circuits implemented as CMOS integrated circuits, and does not adequately represent the majority of real IC defects and failure mechanisms which often do not manifest themselves as stuck-at faults. The types of faults that can be observed in a real gate depend not only on the logic function of the gate, but also on its physical design. These facts are well known [4-7] but usually ignored in engineering practice. In earlier works on layout-based test generation techniques [6,7] the whole circuits having hundreds of gates were analysed as single blocks. Such an approach is computationally expensive and thus highly impractical as a method of generation of tests for real VLSI designs. In this work we characterise faults in library cells, determine kinds of faults and their probabilities and then use this information for defect oriented fault simulation and test generation at higher levels of abstraction. This approach is based on the assumption that the majority of defects occur inside the cells and not in the routing between them. Such assumption would not be realistic in the case of older CMOS technologies with two levels of metal and very dense routing. However, in state-of-the-art deep submicron technologies still only one or two levels are used inside cells but 6 or more levels of metal are available for routing. More routing levels means lower sensitivity to defects. Routing between the cells is less dense and various nodes are routed at various metal levels. As a result, probability of shorts outside cells is significantly reduced. In this work we verify functionality of analysed gates for all possible defects and find the actual functions performed, using transistor-level simulation. This characterisation process may be computationally expensive, but it is performed only once for every library cell. In other words, we replace abstract fault models like SAF with realistic defect models. In [8] a new approach was introduced for hierarchical defect simulation based on defect preanalysis for components, and using the results of preanalysis in higher

level fault simulation. Here, we generalize this approach by introducing a functional fault model as a method for mapping faults from one hierarchical level to another. Based on this approach, hierarchical algorithms for dafect-oriented fault simulation and test generation are developed and implemented. The functional fault model in a form of a set of logical conditions allows to represent the defects in components and in the communication networks by the same technique. Then we propose a methodology which allows to find the types of logic faults that may occur in a real circuit, to determine their probabilities of occurrence, and to find the input test patterns that detect these faults. We compare the results obtained in this way with the results of testing of the same circuits by the sequences of test patterns based on the conventional fault model. Experiments were carried out for the ISCASÕ85 benchmark circuits. The paper is organized as follows. In Section 2 we present a new method of parametric fault modeling for carrying out defect analysis in digital circuits. In Section 3 we define the functional fault model which will be used as a interface for mapping faults from one hierarchical level to another. In Section 4 we propose a uniform hierarchical approach to test based on the functional fault model. Section 5 presents the results of a probabilistic analysis of defects and relates the defects to the functional fault model. In Section 6 we propose a new hierarchical defect oriented fault simulator and a random test generator. Section 7 presents experimental results, and finally, in Section 8 we draw the conclusions of this research.

2. Parametric defect modeling In this Section we present a new general fault model for describing and modeling arbitrary physical defects in components of digital circuits that result in a violation of the logical function of a component. Consider a Boolean function y = f (x1, x2 , É, xn) implemented by an embedded component in a digital circuit. Introduce a Boolean variable d for representing a given defect in the component or in the neighbourhood layout of the component, which may affect the value y by converting the Boolean function f into another function y = f d (x1, x2, É, xn, xn+1, É xp). Here, the variables x n + 1 , É x p belong to the neighbourhood layout of the component which will influence the function y in the presence of defect d. For example, assume there is a short between leeds x1 and x 5 in the circuit in Fig. 1. The faulty function y = f(x1,x2) = Ø (x1 Ù x2) in the case of the defect d can be represented as y = fd(x1,x2,x3,x4)= Ø(x1 x5)Úx2=Ø(x1Ø (x3Ù x4))Úx2).

x3 x4

&

x5 Short

y x1 x2

&

Fig.1. A short between two signal leads Introduce now a generalized parametric function y* = f*( x1, x2, É, xn, xn+1, É xp, d) = Ød & f Ú d & f d as a function of a defect variable d, which describes the behavior of the component simultaneously for both possible cases. For the erroneous case the value of the defect variable d as a parameter is equal to 1, and for the nonerroneous case d = 0. In other words, y* = f d if d = 1, and y* = f if d = 0. The solution of the Boolean differential equation Wd = ¶y* / ¶d = 1

(1)

describes now the conditions (constraints) which activate the fault d on a line y (Fig.2). For example for the short in Fig.1 we have y* = ØdfÚdf d =ØdØ(x1 Ù x2) Ú d(Øx1Ø(x3 Ù x4)ÚØx2). Wd = ¶y* / ¶d = x1 x2 x3 x4. The parametric modeling of a given physical defect d by Boolean differential equations allows us to use the solutions Wd, either - in defect-oriented fault simulation, for checking if the condition (1) for a given defect d is fulfilled (if the defect d is activated), or - in defect-oriented test generation, to solve the differential equation (1) with the goal to activate the given defect d. To find the parametric fault model for a given defect d we have to create the corresponding logical expression for the faulty functions fd either by logical reasoning or by carrying out directly defect simulation. Some examples of the conditions Wd for different type of defects (where stuck-at-fault (SAF) is a particular case) are given in Table 1 (here x k is the observable variable, and xÕk is the variable at the previous time moment). Table 1. Activating conditions for different defects No 1 2 3 4

Defect SAF xk º 0 SAF xk º 1 Short between xk and xl Exchange of lines xk and xl

5

Delay fault on the line xk

Conditions Wr xk = 1 xk = 0 xk = 1, xl = 0 xk = 1, xl = 0, or xk = 0, xl = 1 xk = 1, xÕk = 0, or

xk = 0, xÕk = 1 The logical conditions W for activating defects d can be used at the higher (logical or register transfer) level either for fault simulation or for test pattern generation without paying attention to the physical reasons of defects. d

3. Conception of the functional fault model The method of defect modeling by logical conditions (see Fig. 2) can be generalized for the purpose of hierarchical fault simulation. Component

Wd

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y

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Fig. 2. Functional fault model for a physical defect A module (e.g. a library component) in a circuit can be preprocessed by lower level fault simulation with the goal to generate a set of logical conditions W = {Wr } for all possible lower level faults r of the component. Each condition Wr can be regarded as a higher level functional fault model for a given lower level fault r, since in the presence of the fault r the functional behavior of the component at the input stimuli Wr = 1 will be faulty. Definition 1: We call a failed input pattern ti of a given module M (complex gate or component) a functional fault if it detects at the output of M at least one lower level fault rj in the module M. The functional fault model can be regarded as a uniform way of mapping faults between two hierarchical levels. For example, we can map by the same way both, the gate level stuck-at faults or the physical defects of a component in a circuit to the higher behaviour level of the same component. The input patterns ti for a given fault rj can be found either by traditional gate level test generation (e.g. for stuck-at faults) or by parametric fault modeling and solving corresponding differential equations (1) for physical level defects. Definition 2: We call a set of functional faults which cover all the lower level faults of the component a functional fault model of the component. Using the conception of the functional fault model allows to reduce the complexity of fault modeling if the number of higher level faults is less than the number of lower level faults. For example, for the ISCASÕ85 benchmark circuit c17, it was possible to replace 78 lower level physical defects by only 4 functional faults (see Section 6). The complexity reduction in this particular case is 20 times.

On the other hand, the functional fault model allows to process all the lower level faults by means of higher level language. No disclosure of the internal stucture of the component for modeling lower level faults is needed. In general, the functional fault model is not unique. The given set of low level faults can be covered by different high level functional faults (sets of input patterns of the module). This fact should be considered both, in hierarchical fault simulation and in hierarchical test generation.

4. Uniform hierarchical approach to test The method of modeling faults by logic conditions Wr allows to unify the functional level fault simulation for components of a circuit without going into structural details of components and for structural defects in the communication network of components. In both cases, a condition Wr describes how a lower level fault r (either in a component or in a network) should be activated at a higher level to a given node in a circuit. The conditions Wr can be used both in fault simulation and in test generation. Consider a node k in a circuit as the output of a module M k. and represented by a variable xk.. Associate with the node k a set of faults Rk = RFk È RSk where RFk is the subset of faults in the module Mk, and RSk is a subset of structural faults (defects) in the ÒneighborhoodÓ of the component M k. Denote by Wr the condition when the fault r Î Rk will change the value of xk. An arbitrary erroneous change of the value of x k (denoted by dxk = 1) can be represented formally by implication dxk ®

Ú (r Ù W ), r Î R . r

k

(2)

All the suspected faults can now be determined by solving the equation

Ú (r Ù W ) = 1, r Î R . r

k

(3)

In such a way we should construct for each module Mk of the circuit a list of faults R k with logical conditions Wr for each fault r Î Rk. The conditions for functional faults r Î R Fk of the module can be found, for example, by low level (gate level) test generation for the stuck-at faults in the module. When defect-oriented test method is chosen, then the activisation conditions for defects can be found by parametric defect modeling and solving the equation (1). The conditions for structural faults (or defects) in the network (in the neighbourhood of the module) can be calculated also by parametric fault modeling and solving the corresponding equations (1).

In Fig. 3, a hierarchical test conception based on parametric fault modeling and functional fault model for a 3-level system is illustrated. Functional approach

F

Structural approach Test

W Sk

W Fk

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System

Fk

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F ki Gat e

Test

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W d ki Circuit

Fig.3. Hierarchical test approach In Fig.3 functional and structural test generation approaches are illustrated. In the functional approach, only the information about the functional behaviour is used. In the structural approach, tests are targeted to detect the faults in the networked components and in the network communication. For gates usually stuck-at faults are the basis of test generation. In some sense, this method can be regarded as a functional approach. Using the layout information of the circuit of the gate, physical defects can be selected, and after parametric modeling and solving the equation (1), a set of activation conditions Wdki for a given gate Gki can be created. The test patterns generated in such a way form a set of conditions W Fki which can be regarded as a functional fault model for this gate in a network level. The network structural faults (defects in the layout) can be modeled parametrically for creating a set of conditions WSki which together with the sets of W Fki for all gates in the network form a test for the given module Gk. This test in its turn can be regarded as a functional fault model WFk for the module in a system level etc. In such a way, at each level the faults in a system under test are represented by the functional model as a set of conditions W = W F È WS where W F represents functional faults in the components of the network and WS represents structural faults in the network.

5. Probabilistic defect modeling In the following we consider one kind of physical defects in CMOS gates - shorts between conducting regions. This is one of the most important sources of

faults in CMOS digital circuits. However, the methodology can be extended to other types of physical defects as well (e.g. breaks). A short is a piece of extra conducting material that connects a pair of separate conducting regions in the integrated circuit. This affects the connectivity of the circuit - two separate electrical nodes become connected. It is intuitively obvious that probabilities of shorts depend on the layout of the circuit. Conducting regions that are adjacent to one another are more susceptible to shorts than regions that are separated by a large distance. We assume that every defect that results in a short can be approximated by a circle. To estimate the probabilities of shorts between pairs of nodes we use the concept of critical area for shorts [5]. The critical region for shorts is such a region in the circuit that if the center of a defect of a given radius R is located anywhere inside the critical region, a short between two adjacent conducting regions occurs. The critical area is the area of the critical region. It depends on the shapes and locations of the conducting regions that can be shorted and is a function of the defect radius R. The radii of defects are random and can be characterised by a probability density function P df(R) which is specific for a given manufacturing process and given conducting layer. We assume that the probability of a short between a pair of conducting regions that correspond to a pair of electrical nodes is proportional to the critical area for these two regions. The critical area for shorts is a function Ps(R) of the defect radius R. Since the defect radii exhibit a random distribution, the product P d f(R) * P s (R) integrated over the range of R where Ps(R) > 0 can be taken as the measure of the total probability of shorts between a given pair of nodes. Pt = ò Ps(R) Pdf(R) dR The first step in identification of logic faults and their probabilities is to calculate P t for all pairs of conducting regions representing electrical nodes. If for a given pair P t = 0, this pair of nodes cannot be shorted and is not taken into account. For the pairs that can be shorted the logic faults are determined. In simple cases this can be done by inspection of the circuit, for example it is obvious that a short between an output node and VDD results in Òstuck-at-1Ó fault at this node. In more complex cases it may be necessary to simulate operation of the faulty circuit at the transistor level by SPICE. In our simulations shorts were represented by resistors. We tried several resistance values in the range from 0.01 ohm to 200 ohm. The gate behaviour at the logic level did not depend on this resistance. The waveforms obtained from the simulation allow to determine the actual logic function performed by the faulty circuit.

Table 2. Conditional probabilities of and-type shorts in the complex gate AND2,2/NOR2 and the fault table i

Fault di

Erroneous function f di

not((A*C)*(B+D)) not((A*D)*(B+C)) not(B*(not(A)+C+D)+C*D) A*(not(C*D)) not(C*D) not(B+(C*D)) not((B*C)*(A+D)) not((B*D)*(A+C)) not(A+C*D) B*(not(C*D)) not(C*D) not(A+(C*D)) Not((A+B+D)*(A*B+not(C)+D)) C*(not(A*B)) not(A*B) not(D+A*B) not(A*(B+C+not(D))+B*not(D)+ not(A+B)*D) 18 D/Q D*(not(A*B)) 19 D/GND not(A*B) 20 D/VDD not(C+A*B) 21 N1/Q not((A*B)+(B*C*D)+(A*C*D)) 22 N1/GND sa-0 for Q 23 N1/VSS not(C*D) 24 Q/GND sa-0 at Q 25 Q/VSS sa-1 at Q 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

A/C A/D A/N1 A/Q A/GND A/VDD B/C B/D B/N1 B/Q B/GND B/VDD C/N1 C/Q C/GND C/VDD D/N1

1

Input patterns tj 6 7 8 9 10 11 12 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1

1

Pi 3,1100E-07 1,1940E-07 4,9059E-08 6,9159E-08 2,6895E-08 1,9847E-08 1,0477E-07 5,7931E-08 5,2930E-08 3,3912E-08 4,6466E-08 1,8972E-08 3,9147E-08 9,1480E-08 1,9862E-08 1,4727E-08 2,7604E-08 2,0036E-07 9,9504E-09 1,4727E-08 1,3697E-07 8,4883E-09 2,1532E-07 1,0145E-07 3,5661E-08

In this way the functional faults that result from shorts are identified and their probabilities are determined. This procedure and the software developed for this purpose are described in more detail elsewhere [10]. Table 2 shows the distribution of the probabilities of various types of functional faults for a complex 4 input gate performing the AND2,2/NOR2 function. This gate is from an industrial standard cell library in 0.8 micron CMOS technology. Usually the most time consuming part of the characterisation process is the identification of the logical faults that correspond to shorts. If the number of possible shorts is large and operation of faulty cell is not obvious for most of them, it is necessary to perform many circuit simulations. This is time consuming and difficult to automate. Hence, the complexity of the characterisation process depends mainly on the number of physically possible shorts in the characterised cell and the complexity of the cell function.

6. Hierarchical fault simulation Consider a task of defect oriented fault simulation in a system which is simulated at three levels: register transfer, gate and defect levels (Fig. 4). Formally, if Y is the system variable representing an observable point of the system, yM is an output variable

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of a module and yC is the output of a gate with a physical defect d, then the condition to detect the defect d on the observable test point Y of the system is W = ¶Y/¶yM Ù ¶ yM /¶yG Ù Wd = 1, where ¶Y/¶yM is the Boolean derivative calculated by the high-level simulation, ¶yM /¶ y G is the Boolean derivative calculated by the gate-level simulation, and W d is the functional fault condition found by the gate preanalysis. Functional fault detected

Functional fault activated

Defect High-level simulation

d

n Physical defect analysis

yG n

n

Complex gate

yM

Y

High-level fault analysis

Gate-level simulation

Module

Gate-level fault analysis

System Fig. 4. Hierarchical defect oriented fault simulation

The relationships between the functional faults (patterns) ti and the defects d j for all the gates g in the library L are given by defect tables DT g = çç dij çç, g Î L, where an entry dij = 1 means that the input pattern ti of the gate detects the defect dj , otherwise dij = 0. Let Dg be a set of defects in the gate g Î L. Then for each gate g Î L we create a set of probabilities Pg where each entry pj Î Pg means the conditional probability of a defect dj Î Dg in the condition that a defect is present in the system. The multi-level functional fault simulation is carried out as follows (see Fig. 4): · on the defect level we relate the physical defects of complex gates to the functional fault model by fixing which defects are detected by which input pattern of the gate; this information is stored in the library fault tables; · on the logical level we check if the functional faults of the given gate are activated and propagated to the output of the given module, and · on the RTL level we check if the erroneous signals caused by defects are propagated from the outputs of modules to an observable point of the system. where ti Ì T i means that the test pattern Ti includes the input pattern ti of the gate gj. For carrying out the experimental part of this work, a hierarchical two-level defect oriented fault simulation technique was implemented. The method consists of the following two steps: · traditional gate-level stuck-at fault simulation with the goal of creating a fault table for stuck-at faults of a gate-level circuit, i.e. of finding all the cases when dxk = 1 in (2), and · defect oriented functional fault simulation based on solving the equation (3) for all xk where dxk = 1 with the goal of fixing the subsets of defects detected in all the gates of the given circuit. On the first step, for a given module a fault table FT = ççt ij çç is created for the stuck-at faults x j º e, e Î{0,1}at the outputs of complex gates gj, where an entry tij = e means that a test pattern Ti of the circuit detects the fault x j º e, otherwise tij = X where X means donÕt care. On the other hand, each entry t ij Î {0,1} in F T means that a functional fault ti of the gate gj is detected on its output xj. On the second step, for each tij in the fault table FT, a subset of defects Dg,j(ti) Ì Dg,j will be fixed for the gate gj detected by the test pattern Ti by the following operation: Dg,j(ti) = {dj | j: dij = 1 & , ti Ì Ti }, where ti Ì T i means that the test pattern Ti includes the input pattern ti of the gate gj. Based on this simulator we implemented also a random test pattern generator (D-TPG) targeted for detecting physical defects in the circuit.

7. Experimental results The purpose of experiments carried out with the prototypes of defect oriented fault simulator and test generator was twofold: 1) to compare the quality of 100% stuck-at test patterns in relation to physical CMOS defects for the family of ISCASÕ85 benchmark circuits, and 2) to compare the efficiencies of stuck-at fault based test pattern generator (S-TPG) with defect oriented test pattern generator (D-TPG) for the same circuits. For carrying out the experiments we used the data produced by probabilistic analysis of the physical defects of the AND2,2/NOR2 gate (Table 2), and we resynthesized the ISCASÕ85 circuits trying to use as much as possible this complex gate. Let D be a set of physical defects under consideration. The 25 defects d Î D of the complex gate AND2,2/NOR2 are listed in Table 2 together with the erroneous functions f d. A,B,C,D are the inputs of the gate, Q is the output and N1 is an internal node of the gate. All the defects covered by each input pattern of the gate are marked by 1. For each defect di the probabilities Pi are also given. Table 3. Testing of the gate AND2,2/NOR2 Defect coverage, % OR-type shorts AND-type shorts Counted Probabil. Counted Probabil. defects defects defects Defects 92.50 85.35 96.0 83.03

We generated for the complex gate AND2,2/NOR2 a test set T = {0101,1010,1011,1110} with 100% stuck-at fault coverage, which in the same time (see Table 3), gives in the worst case only 83.03% coverage of defects in D. For AND-type shorts the defect A/C and for ORtype shorts the defects A/C and B/D remained not detected. This result shows that the 100% stuck-at test may not be adequate for detecting physical defects. The problem to investigate by the following experiments was to determine how good are the 100% stuck-at tests in detecting physical defects in more complex circuits. In Table 4 the characteristics of the resynthesized ISCASÕ85 circuits are depicted with the number of test patterns generated for stuck-at faults. For investigation of the correlation between fault coverages for stuck-at faults and the coverage of defects in D, we generated at first test patterns with 100% stuck-at fault coverage. The reached fault coverage of 100% for all the circuits shows that the resynthesized circuits are without redundancy.

Table 4. Data of resynthesis and test generation Circuit c17 c432 c499 c880 c1355 c1908 c3540 c5315 c6288

Total # of gates 6 152 356 293 318 245 613 1035 2547

# of complex gates 1 12 108 53 108 70 124 353 11

Stuck-at Fault cover, % 100.0 100.0 100.0 100.0 100.0 100.0 100.0 100.0 100.0

# of test patterns 6 67 96 60 104 69 228 127 62

Defect-oriented fault simulation for the ISCASÕ85 circuits was carried out hierarchically in two steps. At first, for each complex gate in the circuits the functional fault coverage was calculated. Then, at the lower level, the real defect coverage for these gates based on the functional fault coverages of gates and on the data in Table 2 was calculated. The computed fault coverages for the parts of circuits consisted only of the complex gates AND2,2/NOR2 are depicted in Table 5. From the Table 4 we see that even for the chosen subset of physical defects - the shorts in the layout (breakes and opens were not considered) the quality of stuck-at test would not be sufficent. Table 5. Data of defect-oriented fault simulation Circuit

c17 c432 c499 c880 c1355 c1908 c3540

c5315 c6288

Defect coverage, % OR-type shorts AND-type shorts Counted Probabil. Counted Probabil. defects defects defects defects 92.59 91.10 100.0 100.0 99.38 98.78 99.33 98.97 92.80 85.76 100.0 100.0 95.95 91.98 100.0 100.0 93.42 87.83 100.0 100.0 92.91 85.98 99.94 99.94 94.21 89.98 99.68 99.60

94.71 92.59

91.14 85.35

100.0 100.0

100.0 100.0

In fact, it is not surprising that the 100% stuck-at fault tests can not achieve the 100% defect coverage. The main result of the paper is to present a new method and a tool for efficient calculation of the exact defect coverage for given test sets. By this tool it is possible to show quantitatively the real quality of the given test sets e.g. of tests expected to have 100% quality. In Table 6 the results of defect oriented random test generation are depicted. The cases when the defect oriented test generation has reached better quality compared to the stuck-at fault oriented approach are highlighted. The fact that in most cases the results are the same can be explained by the fact that the not detected defects are redundant. For strict proving the

redundancies, however, deterministic defect-oriented test generator is needed. This will be our future work. Table 6. Data of defect-oriented test generation Circuit

c17 c432 c499 c880 c1355 c1908 c3540

c5315 c6288

Defect coverage, % OR-type shorts AND-type shorts Counted Probabil. Counted Probabil. defects defects defects defects 100.0 100.0 100.0 100.0 100.0 100.0 100.0 100.0 92.80 85.76 100.0 100.0 95.95 91.98 100.0 100.0 93.42 87.83 100.0 100.0 92.91 85.98 100.0 100.0 94.38 90.28 99.74 99.67

94.71 92.59

91.14 85.35

100.0 100.0

100.0 100.0

The new result in this paper is also to show that the quality of tests in terms of defect coverage is higher when the defect probabilities are not taken into account (see Tables 3, 5 and 6). From this result, we can conclude that the traditional methods of test coverage measuring based on simply counting of not detected defects, where all the faults are assumed to have the same probability, are tending to be overestimated.

8. Conclusions A new hierarchical defect modeling method has been developed and implemented as a tool. In this method, we use a new functional fault model developed for representing defects on the higher level, and the fault-to-defect mapping in the form of defect coverage table. In this method, the conditional probabilities of defects can be also used in probabilistic defect coverage calculation. This method was generalized to a uniform approach to map faults from one level to another in system hierarchical representation. For carrying out the experimental part of this work, a hierarchical two-level defect oriented fault simulation technique was implemented. This technique was used also in implementing a defect-oriented random test pattern generator. A probabilistic analysis of CMOS physical defects has been carried out for generating input data for stuckat-fault test quality estimation. Based on these data, and by using the implemented tools it was possible to show quantitatively the real quality of test expected to have 100% quality. It was shown also that the classical test coverage calculation based on simply counting detected and not detected defects without taking into consideration the defect probabilities may lead to considerable overestimation of the real quality of test sets for CMOS circuits.

Acknowledgements This work has been supported by the EC project INCO-COPERNICUS 977133 - VILAB ÒMicroelectronics Virtual Laboratory for Cooperation in Research and Knowledge TransferÓ, by the Estonian Science Foundation grant G3658, and by the Polish State Committee for Scientific Research grant for international cooperation with Ukraine. The authors are grateful for Dr. M.Blyzniuk and Dr. M.Lobur from Lviv Polytechnic, Lviv, Ukraine for their important contribution in earlier stages of this work described in [8] and [10].

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