Synthesis of an RTL design using Synopsys Design Compiler (DC). • Using
Tetramax to ... Insert scan chain into a design using Synopsys DFT compiler.
Sharif University of Technology Department of Computer Engineering
Testability Course Final Project
Design for Testability (DFT) Flow for Digital Designs
Instructor: Shaahin Hessabi Assistant: Hajar Falahati December 2012
Testability Final Project Objectives: • • • • •
Verilog modeling of sequential circuits. Synthesis of an RTL design using Synopsys Design Compiler (DC). Using Tetramax to generate test patterns for Combinational Logic Insert scan chain into a design using Synopsys DFT compiler Using Tetramax to generate test patterns for scan inserted design
Tools: • • • •
Simulation: Modelsim /VCS/NC Verilog /Icarus Verilog Synthesis: Design Compiler (Synopsys) Scan chain insertion: DFT Compiler (embedded in DC) Automatic test pattern generation (ATPG): Tetramax
Testability Final Project Phase 0: Introduction I. II.
III. IV. V.
Select a teammate for Testability project! Please be notice, each team will consist of two students. Please check the links and select two (Complicated enough!!) circuits from ISCAS-89 category and one code from code project. All circuits should be implemented by Verilog code. http://www.pld.ttu.ee/~maksim/benchmarks/ http://www.pld.ttu.ee/~maksim/benchmarks/iscas89 Send list of your team members and your circuits.
[email protected]; Subject: [Test][Final Project][Team] DEADLINE: 11-10-91, 23:55. Approval Mail: 13-10-91
Phase 1: Synthesizing Sequential Circuits I. II.
III. IV.
Check the functionality of your selected circuits and synthesize them. Send a brief description of the functionality of your circuits, including their waveforms!
[email protected]; Subject: [Test][Final Project][Phase1] DEADLINE: 3-11-91, 23:55. Extended DEADLINE: 13-11-91,23:55.
Phase 2: Insert Scan Chain I. II. III. IV. V. VI.
Introduction to DFT Compiler! Brief review on DFT Compiler! Insert a single scan chain in each of the synthesized designs obtained from phse1, using the DFT Compiler (embedded in Design Compiler). Save the netlists after inserting the scan chains. Report area, timing, and power of the scan-inserted netlists, also a brief Review on DFT Compiler! Complete the following table for area, timing, power: Circuit Name
VII. VIII.
Area/timing/power without scan insertion
DEADLINE: 13-11-91, 23:55. Extended DEADLINE: 27-11-91,23:55.
Area/timing/power with scan insertion
Testability Final Project Phase 3: Generate Test Patterns I. II. III. IV. V.
Introduction to Tetramax! Brief review on Tetramax! Generate test patterns for each of the netlists of phase1 using Tetramax, and observe the fault coverage for single stuck-at faults. Generate test patterns for each of the netlists of phase2 using Tetramax, and observe the fault coverage for single stuck-at faults. Complete the following table: Circuit Name
VI. VII.
Fault coverage without scan insertion
DEADLINE: 20-11-91, 23:55. Extended DEADLINE: 11-12-91,23:55.
Fault coverage with scan insertion
