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FPGA Implementation of a Fully Digital Demodulation Technique for Biomedical Application M. H. Zarifi, Student Member, IEEE, J. Frounchi, S. Asgarifar and M. Baradaran Nia Abstract— Widely used demodulation technique in EIT/EIS systems is the direct conversion (zero-IF) method in which measured single tone current (or voltage) signal is mixed with source waveform at the same frequency, so that the magnitude and phase of the measured current (or voltage) can be determined after a low pass filtering stage. This is especially true for an EIS system which might need to operate in a low frequency range as small as 100 Hz. In the system presented here, the amplitude and phase of the IF signal can be measured after digitizing the signal by an ADC in digital domain with transferring the IF signal to the baseband (zero frequency). In this system, a lowpass FIR filter and a variable frequency digital oscillator have been used. In our designed system there is no need for zero crossing technique which suffers from jitter noise and delay of different path, for signal mixing. We have implemented digital demodulation part of system on a Virtex-4 LX25 FPGA from Xilinx. Keywords— Demodulation, EIT, EIS, FIR, FPGA
I. INTRODUCTION
sinusoidal reference input. In down conversion technique, the difference frequency between the measured signal and the reference input is chosen, so the mixer output passes through a low pass filter and the amplitude of the measured signal which is sensitive to the measured signal phase can be determined. The same arrangement with a second sinusoidal reference input, displaced by 90 degrees with respect to the first, can be employed to extract the measured signal phase. For the system shown in Fig. 1, the following relations are hold (c1 = c2 = c): Vmix
AK AK cos( 2Z c t T ) cos T 2 2
(1)
where K is the amplifier voltage gain. The lowpass filter rejects the second harmonic and the dc value is the demodulator output. This demodulation technique (zero-IF) can be used in digital domain either, but we need the exact input of reference input to determine the phase of the measured signal.
N
OWADAYS, micro electrical impedance spectroscopy systems (PEIS) have been developed for single cell analysis [1-3]. In a typical single cell impedance spectroscopy system, the operating frequency range is from 100 Hz to a few MHz [1]. For some applications, the lowest operating frequency can be as low as 1 Hz [2]. The electronic devices working in lower frequencies are suffering from the flicker noise contamination and extraneous offset voltages which can corrupt the measured signal from a tissue. In electrical impedance spectroscopy (EIS) and electrical impedance tomography (EIT) systems, the demodulator role is to extract the amplitude and phase of the voltage signal measured by the patient electrodes. Several demodulation techniques such as phase sensitive detection [4] and digital matched filter [5-6] have been used for these systems. The demodulator affects the output signal-to-noise ratio (SNR) so it is necessary to design it in a way that maximizes SNR. It is also possible to use a high-speed high-resolution analogtodigital converter (ADC) to directly digitize the input reference and measured signals and to perform the demodulation in digital domain. In a typical system, the measured signal is amplified by an instrumental amplifier prior to an analog multiplier which is employed as a mixer. The second input to the mixer is the All authors are with Electrical and Computer Engineering Department, University of Tabriz, Tabriz, Iran. M. H. Zarifi, J. Frounchi and S. Asgarifar are with microelectronic and microsensor laboratory (phone: +98-411-339-3748; email:
[email protected],
[email protected],
[email protected]) M. Baradaran Nia is with navigation and guidance laboratory (email:
[email protected]) CCECE/CCGEI May 5-7 2008 Niagara Falls. Canada 978-1-4244-1643-1/08/$25.00 2008 IEEE
Fig. 1. A typical demodulator system for an EIT system Field Programmable Gate Array (FPGA) vendors now support processors on their FPGA devices to allow complete systems to be implemented on a single programmable chip. Although some vendors have incorporated fixed hard processors on their FPGA die, on the other hand they are being increasingly used for a variety of computationally intensive applications, mainly in the realm of Digital Signal Processing (DSP) and communications [8-14]. Due to rapid increases in the technology, current generation of FPGAs contain a very high number of Configurable Logic Blocks (CLBs), and are becoming more feasible for implementing a wide range of applications. The high nonrecurring engineering (NRE) costs and long development time for ASICs are making FPGAs more attractive for its application in specific DSP solutions. DSP functions such as FIR filters and transforms are used in a number of applications such as communication and
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2 multimedia. These functions are major determinants of the performance and power consumption of the whole system. In this paper, we have implemented fully demodulation technique for EIT/EIS systems on a Virtex-4 LX25 FPGA from Xilinx to increase the process speed with parallelism and reducing power consumption.
II. THE DEMODULATION TECHNIQUE The EIS system presented here has been designed to work in frequency range of 40 Hz to 100 kHz. The block diagram of the demodulator is shown in Fig. 3. The signal from tissue is passed to the analog to digital converter (ADC). This system uses a 10-bit ADC with 1V as input voltage then the digitized data is sent to FPGA for future processing. The downsampling process must ensure the Nyquist criterion which is met for the highest carrier signal. The low-pass filtering is implemented using an FIR filter structure. Sufficient FPGA resource is available to achieve 75dB attenuation in the stop band, using coefficients derived from the ‘optimal’ method described in [14]. The resulting DC components at the output of the lowpass filtering stage contain the phase and amplitude information of the measured voltage. The transfer function of the filter can be derived as follow: Vin1
A cos(Zt T )
VREF 1 1u sin(Zt I )
V path1
Vin1 A cos(Zt T ) A2 cos(2Zt T 2 ) A3 cos(3Zt T 3 ) (11) VREF 1 u cos(Zref t I ) (12)
If ref varies in a wide range, every component of equation (11) will be known after filtering the DC frequency. Table 1 shows the domain of components for different ref in different frequencies.
(3)
Table I.
A cos(Zt T ) u sin(Zt I ) A / 2 sin(T I ) A / 2 u sin( 2Zt T I )
V LPF ( path1)
A / 2 sin(T I )
VREF 2
1u cos(Zt I )
V path 2
A cos( wt T ) u cos(Zt I )
A / 2 cos(T I ) A / 2 cos(2Zt T I ) VLPF ( path 2) A / 2 cos(T I ) OUT1 A cos(T I ) OUT2
(2)
Many recent designs utilize digital waveform synthesis techniques to produce waveforms with very low harmonic distortion, high stability, and good synchronization between the excitation and measurement processes [15-16]. We have implemented variable frequency sinusoidal source (VFSS) of our excitation waveforms within an FPGA. This VFSS generates quadrature outputs which are used as reference signals for phase-sensitive demodulation of the measured voltages. After digitizing input analog signal with a high speed and high resolution analog to digital converter, input signal multiplied by cosine and sinusoidal reference signal which are constructed inside the FPGA. Then the outputs can be achieved by filtering the DC frequency. According to equation (11), by using a variable frequency, sinusoidal source provides us a spectrum analyzing for an input and let us to be relaxed in designing the reference sinusoidal source which is used in sensor section.
A sin(T I )
(4) (5) (6)
ref=
DC component A / 2 cos(T I )
ref= 2
A2 / 2 cos(T 2 I )
ref= 3
A3 / 2 cos(T 3 I )
Because of parallelism of two paths, the outputs will be ready at the same time and this is the other advantage of using FPGA to implement the parallel structures to increase the detection speed. To decrease reference mismatch errors, we have used one source and the other reference signal is created with 90 degrees displacing of phase.
(7) (8) (9) (10)
Where A is the amplitude of the input signal which depends on the tissue and is the phase of input signal which depends on the tissue structure and I is the difference phase of input signal and reference signal which is constant and can be calculated and calibrated for whole system.Vin1 comes from sensors has contacted to the tissue and Vref1 and Vref2 has been generated in the FPGA. Out1 and Out2 are output signals which we interested in at EIT/EIS applications. The FIR filter central frequency is around zero which can be adjusted by the designer. The bandwidth of the LPF filter is 10 Hz. By controlling the filter degree, the frequency response of FIR filter can be narrower, which cuts off more noise and other interferences but in return, it needs more settling time and gates to be implemented. With this selection, the system can work almost 10 Hz lower and 10 Hz upper than 50 Hz in which noise is high and it is harmful for biomedical applications.
D A C
Signal from living tissue
Computer
Fig. 2. The block diagram of the conventional EIT/EIS receivers with Data Acquisition Card (DAC)
Signal from living tissue
A D C
Single chip FPGA
Fig. 3. The block diagram of the proposed EIT/EIS receivers
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3 TABLE II UTILIZATION OF HARDWARE RESOURCES
Fig. 2 illustrates conventional EIT receivers that uses a data acquisition card which usually interface to a computer for this purpose which has high cost with more power consumption and lower mobility but as indicated in Fig.3, our proposed system uses only one chip instead of a whole computer with lower power consumption and high mobility.
FPGA Utilization Summary Logic Utilization Used Available Number of Slice flip flops 2021 21,504 Number of 4 input LUTs 17830 21,504 Logic Distribution Number of occupied Slices 10136 10,752 Number of Slices containing only 10136 10136 related logic Number of Slices containing 0 10136 unrelated logic Number of bonded IOBs 67 240 Number of BUFG/BUFGCTRLs 1 32 Number used as BUFGs 1 Number used as BUFGCTRLs 0
Fig. 4. The block diagram of the digital system on FPGA
III. SIMULATION RESULTS We have implemented a fully digital demodulation technique on a Virtex-4 LX25 FPGA from Xilinx. Two FIR filters have been implemented for filtering the DC component of the input signals. Sufficient FPGA resource is available to achieve 75dB attenuation in the stop band, using coefficients derived from the optimal methods. Fig. 5 illustrates the frequency simulation of the digital FIR filter in MATLAB simulator, which has been implemented on FPGA. A variable frequency digital oscillator has been used to generate a wide range of frequency for mixing with input signals. The Xilinx ISE 8.1i has been used to implement and synthesis the digital system on FPGA. The analysis depicts that output of the system takes about 150msec to settle down. Fig. 6 shows the desired input and output signal verses time. The FPGA features 24,192 logic cells, 48 18×18-bit signed multipliers and 72 block Select RAMs. Table 2 shows the utilization of hardware resources on the chip. The system floor plan is shown in Fig. 8. A 10bit 1MHz analog to digital converter has been used to digitize the input analog signal. Hardware implementation has been illustrated in Fig. 7.
Fig. 6. The transient analysis of the system at different outputs
Fig. 7. Hardware implementation
Fig.
5. The frequency response of FIR filter 001267
Utilization 9% 82% 94% 100% 0% 27% 3%
4 [8]
[8]
[9]
[10] [11]
[12]
[13]
[14]
[15]
[16] Fig. 8. Floorplan of implemented system
CONCLUSION A digital demodulation technique for an EIT system has been presented. In this system, a digital high-Q FIR LPF has been used for narrowband filtering and a sinusoidal reference with variable frequency source implemented to obtain the spectrum of input signal so there is no need for implementing a very accurate sinusoidal source which costs high and needs more complexity and accurate systems.
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