Multilevel Multiphase Space Vector PWM Algorithm With Switching State Redundancy Applied to Three-Phase Four-Leg Converters Óscar López, Jacobo Álvarez, Francisco D. Freijedo, Alejandro G. Yepes, Jano Malvar, Pablo Fernández-Comesaña, Jesús Doval-Gandoy, Andrés Nogueiras, Alfonso Lago and Carlos M. Peñalver Electronics Technology Department University of Vigo Vigo, Spain ES-36210 Email:
[email protected]
Abstract—Three-phase four-leg voltage-source converters are used in inverter, rectifier and active filter applications to control the neutral current caused by unbalanced or nonlinear loads. From the modulation point of view, a four-leg converter can be considered as a four-phase system. Hence, the modulation task can be carried out with a generic multiphase modulation algorithm. In this paper, a recent multilevel multiphase space vector PWM algorithm with switching state redundancy is particularized for multilevel three-phase four-leg converters. The obtained algorithm is compared with an existing three-dimension modulation technique showing important similarities. Finally, the new algorithm is implemented in a low-cost field-programmable gate array and it is tested with a five-level cascaded full-bridge inverter.
I. I NTRODUCTION In four wire systems, unbalanced or nonlinear loads and unbalanced sources can cause large neutral currents. The extra leg of four-leg converters provides an effective neutral connection which allows a precise current control [1]. The growing interest in four-leg converters for three-phase fourwire systems focuses in applications such as distributed power generation, active power filters, fault-tolerant rectifiers and common mode noise reduction. The carrier-based pulse-width modulation (PWM) can be easily applied to four-leg converters [2] even for multilevel topologies [3]. The application of the space vector pulsewidth modulation (SVPWM) to four-leg converters is more involved. In fact, most of the SVPWM algorithms that have been developed to four-leg converters are devoted to two-level converters [4]–[6]. From the modulation point of view, a four-leg converter can be considered as a four-phase converter. Therefore, the general multilevel multiphase SVPWM techniques developed in [7] and [8] can be applied to solve the space vector modulation problem in four-leg converters. This paper is the last one of a series of four papers that show the application of both multiphase multilevel SVPWM techniques to three-phase converters with three and four legs [9]–[11]. The application of the multiphase modulation technique in [7] to multilevel
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converters with three legs provides the simple modulation algorithm in [9], which is fully equivalent to the previous threedimensional (3D) SVPWM algorithm presented in [12]. If the technique in [7] is applied to multilevel four-leg converters then the result is the novel four-dimensional (4D) SVPWM algorithm presented in [10]. The modulation technique in [7] does not make use of the switching state redundancy available in multilevel converters, which allows to use different switching state combinations with the same phase-to-phase voltages but with different homopolar voltage component. Consequently, the modulation index range available with the SVPWM algorithms in [9] and [10] is not optimal and it can be extended. Such problem is solved by the multilevel multiphase SVPWM technique in [8] that takes advantage of the switching state redundancy. The application of this modulation technique to three-phase three-leg converters provides the very simple algorithm in [11] in which the part devoted to calculate the two-dimensional (2D) space vectors is equivalent to the fast 2D SVPWM algorithm presented in [13]. Consequently, the algorithm in [11] can be considered as an extension of the algorithm in [13] that includes a method to select the redundant switching states. This paper presents the application of the multilevel multiphase SVPWM technique in [8] to three-phase four-leg converters. The result is a new 3D SVPWM algorithm that allows to select the switching states of the converter among the available redundant states. This new algorithm is compared with the existing multilevel 3D SVPWM algorithm in [14] showing important similarities. Finally, the modulation technique is implemented in a field-programmable gate array (FPGA) and it is tested with a real prototype based on a fivelevel cascaded full-bridge inverter. II. M ULTILEVEL M ULTIPHASE SVPWM A LGORITHM W ITH S WITCHING S TATE R EDUNDANCY The SVPWM in multiphase converters is a multidimensional problem in which the vector selection can be carried out directly in a multidimensional space. In [8], the mod-
568
ulation problem of a P -phase converter is formulated in a P -dimensional space and it is solved for multilevel topologies in which the output level of every phase is an integer multiple of a fixed voltage step Vdc . The general SVPWM technique in [8] allows to synthesize a reference voltage vector vr = [vr 1 , vr 2 , . . . , vr P ]T by means of a sequence of several T switching vectors vsj = [vs 1j , vs 2j , . . . , vs P j ] during the modulation cycle. Each switching vector must be applied during an interval tj in accordance with the following modulation law ωr =
P +1 X
ω sj tj ,
j=1
P +1 X
tj = 1
where P is the permutation matrix that sorts the comˆ is a upper ponents of ω f in descending order and D triangular matrix made with ones. The dwell times are calculated as ˆf 1, if j = 1 1 − ω j−1 j τj = ω (9) ˆf − vˆf , if 2 ≤ j ≤ P P ω ˆf , if j = P + 1 where ω ˆ f k are the components of the vector that results of sorting the vector ω f . 5) From the integer part, obtain the value of qi as
(1)
j=1
where ω r = [ωr 1 , ωr 2 , . . . , ωr P −1 ]T is the reference space vector that corresponds to the reference vector vr , and ω sj = [ωs 1 , ωs 2 , . . . , ωs P −1 ]T are the space vectors that correspond to the switching vectors vsj . The steps of the generic modulation technique in [8] are the following: 1) Normalize the reference vector respect to the voltage step of the multilevel converter Vdc : Vr . vr = Vdc
qi =
qmin k = ∆q k + Nmin k P k
0
7) Determine the bounding indices qmin and qmax by using expressions (4) qmin = max(qmin 1 , qmin 2 , . . . , qmin P ) 1
(5)
ωf = ωr − ωi .
(6)
4) From the fractional part, obtain the sequence of displaced space vectors ω dj = [ωd 1 , ωd 2 , . . . , ωd P −1 ]T and their dwell times τj by means of the two-level multiphase SVPWM in [7]. The displaced space vector sequence is extracted from the matrix 1 1 ... 1 1 ωd 1 ωd 12 . . . ωd 1P +1 2 2 2 D = ωd 1 ωd 2 . . . ωd P +1 (7) . .. .. .. . . . . . ...
2
P
qmax = min(qmax , qmax , . . . , qmax ).
ω i = integ(ω r )
ωd P 2
ωd P P +1
qmax − qmin + 1 ≥ P.
(15)
(16)
9) Select P consecutive integer numbers {qm } within the interval [qmax , qmin ] according to any desired modulation strategy. 10) Calculate the values of nm and jm that correspond to each selected index qm by means of qm − qi (17) nm = integ P jm = qm − qi − nm P + 1. (18) 11) Obtain the vectors of the switching sequence {vsm } and their switching times {tm } by means of vsm = Tv (ω i + ω dj ) + nm [1, 1, . . . , 1]T
D=P D
(14)
8) Test if the reference does not lie in the overmodulation region with the condition
that is calculated as Tˆ
(12)
where Nmin k and Nmax k are the minimum and maximum levels available in the phase k of the inverter, and ( PP qi − ωi k P − j=1 ωd kj if k < P k ∆q = (13) qi if k = P.
3) Decompose the reference space vector into the sum of its integer part ω i and its fractional part ω f :
ωd P 1
(11)
k
k
qmax = ∆q + Nmax P + (P − 1)
(3)
(P − 1) × P matrix . . . 0 −1 . . . 0 −1 . . .. .. . .. . 0 . . . 1 −1
(10)
6) Calculate the intervals [qmin k , qmax k ] that correspond to each phase k by means of
2) Calculate the reference space vector ω r from vr by using the expression
where Tω is the following 1 0 0 1 Tω = . . .. ..
ωi k .
k=1
(2)
ω r = Tω vr
P −1 X
tm = τjm
(8)
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(19) (20)
Converter Leg a +2 +1 0 –1 –2
Leg b
Leg c
+2 +1 0 –1 –2
Fig. 1.
+2 +1 0 –1 –2
The reference space vector ω r = [ωr a , ωr b , ωr c ]T that corresponds to the normalized reference vector vr is a 3D real vector that can be calculated from (3) as
Leg n +2 +1 0 –1 –2
ω r = Tω vr ∈ R3 where the transformation matrix Tω is 1 0 0 −1 Tω = 0 1 0 −1 . 0 0 1 −1
Functional diagram of multilevel four-leg converter.
× (P − 1) transformation ... 0 . . . 0 . .. . (21) . .. . . . 1 0 ... 0
where Tv is the following P matrix: 1 0 0 1 . . Tv = .. .. 0 0 0
Finally, the trigger signals of transistors are generated from these switching vectors and switching times. The relationship between them depends on the multilevel topology [15]. This multilevel multiphase modulation SVPWM technique with switching state redundancy is valid for converters with any number of levels and phases. It can be applied to the standard multilevel topologies such us the flying capacitor, the diode-clamped and the cascaded full-bridge topologies. It is able to handle all switching states of the converter, without discard any one, and it provides a sorted switching vector sequence that minimizes the number of switchings. In addition, the algorithm is suitable for real-time implementation due to its low computational complexity [8]. III. A PPLICATION TO T HREE -P HASE F OUR -L EG C ONVERTERS A. Calculation of the Space Vector Sequence The functional diagram of a multilevel four-leg converter shown in Fig. 1 is identical to the functional diagram of a multilevel four-phase converter where the neutral leg corresponds to the fourth phase [10]. Hence, the modulation algorithm for four-leg converters can be obtained by making P = 4 in the generic multiphase algorithm that has been summarized in the above section. The switching states of multilevel four-leg converters are 4D integer vectors that gather the state of all converter legs: vs = [vs a , vs b , vs c , vs n ]T ∈ Z4 .
(24)
(25)
Hence, the three components of the reference space vector can be easily calculated from the four components of the normalized reference vector as ωr a = vr a − vr n ωr b = vr b − vr n
(26)
ωr c = vr c − vr n . In accordance with (5) and (6), the integer and fractional parts of the reference space vector are ω i = integ(ω r ) = [ωi a , ωi b , ωi c ]T ∈ Z3 a
b
c T
3
ω f = ω r − ω i = [ωf , ωf , ωf ] ∈ R .
(27) (28)
The next step of the algorithm is to obtain the sequence of displaced space vectors {ω dj } that approximates the fractional part of the reference space vector ω f . In this case, the sequence is formed just by four 3D vectors: ω d1 = [ωd a1 , ωd b1 , ωd c1 ]T , ω d2 = [ωd a2 , ωd b2 , ωd c2 ]T , ω d3 = [ωd a3 , ωd b3 , ωd c3 ]T and ω d4 = [ωd a4 , ωd b4 , ωd c4 ]T . This sequence and the corresponding dwell times τj are obtained by means of the two-level 3D SVPWM algorithm without redundancy developed in [9]. This 3D algorithm provides the results displayed in Table I in which the parameters Cab , Cbc and Cca are calculated by comparing the components of the fractional part of the reference space vector: Cab = [ωf a ≥ ωf b ] Cbc = [ωf b ≥ ωf c ] c
(29)
a
Cca = [ωf ≥ ωf ]. The sequence of space vectors that approximate the reference space vector ω r are calculated as ω s1 = ω i + ω d1
→
τ1
ω s2 = ω i + ω d2
→
τ2
ω s3 = ω i + ω d3
→
τ3
ω s4 = ω i + ω d4
→
τ4 .
(30)
(22)
The reference voltage vector of the SVPWM algorithm gathers the reference for each phase together with the reference for the neutral leg. Taking into account (2), the normalized voltage reference vr is the 4D real vector: Vr = [vr a , vr b , vr c , vr n ]T ∈ R4 . (23) vr = Vdc
B. Selection of the Switching Vector Sequence The following part of the modulation algorithm carries out the selection of a switching vector sequence from the previous sequence of space vectors. Due to switching state redundancy, there are multiple solutions that requires to select one sequence into the available possibilities.
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TABLE I D ISPLACED SPACE - VECTOR SEQUENCE AND DWELL TIMES . Cab Cbc Cca Displaced space-vector sequence
0
0
0
1
1
1
0
1
1
0
1
0
Dwell times
1
ω d1 ω d2 ω d3 ω d4
= [0, 0, 0]T = [0, 0, 1]T = [0, 1, 1]T = [1, 1, 1]T
τ1 τ2 τ3 τ4
= 1 − ωf c = ωf c − ωf b = ωf b − ωf a = ωf a
0
ω d1 ω d2 ω d3 ω d4
= [0, 0, 0]T = [0, 1, 0]T = [1, 1, 0]T = [1, 1, 1]T
τ1 τ2 τ3 τ4
= 1 − ωf b = ωf b − ωf a = ωf a − ωf c = ωf c
1
ω d1 ω d2 ω d3 ω d4
= [0, 0, 0]T = [0, 1, 0]T = [0, 1, 1]T = [1, 1, 1]T
τ1 τ2 τ3 τ4
= 1 − ωf b = ωf b − ωf c = ωf c − ωf a = ωf a
0
ω d1 ω d2 ω d3 ω d4
= [0, 0, 0]T = [1, 0, 0]T = [1, 0, 1]T = [1, 1, 1]T
τ1 τ2 τ3 τ4
= 1 − ωf a = ωf a − ωf c = ωf c − ωf b = ωf b
0
ω d1 ω d2 ω d3 ω d4
= [0, 0, 0]T = [1, 0, 0]T = [1, 1, 0]T = [1, 1, 1]T
τ1 τ2 τ3 τ4
= 1 − ωf a = ωf a − ωf b = ωf b − ωf c = ωf c
ω d1 ω d2 ω d3 ω d4
[0, 0, 0]T
1
= = [0, 0, 1]T = [1, 0, 1]T = [1, 1, 1]T
τ1 τ2 τ3 τ4
By means of the condition given in (16), with four-leg converters the reference does not lie in the overmodulation region if qmax − qmin < 3. (36) The next step is to select four consecutive integer numbers {q1 , q2 , q3 , q4 } within the interval [qmax , qmin ] according to any desired modulation strategy. The values of n1 , n2 , n3 and n4 that correspond to the previously selected indices are calculated from (17) as q1 − qi n1 = integ 4 q2 − qi n2 = integ 4 (37) q3 − qi n3 = integ 4 q4 − qi n4 = integ 4 and the values of j1 , j2 , j3 and j4 by means of (18) as j1 = q1 − qi − 4n1 + 1 j2 = q2 − qi − 4n2 + 1 j3 = q3 − qi − 4n3 + 1
c
= 1 − ωf = ωf c − ωf a = ωf a − ωf b = ωf b
(38)
j4 = q4 − qi − 4n4 + 1. Finally, with a four-leg converter, the four vectors of the switching sequence are calculated from (19) as vs1 = [ωs aj1 + n1 , ωs bj1 + n1 , ωs cj1 + n1 , n1 ]T
The next step of the SVPWM algorithm requires to calculate the value of the parameter qi from the integer part of the reference space vector by means of expression in (10) as qi = ωi a + ωi b + ωi c .
(31)
vs2 = [ωs aj2 + n2 , ωs bj2 + n2 , ωs cj2 + n2 , n2 ]T vs3 = [ωs aj3 + n3 , ωs bj3 + n3 , ωs cj3 + n3 , n3 ]T vs4 = [ωs aj4 + n4 , ωs bj4 + n4 , ωs cj4 + n4 , n4 ]T
and their corresponding switching times by means of (20) as
In four leg converters there are four intervals [qmin a , qmax a ], [qmin b , qmax b ], [qmin c , qmax c ] and [qmin n , qmax n ] that are calculated by means of (11) and (12) as a
a
a
a
t1 = τj1 t2 = τj2 t3 = τj3
a
a
[qmin , qmax ] = [∆q + 3Nmin , ∆q + 3Nmax + 2] [qmin b , qmax b ] = [∆q b + 3Nmin b , ∆q b + 3Nmax b + 2] [qmin c , qmax c ] = [∆q c + 3Nmin c , ∆q c + 3Nmax c + 2] [qmin n , qmax n ] = [∆q n + 3Nmin n , ∆q n + 3Nmax n + 2] (32) where from (13) and taking into account the particular values of ω d1 and ω d4 in Table I then ∆q a = qi − 4ωi a − ωd a2 − ωd a3 − 1 ∆q b = qi − 4ωi b − ωd b2 − ωd b3 − 1
(33)
∆q c = qi − 4ωi c − ωd c2 − ωd c3 − 1
t4 = τj4 .
ω r = [0.27, −2.16, −1.43]T
qmin = max(qmin a , qmin b , qmin c , qmin n ) a
b
c
n
qmax = min(qmax , qmax , qmax , qmax ).
(40)
C. Example Let us consider a reference voltage of 41.7 V for the leg a, −34.5 V for the leg b, −9.3 V for the leg c and 33.5 V for the neutral leg. From (2), if the voltage step of the converter is Vdc = 30 V then the normalized reference voltage vector is Vr vr = = [1.39, −1.15, −0, 31, 1.12]T . (41) Vdc In this case, the reference space vector, calculated by means of (3), is the following 3D vector:
∆q n = qi . The bounding indices qmin and qmax are determined by using expressions in (14) and (15), respectively, as
(39)
(42)
In accordance with (27) and (28), the integer and fractional parts of the reference space vector are
(34)
ω i = integ(ω r ) = [0, −3, −2]T
(43)
(35)
ω f = ω r − ω i = [0.27, 0.74, 0.57]T .
(44)
571
The conditions in (29) provide the following results: a
b
b
c
c
a
Finally, the following switching vector sequence vs1 = vs (n1 , j1 ) = [2, −1, 0, 1]T
Cab = [ωf ≥ ωf ] = 0 Cbc = [ωf ≥ ωf ] = 1
vs2 = vs (n2 , j2 ) = [2, −1, 0, 2]T
(45)
Cca = [ωf ≥ ωf ] = 1.
vs3 = vs (n3 , j3 ) = [2, 0, 0, 2]T
The case 011 in Table I provides the following displaced space vector sequence: ω d1 = [0, 0, 0]T
vs4 = vs (n4 , j4 ) = [2, 0, 1, 2]T .
ω d2 = [0, 1, 0]T
together with following switching times t1 = τ4 = 0.27
(46)
ω d3 = [0, 1, 1]T
t2 = τ1 = 0.26 t3 = τ3 = 0.30.
together with the following dwell times:
are obtained by means of (39) and (40), respectively.
τ1 = 1 − ωf b = 0.26 τ2 = ωf b − ωf c = 0.17 a
τ2 = ωf − ωf = 0.30
Consequently, from (30) the space vector sequence that approximates the reference space vector ω r is ω s1 = [0, −3, 2]T
→
τ1 = 0.26
T
→
τ2 = 0.17
T
ω s3 = [0, −2, 3]
→
τ3 = 0.30
ω s4 = [1, −2, 3]T
→
τ4 = 0.27.
(48)
The value of the index qi is calculated by means of (31) as qi = ωi a + ωi b + ωi c = −5.
[qmin a , qmax a ] = [−14, 5] [qmin c , qmax c ] = [−7, 12]
The 3D SVPWM algorithm for four-leg multilevel converters presented in [14] uses the line-to-neutral values of the reference vector and the switching states to carry out the space vector representation of the system in a 3D space. This transformation is exactly the same transformation in (24) that is used by the new algorithm to calculate the 3D space vectors. The algorithm in [14] makes use of the 3D SVPWM generalized algorithm in [12] to find the four space vectors nearest to the reference vector and to calculate their dwell times: 1 1 1 T [San , Sbn , Scn ] → d1
(49)
If a five-level cascaded full-bridge inverter is considered then the available levels in all legs go from −2 to +2. Hence, Nmin a = Nmin b = Nmin c = Nmin n = −2 and Nmax a = Nmax b = Nmax c = Nmax n = 2 and from (32), the intervals of indices that correspond to the inverter legs are [qmin b , qmax b ] = [−4, 15]
IV. C OMPARISON W ITH E XISTING 3D A LGORITHM
(47)
τ3 = ωf a = 0.27.
ω s2 = [0, −2, 2]
(50)
Consequently, from (34) and (35), the range of the indices for the four legs is [qmin , qmax ] = [−4, 5].
(51)
The length of this interval is greater than four, therefore the reference vector is not in the overmodulation region and it can be accurately synthesized. Among all available possibilities, the following four last indices within the range have been selected: {q1 , q2 , q3 , q4 } = {2, 3, 4, 5}. (52)
j2 = 1
j3 = 2
j4 = 3.
(53)
→
d2
3 3 3 T [San , Sbn , Scn ]
→
d3
4 4 4 T [San , Sbn , Scn ]
→
d4 .
(56)
1 1 1 T [San , Sbn , Scn ] ≡ [ωs a1 , ωs b1 , ωs c1 ]T
→ d1 ≡ τ1
2 2 2 T [San , Sbn , Scn ] 3 3 3 T [San , Sbn , Scn ] 4 4 4 T [San , Sbn , Scn ]
→ d2 ≡ τ2
≡ ≡ ≡
[ωs a2 , ωs b2 , ωs c2 ]T [ωs a3 , ωs b3 , ωs c3 ]T [ωs a4 , ωs b4 , ωs c4 ]T
→ d3 ≡ τ3
(57)
→ d4 ≡ τ4 .
The application of the 3D SVPWM algorithm in [14] to the vector vr = [1.39, −1.15, −0, 31, 1.12]T that was considered in the above example provides the following results:
The values of the nm and jm that correspond to the previous qm indices can be calculated by means of (37) and (38): n1 = 1 n2 = 2 n3 = 2 n4 = 2
2 2 2 T [San , Sbn , Scn ]
But the 3D SVPWM generalized algorithm in [12] is fully equivalent to the 3D SVPWM algorithm for three-phase converters without redundancy in [9], which was used in this paper to calculate the sequence of space vectors that approximates the reference space vector. Therefore, the space vectors and dwell times obtained with both 3D SVPWM algorithms for four-leg converters are exactly the same
[qmin n , qmax n ] = [−13, 6].
j1 = 4
(55)
t2 = τ2 = 0.17
ω d4 = [1, 1, 1]T
c
(54)
1 1 1 [San , Sbn , Scn ] = [0, −3, −2]T
→
d1 = 0.26
2 2 2 [San , Sbn , Scn ] 3 3 3 [San , Sbn , Scn ] 4 4 4 [San , Sbn , Scn ]
= [0, −2, −2]
T
→
d2 = 0.16
= [0, −2, −1]
T
→
d3 = 0.30
= [1, −2, −1]T
→
d4 = 0.27
(58)
which exactly match the results obtained with the new algorithm in (48). Fig. 2 compares the sequence of space vectors
572
Reference voltage
Normalized reference voltage 2
a
Voltage (p.u.)
Voltage (p.u.)
2 1
b 0
n
vn
va
vc
0 −1 −2
−1
0
c
0.2
0.4
−2 1
0.8
1
0.8
1
0.8
1
0.8
1
0.8
1
2 Voltage (p.u.)
0.5 New 3D SVPWM algorithm
4 2
Wa
Wc
Wb
1 0 −1 −2
0
0
0.2
0.4
0.6
Output voltage of leg "n"
−2 2 Voltage (p.u.)
Space vector sequence
0.6
Output voltage of leg "a" 0
−4 0
0.5
1
Multilevel 3D SVPWM algorithm in [14] 4
1 0 −1 −2
2
San
Scn
0
Sbn
0.2
0.4
0.6
Line−to−neutral output voltage 0
4 Voltage (p.u.)
Space vector sequence
vb
1
−2 −4 0
0.5
1
2 0 −2 −4
Difference between both algoritms
0
1 Fig. 2. Comparison of the space vector sequence obtained with both 3D Wa-San Wb-Sbn Wc-Scn SVPWM algorithms. Voltage (p.u.)
Diff. (%)
The algorithm was tested by simulation and in laboratory. In both cases, the considered conditions are a balanced voltage reference, where vr a = 1.9 sin(w t), vr b = 1.9 sin(w t+2π/3) and vr c = 1.9 sin(w t − 2π/3), with a third-harmonic zero sequence vr n = 1.5 sin(3w t + π). The fundamental frequency is 50 Hz and the switching frequency is 10 kHz. Fig. 3 shows the simulation results obtained with Simulink. The four traces in the first plot are the reference voltage for each leg. The subsequent plots are the leg a output voltage, the leg n output voltage, the line-to-neutral output voltage and the line-to-line output voltage. Traces in black are the switched voltages and traces in gray are the same signals after filtering. Leg voltages have an homopolar component, which is injected by the modulation algorithm, that is canceled in the lineto-neutral and line-to-line voltages. Therefore, even though
0.6
4
0
V. E XPERIMENTAL R ESULTS
0.4
Line−to−line output voltage
0.5
{ω sj }−0.5 obtained with both modulation algorithms showing identical results, as well. −1 Consequently, the 3D SVPWM0.5algorithm presented in 1[14] 0 is fully equivalent to the partTime of (p.u.) the new 3D SVPWM that calculates the space vectors and the dwell times, which was described in section III-A. The part that carries out the switching state selection, described in section III-B, is not addressed in [14]. Therefore, the new modulation algorithm for four-leg converters can be considered as an extension of the algorithm in [14] that solves the switching state selection problem.
0.2
2 0 −2 −4 0
0.2
0.4
0.6 Time (p.u.)
Fig. 3.
Simulation results.
the leg voltages do not follow exactly the reference voltages the line-to-neutral and line-to-line voltages are the expected signals. The SVPWM algorithm was described for a five-level inverter by using very-high-speed integrated circuit hardware description language (VHDL) and it was implemented in a Digilent S3 board. Table II shows a summary of the resources used by the implementation. It is important to remark that any block random access memory (RAM) and any multiplier available in the FPGA was used because the algorithm does not need data storage or multiplication operations. Fig. 4 shows the FPGA output waveforms, which correspond to the trigger signals, for the same case illustrated in the above example where vr = [1.39, −1.15, −0, 31, 1.12]T . The experimental results are in accordance with the theoretical results obtained in (54) and (55). The 4D SVPWM algorithm was tested with the five-level cascaded full-bridge inverter shown in Fig. 5, which is the same setup used in [10]. The voltage of all dc sources is Vdc = 30 V. Fig. 6 shows a diagram and a photograph of
573
TABLE II R ESOURCES SUMMARY. Target Device : xc3s200 Number of Slice Flip Flops: Number of 4 input LUTs: Number of occupied Slices: Total Number 4 input LUTs: Number of bonded IOBs: IOB Flip Flops: Number of Block RAMs: Number of MULT18X18s: Number of GCLKs: Number of Startups: Total equivalent gate count
Leg a:
2
2
2
2
dSPACE
2,024 out of 2,330 out of 1,725 out of 2,597 out of 63 out of 66 0 out of 0 out of 8 out of 1 out of for design:
2
2
3,840 3,840 1,920 3,840 173
FPGA
Control
52% 60% 89% 67% 36%
SVPWM
dc link
12 0% 12 0% 8 100% 1 100% 32,226
Trigger signals
Optical link
Inverter
Load
Inverter Optical link
2
FPGA Leg b:
-1
-1
0
0
0
-1
-1
dSPACE
dc link Leg c:
0
0
0
1
0
0
0
Load Leg n:
1
2
2
2
2
2
1
Fig. 6.
Fig. 4.
FB
FB
FB
FB
As expected, neither the homopolar components of the leg voltages nor the third harmonic of the neutral voltage are present in this voltage.
Trigger signals.
FB FB
VI. C ONCLUSION
FB FB
Load
FB
Fig. 5.
Diagram and photograph of the experimental test setup.
Four-leg five-level cascaded full-bridge inverter.
the experimental setup used in tests. It includes the power converter, the FPGA board and a personal computer with a dSPACE DS1103 PPC Controller Board. Fig. 7 shows the measured output voltage of the inverter in the same case simulated in Fig. 3. The experimental results agree with the simulation results. Line-to-line voltage, shown in Fig. 7b, has a large third harmonic which corresponds to the leg n reference. Line-to-neutral voltage, shown in Fig. 7c, is a ninelevel voltage with a very low total harmonic distortion (THD).
In this paper the recent SVPWM algorithm for multilevel multiphase converters that takes into account the switching state redundancy is particularized for three-phase four-leg converters. The particularized algorithm is a 3D SVPWM algorithm that provides a sorted switching vector sequence, which minimizes the number of switchings. It can be used with the standard multilevel topologies with any number of levels. It is suitable for real-time implementation due to its low computational complexity. The five-level version of this algorithm was implemented in a low-cost FPGA and it was successfully tested by using a four-leg cascaded full-bridge inverter. The part of the new algorithm that calculates the space vector sequence resulted to be equal to an existing 3D SVPWM algorithm specifically designed for four-leg converters. Consequently, the new algorithm can be considered as an extension of the old one in which the problem of the redundant switching state selection has been solved. ACKNOWLEDGMENT This work was supported by the Spanish Ministry of Education and Science under the project number DPI2009-07004. R EFERENCES [1] G. Dong and O. Ojo, “Current regulation in four-leg voltage-source converters,” IEEE Trans. Ind. Electron., vol. 54, no. 4, pp. 2095–2105, Aug. 2007.
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(a) Leg voltages Vs a and Vs n
(b) Line-to-neutral voltage Vs a − Vs n
(c) Line-to-line voltage Vs b − Vs a Fig. 7. Inverter output voltage. Ch1 and Ch3: switched voltages; Ch2 and Ch4: filtered voltages.
[2] J.-H. Kim and S.-K. Sul, “A carrier-based PWM method for threephase four-leg voltage source converters,” IEEE Trans. Power Electron., vol. 19, no. 1, pp. 66–75, Jan. 2004. [3] J.-H. Kim, S.-K. Sul, and P. N. Enjeti, “A carrier-based PWM method with optimal switching sequence for a multilevel four-leg voltage-source inverter,” IEEE Trans. Ind. Appl., vol. 44, no. 4, pp. 1239–1248, Jul. 2008.
[4] R. Zhang, V. Prasad, D. Boroyevich, and F. Lee, “Three-dimensional space vector modulation for four-leg voltage-source converters,” IEEE Trans. Power Electron., vol. 17, no. 3, pp. 314–326, May 2002. [5] R. Baghernejad, A. Bakhshai, and D. Yazdani, “A real-time neurocomputing three-dimensional space vector algorithm for three-phase four-leg converters,” in Proc. IEEE Industrial Electronics Conf. IECON, Raleigh, NC, 6–10 Nov. 2005, pp. 1067–1070. [6] M. Perales, M. M. Prats, R. Portillo, J. L. Mora, J. I. Leon, and L. G. Franquelo, “Three-dimensional space vector modulation in abc coordinates for four-leg voltage source converters,” IEEE Power Electron. Lett., vol. 1, no. 4, pp. 104–109, Dec. 2003. [7] O. López, J. Alvarez, J. Doval-Gandoy, and F. D. Freijedo, “Multilevel multiphase space vector PWM algorithm,” IEEE Trans. Ind. Electron., vol. 55, no. 5, pp. 1933–1942, May 2008. [8] ——, “Multilevel multiphase space vector PWM algorithm with switching state redundancy,” IEEE Trans. Ind. Electron., vol. 56, no. 3, pp. 792–804, Mar. 2009. [9] O. López, J. Alvarez, J. Doval-Gandoy, F. D. Freijedo, A. Nogueiras, and C. M. Peñalver, “Multilevel multiphase space vector PWM algorithm applied to three-phase converters,” in Proc. IEEE Industrial Electronics Society Conf. IECON, Orlando, FL, 10–13 Nov. 2008, pp. 3288–3293. [10] O. López, J. Alvarez, J. Doval-Gandoy, F. D. Freijedo, A. Lago, and C. M. Peñalver, “Four-dimensional space-vector pulse-width modulation algorithm for multilevel four-leg converters,” in Proc. IEEE Industrial Electronics Society Conf. IECON, Orlando, FL, 10–13 Nov. 2008, pp. 3250–3257. [11] O. López, J. Alvarez, F. D. Freijedo, J. Doval-Gandoy, A. Nogueiras, A. Lago, and C. M. Peñalver, “Multilevel multiphase space vector PWM algorithm with switching state redundancy applied to three-phase converters,” in Proc. IEEE Industrial Electronics Conf. IECON, Porto, Portugal, 3–5 Nov. 2009. [12] M. M. Prats, L. G. Franquelo, J. I. Leon, R. Portillo, E. Galvan, and J. M. Carrasco, “A 3-D space vector modulation generalized algorithm for multilevel converters,” IEEE Power Electron. Lett., vol. 1, no. 4, pp. 110–114, Dec. 2003. [13] N. Celanovic and D. Boroyevich, “A fast space-vector modulation algorithm for multilevel three-phase converters,” IEEE Trans. Ind. Appl., vol. 37, no. 2, pp. 637–641, Mar. 2001. [14] L. G. Franquelo, M. M. Prats, R. Portillo, J. I. Leon, M. A. Perales, J. M. Carrasco, E. Galvan, and J. L. Mora, “Three-dimensional spacevector modulation algorithm for four-leg multilevel converters using abc coordinates,” IEEE Trans. Ind. Electron., vol. 53, no. 2, pp. 458–466, Apr. 2006. [15] O. López, J. Doval-Gandoy, C. M. Peñalver, J. Rey, and F. D. Freijedo, “Redundancy and basic switching rules in multilevel converters,” Int. Review of Electrical Engineering, vol. 0, no. 0, pp. 66–73, Jan.–Feb. 2006.
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