electronics Article
Optimization of Line-Tunneling Type L-Shaped Tunnel Field-Effect-Transistor for Steep Subthreshold Slope Faraz Najam
and Yun Seop Yu *
Department of Electrical, Electronic and Control Engineering and IITC, Hankyong National University, Anseong 17579, Korea;
[email protected] * Correspondence:
[email protected]; Tel.: +81-31-670-5293 Received: 12 October 2018; Accepted: 22 October 2018; Published: 24 October 2018
Abstract: The L-shaped tunneling field-effect-transistor (LTFET) has been recently introduced to overcome the thermal subthreshold limit of conventional metal-oxide-semiconductor field-effect-transistors (MOSFET). In this work, the shortcomings of the LTFET was investigated. It was found that the corner effect present in the LTFET effectively degrades its subthreshold slope. To avoid the corner effect, a new type of device with dual material gates is presented. The new device, termed the dual-gate (DG) LTEFT (DG-LTFET), avoids the corner effect and results in a significantly improved subthreshold slope of less than 10 mV/dec, and an improved ON/OFF current ratio over the LTFET. The DG-LTFET was evaluated for different device parameters and bench-marked against the LTFET. This work presents the optimum configuration of the DG-LTFET in terms of device dimensions and doping levels to determine the best subthreshold, ON current, and ambipolar performance. Keywords: band-to-band tunneling; L-shaped tunnel field-effect-transistor; double-gate tunnel field-effect-transistor; corner-effect
1. Introduction Tunnel field-effect-transistors (TFETs) are being actively pursued as a potential replacement to conventional metal-oxide-semiconductor (MOS) technology [1]. TFETs offer a sub-thermal subthreshold slope (SS) but suffer from limited ON current ION performance [2]. To overcome the limit, different types of line tunneling type TFETs have been introduced, including L-shaped [3] (LTFETs), U-shaped [4] (UTFETs), and Z-shaped [5] TFETs (ZTFETs). Among them, only the LTFET has been experimentally demonstrated [3]. It was found using device simulations that the 2D corner effect [6] present in LTFETs degrades its subthreshold performance. In order to remove SS degradation due to the kink effect induced by the source corner, the fully depleted rounded corner with a gradual doping profile was used [6]. The LTFET still achieves a sub-thermal SS, but as shown in this work there is room for significant improvement in the subthreshold performance of LTFETs. To achieve this improvement, a new device based on the original LTFET is introduced. The new device uses a dual-gate (DG) structure and is termed the DG-LTFET. The two gates (gate1 and gate2) have different workfunctions and different heights. The DG-LTFET was thoroughly evaluated for different device parameters, including the source region height, gate1 and gate2 heights, gate1 and gate2 workfunctions, channel thickness, and drain doping levels. Optimum dimensions and drain doping level were determined for the DG-LTFET. Section 2 briefly discusses the corner-effect problem of the LTFET. Section 3 introduces the DG-LTFET and compares its results with the LTFET. Section 4 presents the conclusion.
Electronics 2018, 7, 275; doi:10.3390/electronics7110275
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introduces the DG-LTFET and compares its results with the LTFET. Section 4 presents the conclusion. Electronics 2018, 7, 275 2 of 11 2. The LTFET: The Corner Effect 2. The LTFET: The Corner Effect Figure 1 shows a schematic for LTFET. The p+ (1020 cm−3) doped source region overlaps the gate + (1020 cm −3 ) doped 12 cm−3 with Figure the n− 1(10 channel sandwiched in p between them. This sandwiched is shows a)schematic for LTFET. The source regionchannel overlapsregion the gate − 12 − 3 termed There) is also a part of the channel termed RoffsetThis in which there is channel an offsetregion presentis with theasnRnonoffset (10 . cm channel sandwiched in between them. sandwiched between the source. and theisgate, indicted Figuretermed 1. The following parameters usedpresent for all termed as Rnonoffset There also aaspart of thein channel Roffset in which there iswere an offset devices in this workasunless otherwise source height (Hs) were = 40 used nm, oxide betweenconsidered the source and the gate, indicted in Figurespecified: 1. The following parameters for all thickness (tox) = 2 nm, of Runless nonoffset otherwise (Tj) = 5 nm,specified: channel length ch) = 50 height of R offset (H offset) devices considered in length this work source (L height (Hnm, ) = 40 nm, oxide thickness s =(tox 10) = nm, height ofofRR nonoffset (H(T nonoffset = Hschannel , gate height g1) = = 50 Hsnm, + (H offset −of toxR)offset = 48(Hnm, 2 nm, length length (H (Lch height ) = 10 nm, j ) = 5) nm, offsetdielectric nonoffset 20 cm−3. permittivity εox = 25, metal gate Wg1 rk_LTFET eV, and (Nd) = 10 height of Rnonoffset (Hnonoffset ) = Hworkfunction ) = H=s +4.72 (Hoffset − toxdrain ) = 48doping nm, dielectric permittivity s , gate height (H εox = 25, metal gate workfunction Wrk_LTFET = 4.72 eV, and drain doping (Nd ) = 1020 cm−3 .
Figure1.1.Schematic Schematicof ofthe theL-shaped L-shapedtunneling tunnelingfield-effect-transistor field-effect-transistor(LTFET). (LTFET). Figure
Sentaurus technology-computer-aided-design tool (TCAD) was used as the simulator [7]. Sentaurus technology-computer-aided-design tool (TCAD) was used as the simulator [7]. The The following models were used in the simulation: the dynamic nonlocal band-to-band-tunneling following models were used in the simulation: the dynamic nonlocal band-to-band-tunneling (BTBT) model, Fermi statistics, and the constant mobility model. The dynamic nonlocal BTBT model (BTBT) model, Fermi statistics, and the constant mobility model. The dynamic nonlocal BTBT model calculates BTBT in both lateral and 1D directions. Crystal orientation is assumed to be in calculates BTBT in both lateral and 1D directions. Crystal orientation is assumed to be in all all devices. A constant electron effective tunneling mass of 0.19 mo was used in all simulations [8]. devices. A constant electron effective tunneling mass of 0.19 mo was used in all simulations [8]. All All simulations were performed at a drain source bias V ds = 0.1 V unless otherwise specified. simulations were performed at a drain source bias Vds = 0.1 V unless otherwise specified. For analysis to follow, drain-source current (I ) versus gate-source bias (V gs ) characteristics of For analysis to follow, drain-source current (Ids ds) versus gate-source bias (Vgs) characteristics of the LTFET are shown in Figure 2a. There is a direct overlap between gate and source in Rnonoffset , the LTFET are shown in Figure 2a. There is a direct overlap between gate and source in Rnonoffset, and and the electric field in Rnonoffset is in the 1D direction. In Roffset , however, the electric field from the gate the electric field in Rnonoffset is in the 1D direction. In Roffset, however, the electric field from the gate converges around the sharp source corner marked by an X in Figure 1. This increases the potential in converges around the sharp source corner marked by an X in Figure 1. This increases the potential R as compared to Rnonoffset for any given bias (until potential saturates due to electron inversion). inoffset Roffset as compared to Rnonoffset for any given bias (until potential saturates due to electron Figure 2b shows the surface potential at V gs = 0 V. It can be seen that, because the electric field inversion). Figure 2b shows the surface potential at Vgs = 0 V. It can be seen that, because the electric converges around the sharp source corner [6], the potential in Roffset has increased. Since the potential field converges around the sharp source corner [6], the potential in Roffset has increased. Since the is higher in Roffset asincompared to Rnonoffset threshold voltage for BTBT in ) is lower offset (V potential is higher Roffset as compared to, the Rnonoffset , the threshold voltage forRBTBT inth_Roffset Roffset (V th_Roffset) than the threshold voltage for BTBT in R (V ). nonoffset th_Rnonoffset is lower than the threshold voltage for BTBT in Rnonoffset (Vth_Rnonoffset). Figure 3a,b show the tunneling rate (G ) contour plot and and Gtun ,Grespectively, at V gs = 0.21 V which tun Figures 3a,b show the tunneling−rate (Gtun) contour plot tun, respectively, at Vgs = 0.21 V 13 A (from Figure 2a). It is obvious from Figure 3 that the BTBT is the bias needed to generate I = 10 ds −13 which is the bias needed to generate Ids = 10 A (from Figure 2a). It is obvious from Figure 3 that only takesonly placetakes in Roffset , whereas completely switchedswitched off. Figureoff. 4a Figure shows G at several nonoffset is the BTBT place in Roffset,Rwhereas Rnonoffset is completely 4atun shows Gtun V values. From Figure 4a, V and V can be found to be around V = 0.17 gs gs th_Roffset th_Rnonoffset at several Vgs values. From Figure 4a, Vth_Roffset and Vth_Rnonoffset can be found to be around Vgs = 0.17 VV and 0.24 0.24 V, V, respectively. Gtun atat V gs = 0.24 V. Figure 4a th_Rnonoffset and respectively.Figure Figure4b4bshows showsthe the Gtuncontour contourplot plot Vgs= =VV th_Rnonoffset = 0.24 V. Figure 4a shows that G in R just after it turns on, is always higher and has a much larger BTBT tunin Rnonoffset nonoffset shows that Gtun just after it turns on, is always higher and has a much larger BTBT areaarea (in (in the y direction) as compared to Roffset . Thus, whenever Rnonoffset turns on, it dominates over Roffset . The reason why Gtun is higher in Rnonoffset is simply because the BTBT paths in Roffset are laterally
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the y direction) as compared to Roffset. Thus, whenever Rnonoffset turns on, it dominates over Roffset3. ofThe 11 the y direction) ashigher compared Roffset. Thus, whenever Rnonoffset turns on, it dominates over Roffset. The reason why Gtun is in Rto nonoffset is simply because the BTBT paths in Roffset are laterally oriented whysource Gtun isto higher in Rnonoffset simply because the BTBT paths in Roffset are laterally oriented orreason 2D from the surface in Ris offset, whereas the BTBT paths in Rnonoffset are 1D. The 2D BTBT or 2D from source to the surface in R offset ,Rwhereas the paths inRRoffset nonoffset are 1D. oriented or 2D from source to the , whereas the BTBT in .Rnonoffset areThe 1D.2D TheBTBT 2D paths being naturally longer thansurface the 1Dinpaths in aBTBT lower Gtunpaths in offsetresult pathspaths beingbeing naturally longer thanthan the 1D result in a lower Gtun in Roffset BTBT naturally longer thepaths 1D paths result in a lower Gtun in .Roffset .
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10 -5 Rnonoffset + Roffset 10 Vds=0.10 V Rnonoffset + Roffset -8 Only Vds=0.10 V R nonoffset 10 -8 10 Only Rnonoffset -11 10 -11 Vth_Rnonoffset 10 -14 Vth_Rnonoffset =0.24 V 10 -14 =0.24 V 10 V th_Roffset=0.17 V -17 10 -17 Vth_Roffset=0.17 V 10
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Figure2.2. (a) (a)IIds ds-V -Vgs of the the LTFET. LTFET.VVth_Rnonoffset th_Rnonoffset = 0.24 VV and Vth_Roffset = 0.17 V. (b) Figure transfer characteristics characteristics of = 0.24 and V th_Roffset = 0.17 V. gs transfer Figure 2.along (a) Idsthe -Vgscutline transfer characteristics of at theVgs LTFET. Vth_Rnonoffsetis=higher 0.24 V in and Vth_Roffset = 0.17 V. (b) Potential shown in the inset = 0 V. Potential R offset . (b) Potential along the cutline shown in the inset at V gs = 0 V. Potential is higher in Roffset . Potential along the cutline shown in the inset at Vgs = 0 V. Potential is higher in Roffset.
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Figure 3. (a) Gtun contour plot at Vgs = 0.21 V, which is the bias needed to generate Ids = 10−13 A and (b) 13 A (a)GG tun contour plot 0.21 V,V, which is is thethe bias needed to generate Ids =I 10−13 A− and (b) Figure 3.3.(a) plot at at VVgsgs= = 0.21 which bias needed to generate tun extracted from (a). GFigure tun contour ds = 10 tun extracted from (a). G and (b) Gtun extracted from (a).
From Figure 4a, it can be observed that, for a large part of the subthreshold region (Vgs < 0.24 From Figure it can that, for a large part ofsubthreshold the subthreshold region gs < V), 0.24 From Figure 4a,4a, it can be be observed forand a large part ofisthe region (V gs Gtun in ,RRoffset , demonstrated in Figure 4a, aturn significant and with the condition G tunwith in R nonoffset > G tun G in R offset , demonstrated in Figure 4a, a significant the subthreshold region, and the condition in R > G in R , demonstrated in tun tun nonoffset offset improvement in SS could be expected. improvement in SS could be expected. Figure a significant improvement in SS be expected. In4a, other words, the Rnonoffset could becould regarded as a parasitic region with a parasitic, fringing In other words, the R nonoffset could be regarded parasitic region withSince awith parasitic, fringing In other words, the R could be regarded as a parasitic region parasitic, capacitance originating from nonoffset the bottom of the gate toas thea sharp source corner. theapotential is capacitance originating from the bottom of the gate to the sharp source corner. Since the potential fringing capacitance originating from the bottom of the gate to the sharp source corner. different in this area (Figure 2b), the capacitance associated with this region is different from theis in this area (Figure in 2b), capacitance associated with this region iswith different from the Since the potential is different thisthe area (Figure 2b), the capacitance associated this region is Rdifferent nonoffset region. If Vth_Rnonoffset < Vth_Roffset could be achieved, as is demonstrated below, the effect of this R nonoffset from region. If V th_Rnonoffset < V th_Roffset could be achieved, as is demonstrated below, the effect of this different the R region. If V < V could be achieved, as is demonstrated nonoffset th_Rnonoffset parasitic capacitance could be practically eliminated, th_Roffset and this is the purpose of the device proposed parasitic capacitance could practically eliminated, this eliminated, is the the purpose theisdevice proposed below, the effect of this parasitic capacitance could be practically andofthis the of below. Since drain is not in be close proximity to Roffset /Rand nonoffset, where BTBT current is purpose generated, below. Since drain is not in close proximity to R offsetproximity /R nonoffset, where the BTBT current is generated, the device proposed below. Since drain is not in close to R /R , where the BTBT offset nonoffset gate-drain capacitance fringing capacitance is not expected to influence the potential and BTBT gate-drain capacitance fringing capacitance not expected to influence potential and BTBT current is generated, gate-drain capacitance isfringing capacitance is not the expected to influence significantly at high frequency. significantly at high frequency. the potential and BTBT significantly at high frequency.
Electronics 2018, 7, 7, 275 Electronics 2018, x FOR PEER REVIEW Electronics 2018, 7, x FOR PEER REVIEW Rnonoffset Rnonoffset
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10 Vgs=0.165 V 28 1025 Vgs=0.17 V Vgs=0.165 V Vth_Rnonoffset 10 Vgs=0.21 V 25 Vgs=0.17 V Vth_Rnonoffset 1022 =0.24 V Vgs=0.24 V Vgs=0.21 V 10 Vgs=0.25 V 22 =0.24 V Vgs=0.24 V 1019 Vgs=0.27 V Vgs=0.25 V 10 Vgs=0.3 V 19 Vgs=0.27 V 1016 Vth_Roffset Vgs=0.4 V Vgs=0.3 V 10 Vgs=0.5 V 16 Vth_Roffset Vgs=0.4 V =0.17 V 1013 10 V =0.1 VVgs=0.5 V =0.17 V 13 V =0.1 V Cutline 10 Cutline 0.00 0.01 0.02 0.03 0.04 0.05 y [μm] 0.00 0.01 0.02 0.03 0.04 0.05
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Figure 4. (a) Gtun at different Vgs. (a) Vth_Rnonoffset = 0.24 V and Vth_Roffset = 0.17 V. (b) Gtun contour plot at Figure 4. (a) Gtun at different Vgs .(a) (a)VVth_Rnonoffset == 0.24 Vthe and Vth_Roffset 0.17 V. tun contour plot at gs = V4. th_Rnonoverlap = 0.24 V. In (b), arrow indicates height of R=nonoffset . (b) V Figure (a) Gtun at different V gs .yellow 0.24 V and V th_Roffset = 0.17 V. G (b) Gtun contour th_Rnonoffset gs = Vth_Rnonoverlap = 0.24 V. In (b), yellow arrow indicates the height of Rnonoffset. V plot at V gs = V th_Rnonoverlap = 0.24 V. In (b), yellow arrow indicates the height of Rnonoffset .
3. DG-LTFET 3. 3. DG-LTFET DG-LTFET 3.1. The DG-LTFET: Basic Device Physics 3.1.3.1. The DG-LTFET: Basic Device Physics The DG-LTFET: Basic Device Physics In order to achieve the condition Vth_Rnonoffset < Vth_Roffset, the DG-LTFET is presented in Figure 5a. In In order to achieve the the condition V th_Rnonoffset < Vth_Roffset , lower Gtun. The more efficient 1D BTBT from the source to Rnonoffset, with a higher Gtun takes place at a exists in the LTFET. With Rnonoffset not conducting the device does not utilize its channel fully during higher bias in the subthreshold region. In other words, the condition, that is, Vth_Rnonoffset > Vth_Roffset, the subthreshold region. A new type of device based on the LTFET was introduced in this work. The device exists in the gate LTFET. Withwith Rnonoffset not conducting the increases device does not utilize channel fully during uses a dual structure Wrk_gate1 < Wrk_gate2 . This the potential in Rits nonoffset and lowers theVth_Rnonoffset subthreshold A new typetheofthreshold device based on of thethe LTFET this work. The . Theregion. DG-LTFET reverses condition LTFET,was that introduced is, it lowers Vin th_Rnonoffset device uses ita
