Subthreshold current reduction for decoded-driver by ... - IEEE Xplore

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 28, NO. 11, NOVEMBER 1993

Subthreshold Current Reduction for Decoded-Driver by Self-Reverse Biasing Takayuki Kawahara, Member, IEEE, Masashi Horiguchi, Member, IEEE, Yoshiki Kawajiri,

Goro Kitsukawa, Tokuo Kure, Associate Member, IEEE, and Masakazu Aoki, Member, IEEE

Abstract- Analytical expressions are presented for subthreshold current reduction in a Decoded-Driverby self-reverse biasing, which is inherently required for low-voltage, low-power, highspeed DRAM's for portable equipment. The scheme involves inserting a switching MOS transistor between the driver circuits and its power supply line. The subthreshold current of the Decoded-Driver is reduced to the table iorder of lo-' in the practical temperature range (250-350 K) with 254 mV of selfreverse biasing voltage, while the delay time is only 3% more than in conventional schemes. The transition time of 1 ms from the operating state to the low subthreshold current state is sufficient to reduce the subthresholdcurrent. The rapid recovery time of 1 ns from the low subthreshold current state does not interrupt the start of normal operation. The of subthreshold current reduction was confirmed experimentally using a test chip fabricated with 0.25-pm technology.

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I. INTRODUCTION

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RAM'S for portable equipment require both low-power, low-voltage operation for battery use and high speed for treating, e.g., moving pictures in multimedia applications. A 1.5-V DRAM was reported [l] with an estimated 10 mW of power consumption at a I-ps cycle time at the 16-Mb DRAM level, despite the DRAM being known as a difficult device under low-voltage operation in portable equipment. However, to obtain higher speed at low-voltage operation, the threshold voltage for the MOS transistor in DRAM's must be lowered. This is limited by the subthreshold conduction [2], [3] of the MOS transistor, which raises the OFF current[4]. In future high-density DRAM's this current will exceed the capacity of the back-up battery. For example, as shown in Fig. 1, the data retention current of a 256-Mb DRAM with a threshold voltage of 0.1 V for high performance is about one order larger than that of a 64-Mb DRAM. It could be reduced by operating at liquid nitrogen temperature [5], but roomtemperature operation is essential for portable equipment. On the other hand, a memory LSI mainly consists of blocks containing a large number of simple logical circuits arranged repeatedly (Decoded-Driver),where only a few circuits operate at the same time. The decoders, word drivers, and Y-drivers of a DRAM are examples of such circuits. The subthreshold current from these drivers determined the whole chip current because the total gate width of such drivers occupies more Manuscnpt received April 30, 1993; revised July 2, 1993.

T. Kawahara, M. Horiguchi, G. Kitsukawa, T. Kure, and M. Aoki are with the Central Research Laboratory, Hitachi Ltd., Kokubunji, Tokyo 185, Japan. Y. Kawajiri is with the Semiconductor and Integrated Circuits Division, Hitachi Ltd., Shinjuku, Tokyo 162, Japan. IEEE Log Number 92 1 184 1.

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than half of that in the whole chip and a low threshold voltage is necessary for high speed. Therefore, subthreshold current reduction for the Decoded-Driver is the primary issue for lowvoltage, high-speed DRAM's. The same type of circuit is also important in MPU, as the ratio of on-chip cache memory to the whole chip increases [6] for higher performance, where the situation is the same as the memory LSI. To meet these requirements, we proposed a subthreshold current reduction scheme for word drivers [7] with 53pA of data-retention current in the whole chip. However, there have been no analytical reports about subthreshold current reduction including the dynamical behaviors. This paper presents analytical expressions for the subthreshold reduction scheme in a Decoded-Driver in both the steady and dynamical states. The subthreshold current reduction technique for the Decoded-Driver based on selfreverse biasing is described in Section 11. The effect of subthreshold current reduction by this technique, in both the steady and dynamical states, is analytically discussed in Section 111, and some experimental results are shown in Section IV. 11. SUBTHRESHOLD CURRENT REDUCTIONFOR DECODED-DRIVER BY SELF-REVERSE BIASING

A. Principle of Subthreshold Current Reduction The dependence of the drain current IDS on the gate-source voltage VGSwhen it is below the threshold voltage, i.e., in the

0018-9200/93$03 8.00 0 1993 IEEE

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KAWAHARA et al.: CURRENT REDUCTION FOR DECODED-DRIVER

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subthreshold region, is expressed [8] assuming that the drain voltage dependence can be ignored:

where W is the gate width, VT is the threshold voltage, IOand WOare the gate width and the drain current at the threshold voltage, and S is the subthreshold swing defined in terms of the depletion-layer capacitance CD and the insulator capacitance Ci:

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In a conventional CMOS driver in the stand-by state, when there is an input at VC, an n-channel MOS transistor (nMOS) is ON and a p-channel transistor (PMOS) is OFF, as shown in Fig. 2, or, when the input is at GND, the nMOS is OFF, and the PMOS is ON. Although the region under the gate is weakly inverted in an OFF state transistor, the subthreshold current is at VGS = OV expressed by (3) is small enough to provide the small OFF current of a CMOS LSI:

(3) However, when the threshold voltage is reduced from VT to VT, (shown in the right-hand side of the figure) as a result of scaling the operation voltage to retain high performance, the drain current of MOS at VGS = OV increases from is to is/. Physical limitations prevent S from being scaled below In 10 according to the lower threshold voltage. Therefore, the power consumption in the stand-by state becomes large in memory LSI's because of the large subthreshold current at low-voltage, high-speed operation. This problem is especially serious in battery-operated and battery-backed-up memory LSI's. To reduce this is!, we must provide a way to transfer from the (Y state to state in Fig. 2 to automatically set the source voltage lower than the gate voltage by AVSRB.

B. Circuit Diagram This section describes the subthreshold current reduction technique for Decoded-Driver by self-reverse biasing voltage. The Decoded-Driver is a common type of driver for memory LSI's. It has a group of the same kind of circuits arranged re-

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(b) Fig. 3. Subthreshold-current-reducedDecoded-Driver by self-reverse biasing. WC:Gate width of M c . VTC:Threshold voltage of M c . AVSRB: Self-reverse biasing voltage at the steady state. WO:Gate width of M c . V T D Threshold : voltage of M D . I : Operation current. kSubthreshold current. R: Number of Decoded-Drivers connected to one M c . CO: Output load of Decoded-Driver. C : Parasitic capacitance of common source.

peatedly, but only a few of them operate simultaneously. This circuit organization can drastically reduce the subthreshold current, as shown in Fig. 3. The configuration simply consists of inserting a switching PMOS transistor M c between the power supply Vc and the common source (Vel) of PMOS transistor MD ( M D -~ MO,) of drivers. In the operating state the inputs of a few active drivers (for example, only one) changes to a low level, and M c is ON to provide a sufficient current of I to a few active drivers. In the stand-by state, where the inputs of all drivers remain at a level of VC, MC is OFF to reduce the large subthreshold current of drivers M D to a small current of i. The important point is that the drivability of M c in the operating state is sufficient to supply a current of I to only a few MO's of drivers. Therefore, the subthreshold current is also as small as i, corresponding to a few drivers. Thus the common source lower than the gate voltage of Vc. voltage of V& is A V ~ R B This causes the PMOS transistor to have self-reverse biasing between the source and gate, which prevents the subthreshold current flow. Since V& lowering is stopped as AVSRB by

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TABLE I COMPARISON OF PERFORMANCE OF DECODED-DRIVERS Operation

Stand-by

self-reverse biasing, the recovery of lowered V& is quick and power dissipation for recovery is small. Note that the A V ~ R B lowering operation is automatically performed when the standby state is started. The subthreshold current of each driver is reduced and reaches a steady state of i / n for each driver. The layout penalty of the extra MC presents no problem, because only one MC is needed for many Decoded-Drivers. In addition, the gate width of M c is small since the drivability of M c is enough for the few numbers of MD'Sin operation. This scheme is useful for a group of identical circuits where only a few operate simultaneously, such as word drivers, Y drivers, and decoders in memory LSI's. OF TKE SUBTHRESHOLD 111. EVALUATION CURRENT REDUCTION

This chapter quantitatively discusses the subthreshold current reduction obtained by this scheme while maintaining the higher operating speed. The temperature dependence of the subthreshold current reduction, the transition time from the operating state to the low subthreshold current state, and the recovery time back to the operating state are also discussed. Table I summarizes the comparison of the proposed Decoded-Driver with a conventional scheme, and Table I1 summarizes the features of subthreshold current reduction technique. These tables show that the conventional driver, where the common source is directly connected to the supply voltage, has high drivability but a large subthreshold current. On the other hand, the proposed scheme has a very small subthreshold current in the practical temperature range (250-350 K) with only a slight increase in delay time. The evolution time from the operating state to the low subthreshold current state is sufficient to reduce the subthreshold current, and the recovery time from the low subthreshold current state does not interrupt the start of normal operation. Detailed discussions follow.

A . Self-Reverse Biasing Voltage AVSRBin the Steady State The subthreshold current in the proposed scheme is reduced by the self-reverse biasing voltage of AVSRB,where VGSis automatically set to reverse biasing to prevent the subthreshold . voltage is derived as cutrent from flowing as this A V S R BThis follows. The voltage lowering of the common source voltage

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of VC, in Fig. 3 is continued until the current supplied from the M c balances the current flowing to the PMOS MDI MD,. The current from IMC of M c is expressed as follows, assuming the drain voltage dependence can be ignored:

(4) This current balances the current of I M D in MDI - MO, in the steady state.

is obtained as Therefore, from the IWC = IWD,A V ~ R B

In the above equations, WC and VTC are the gate width and the threshold voltage of Mc, respectively, and WD and VTD are the gate width and the threshold voltage of each MO with the same value, respectively. The dependence of the on the ratio of the total gate width of MD to derived A V ~ R B the gate width of M c is shown in Fig. 4, with the parameter of threshold voltage difference between M c and MO. The subthreshold swing is assumed to be 90 mVldecade. When n . WD/WCis large or I VTC 1 is larger than I VTD 1, AVSRB

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TABLE Il FEATURES OF SUBTHRESHOLD CURRENT REDUCTION TECHNIQUE; ASSUMED NUMBERS FOR EXAMPLES: WC = 200 pm, I VTCI = 0.2 V, C = 10 pF, W , = 20 pm, I i . 5 I~ =0.1 V, CO = 2 pF, n = 512, S = 90mV/decade, VC = 2.2 V FcatulCS

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than I VTD1, the effect of the subthreshold current reduction is large (i.e., y is small). The example parameters in the caption of Table I1 give y = 1.5 . However, even if sufficient subthreshold current reduction ratio is obtained, it is no good if the delay time of the DecodedDriver is increased by inserting the switch of MC in series with the MO's. The delay time ratio compared to the conventional scheme is obtained as the ratio of time constant of charging the load CO using the analytical expression shown on the right hand side of Fig. 5. In the conventional scheme, where VCl is directly connected to the VC, the well-known time constant rc is given, where the gmD is the transconductance of MO.

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becomes large because the subthreshold current from the M c becomes small. Using example parameters in the caption of of 254 mV. Table I1 shows the A V ~ R B

In the proposed scheme, the operation is expressed as the combination of three operations shown in Fig. S(a)-(c). These are (a) charging the parasitic capacitance C of common source Vcl by M c from VC (time constant ra), (b) charging the output load CO by MD from charges in C (time constant T b ) , and (c) charging the CO from Vc by the series of M c and MD (time constant rc).Operation (a) and operation (b) are dependent operations, and operation (c) is independent of these operations. Therefore, the total time constant is expressed as

B. Ratio y of Subthreshold Current Reduction to the Conventional Scheme The conventional subthreshold current of IMDT is the sum of the currents of M D in all the drivers, as shown in Table I. In the proposed scheme, the subthreshold current is the IMC of (4). Therefore, the subthreshold current reduction ratio 7 is derived as IMC

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where the gmc is the transconductance of Mc. Therefore, we get the delay time ratio tR as the ratio of time constants:

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In particular, when WC = W D VTC , = VTD, SO y = l / n . The dependence of y on the gate width ratio of n .WD/WCis C~ larger shown in Fig. 5. When n . WD/WCis large, or ~ V T is

Using the example parameters in the caption of Table U, tR is 1.05. The gate width ratio dependence of T R is shown in Fig. 5. When ~ . W D / W is smaller ~ than lo2,the degradation in speed in the proposed scheme is small. Although the gate width ratio

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of WC/WDis an important parameter for operating state, the gate width ratio of n -WD/WCis chosen in this figure to show the subthreshold current reduction ratio, where n . WD/WCis an important parameter as shown in (7). In addition, the speed of the proposed scheme can be improved compared to the conventional scheme in the case of high threshold voltage to reduce subthreshold current to the level of the proposed scheme. For a typical circuit of the Decoded-Driver, simulation results of delay time are shown in Fig. 6. Also shown is the subthreshold current reduction ratio dependence to the gate width ratio of WC/WD.This is an example of applying the proposed scheme to an X-decoder and a static word driver. For a dynamic word driver, since the driver for common drain of word drivers is the example of Decoded-Driver, the subthreshold current reduction scheme can be applied to that driver. In Fig. 6, the parasitic capacitance of the common source is 10 pF and the capacitance at the output of each driver is 2 pF. The delay time is defined from the 50% amplitude of the input signal AX of the X-decoder to the 90% amplitude of the output signal W of the word driver. The delay time is only degraded by 3% with a subthreshold reduction ratio of 1.5 . 10-3.

The temperature dependence of the threshold voltage is expressed [8] as

where Q B is the difference in the Fermi level at the donor concentration of NO and the intrinsic Fermi level, and is the permitivity. The difference in NO needed to get a threshold voltage difference of 0.1 V is about 10%. At such a small difference, the temperature dependences of both Q B ' S are almost the same, and changes in the second term on the righthand side of the (12) needed to vary the NO are small. So the temperature dependences of the threshold voltages in (1 1) are the same. On the other hand, the temperature dependence of S is almost linearly proportional to the temperature [9] and is expressed as

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C . Temperature Dependence of the Subthreshold Current Reduction Ratio The derivative of the subthreshold current reduction ratio by temperature is given by

2

Note that = 0 when I VTO /=I VTC 1. Fig. 7 shows the coefficient of temperature dependence of (14), and the temperature dependence of y itself is also shown. The y at 250 K with the 1 VTC I=) VTD1 +O.lV is 0.9. and the y at 350 K is 2.2. Although y doubles with this 100-K increase, a value of 1 0 - ~ is sufficient for practical use.

dT D . Dynamic Behavior between the Operating State and the low subthreshold current State The second term in the parentheses on the right-hand side is negligible because the temperature dependences of VTCand VTD are almost the same in the practical range of threshold voltage difference.

The above discussions about the subthreshold current reduction ratio were for the steady state. This section discusses the dynamical behaviors of transition from the operating state to the low subthreshold current state and vice versa. Both times

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Fig. 8. Self-reverse biasing voltage evolution.

are small enough to give a sufficient subthreshold reduction ratio and high-speed operation. Since the voltage drop of the common source of VCl de- This equation is solved with the initial condition of VCl(0) = termines the subthreshold current reduction ratio as discussed Vc - A V ~ R B : in Section B, a discussion about the time dependence of V& is necessary to understand the above dynamical behavior. In the transition from the operating state to the low subthreshold current state, the self-reverse biasing voltage evolution at Vc1 The time constant of TR in (19) is expressed as is caused by the difference between the subthreshold current from the M c and that to the MO. We get the following equation, where C is the total parasitic capacitance of node Vc1: When t -+ 00, we get VCl(o0) = VC, which is the ready voltage for operation. The dynamic subthreshold current reduction ratio y (t) is of (16) and (19): also given as follows from the This equation is solved with the initial condition of VCl(0) =

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When t ---t 00, we get Vcl(m) = VC - A V ~ R Bwhich , is the same as at the steady state. On the other hand, the time dependence of recovery from the low subthreshold current state to the operating state is derived on the assumption that the charging up of C is done before the operation of the Decoded-Driver. The following equation is given, where /3 is the gain coefficient of Mc:

Fig. 8 shows the time dependance of AVcl = Vc - Vcl(t) at example parameters with I V - D 1 as a parameter. It takes 1 ms for the AV,, to almost reach the steady state. When the proposed scheme is applied to a DRAM in data-retention mode, one group of word drivers operates every 64 or 128 ms for burst refresh operation. So, the transition time of 1 ms is sufficiently small to reduce the subthreshold current. Note that the current from the VC itself is quickly reduced when the MC tums off. However, if the cycle time is much shorter than the transition time, the reduction of power consumption is small because the discharged charges by large subthreshold current of Decoded-Drivers are supplied at the start of the next cycle. And if the drain voltage dependence would be taken into account, the current from the VC once turns to zero when the MC tums off because the source to drain voltage is zero, and then reaches to the low subthreshold current level. The recovery of AVc1 to the operation state is shown in Fig. 9 with the same conditions as in Fig. 8. Since it takes only 1 ns, the proposed scheme does not interrupt the start of normal operation.

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IV. EXPERIMENTAL RESULTS To evaluate this subthreshold current reduction technique for a Decoded-Driver by self-reverse biasing, a simple test chip was fabricated using 0.25-pm technology (Fig. 10). The total gate width of M D was 163,840 pm, and four sets of gate widths of MC'S were prepared. The measured threshold voltage difference of M D and Mc's was 129 mV f 16 mV, and measured subthreshold swing was 91 mV f 4 mV/decade. vs The n-well voltages were set the same in both kinds of PMOS. (b) The subthreshold current in the conventional scheme was Fig. 10. Test chip. estimated by measuring the IDS-VGS characteristics of MD when all the MC'S were ON (the voltages of GI-G4 were GND). The proposed scheme was estimated by measuring the through a switching MOS transistor insertion. This is the IDSof one or more nodes S1-S4 dependences on the voltages primary issue for reducing the total subthreshold current of applied to Gl-G4 and G, which are the same as the voltages high-density memory LSI aiming at the low voltage, low applied to S 1 4 4 . power, and high speed for use in portable equipment. The The measured dependences subthreshold current reduction subthreshold current of the Decoded-Driver is reduced to ratios dependence to the gate width ratio at n = 512 are shown the order of lop3 in the practical range of temperature in Fig. 11. The values derived from (7) are also shown in the (250-350 K), with small self-reverse biasing voltage of 254 figure, with the threshold voltage difference of 130 mV and the mV, while the delay time is only 3% larger than in the S of 90 mV. Since only one set of threshold voltage difference scheme. The transition time of 1 ns from the (I VTCI - I VTD(= 130 mV) was prepared in the test chip, conventional operating state to the low subthreshold current state is suffithe gate voltage of VGCand VGDare differed to realize other cient to reduce the subthreshold current. The recovery time threshold voltage differences equivalently corresponding to the of 1 ns from the low subthreshold current state does not discussion in Section 111-B.Therefore, VGC = VGD- 0.1 V interrupt the start of normal operation. The dependence of in Fig. 11 is equivalent to 1 VTC I - I VTD (= 0.03 V, the subthreshold current reduction ratio on the gate width of which is 0.1 V smaller than the original threshold voltage difference. Also, VGC = VGD 0.1 V is equivalent to the switching MOS transistor was measured, using the test with 0.25-pm technology, to be on the order of lop3 1 VTC1 - I VTD1 = 0.23 V, which is 0.1 V larger than the chip in the subthreshold current reduction ratio. Good agreement original threshold voltage difference. The measurements show was also obtained between the calculated values and measured a sufficient subthreshold current reduction ratio of lop3 when values. the nWn/Wc is 25.6 and the threshold voltage difference is 130 mV. The measured data agree well with the values derived from (7). ACKNOWLEDGMENT

+

V. CONCLUSION Analytical expressions are presented for subthreshold current reduction in a Decoded-Driver by self-reverse biasing

The authors wish to thank M. Ishihara, K. Kajigaya, T. Matsumoto, R. Hori, K. Shimohigashi, K. Itoh, T. Nishida, J. Etoh, T. Akiba, and T. Sakata for their helpful suggestions. The authors would also like to thank S. Shukuri, K. Sagara,

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T. Kisu. and Y. Yamashita for their support in fabricating the test chip. REFERENCES [I] M. Aoki et al., “A 1.5-V DRAM for battery-based applications,” ISSCC Dig Tech. Papers, pp. 238-239, Feb. 1989. [2] T. Masuhara, J. Etoh, and M. Nagata, “A precise MOSFET model for low-voltage circuits,” IEEE Trans. Electron Devices, vol. ED-2 I , pp. 363-371, June 1974. [3] G. W. Taylor, “Subthreshold conduction in MOSFET’s,” IEEE Trans. Electron Devices, vol. ED-25, pp. 337-350, March 1978. [4] K. Itoh, “Reviews and prospects of deep submicron DRAM technology.’’ in Extended Abstracts of the 1991 Int. Conf. on Solid-State Devices and Materials, pp. 4 6 8 4 7 1, 199 1. [5] F. H. Gaensslen and R. C. Jaeger, “Low temperature microelectronics,” in Ertended Abstracts of the 1990 lnt. Conf. on Solid-state Devices and Materials, pp. 353-356, 1990. [6] P. P. Gelsinger et al., “Microprocessor cira 2000,” IEEE Spectrum, vol. 26, pp. 4 3 4 9 , Oct. 1989. [7] G. Kitsukawa et al., “256 Mb DRAM technologies for file applications,” ISSCC Dig. Tech. Papers, pp. 4 8 4 9 , Feb. 1993. [8] S . M. Sze, Physics of Semiconductor Devices, 2nd ed. New York: Wiley, 1981, Chap. 8. [9] M. Aoki et al., “Performance and hot-camer effects of small CRYO-CMOS devices,” IEEE Trans. Electron Devices, vol. ED-34, pp. 8-18, Jan. 1987.

Takayuki Kawahara (M’91) was bom in Kumamoto, Japan, on June 10, 1960. He received the B.S. and M.S. degrees in physics from Kyusyu University, Fukuoka, Japan, in 1983 and 1985, respectively. In 1985 he joined the Central Research Laboratory, Hitachi Ltd., Tokyo, Japan, where he was engaged in the research of BiCMOS DRAM’s. Currently, his interest is in high-density DRAM development. Mr. Kawahara is a member of the Institute of Electronics, Informatiim, and Communication Engineers of Japan.

Electronics, Informatii

Masashi Horiguchi (M’86) was born in Hyogo, Japan, on March 18, 1955. He received the B.S. degree in electronic engineering and the M.S. degree in information engineering from the University of Tokyo, Tokyo, Japan, in 1977 and 1979, respectively. He joined the Central Research Laboratory, Hitachi Ltd., Tokyo, Japan, in 1979. He has been engaged in the research and development of MOS dynamic memories. Mr. Horiguchi is a member of the Institute of and Communication Engineers of Japan.

Yoshiki Kawajiri was bom in Ishikawa, Japan, on October 10, 1951. He graduated from Ishikawa Technical High School, Ishikawa, Japan, in 1970. From 1970 to 1992 he was engaged in the research and development of MOS memories at the Central Research Laboratory, Hitachi Ltd, Tokyo, Japan. Since 1992 he has been engaged in product marketing at the Semiconductor and Integrated Circuits Division, Hitachi Ltd., Tokyo, Japan. Mr. Kawajiri is a member of the Institute of Electronics, Information, and Communication Engineers of Japan.

Goro Kitsukawa was born in Aichi, Japan, on January 16, 1950. He received the B.S. and Ph.D. degrees in electric engineering from Nagoya University, Nagoya, Japan, in 1972 and 1992, respectively. In 1972 he joined the Central Research Laboratory, Hitachi Ltd., Tokyo, Japan, where he was engaged in the research and development of bipolar RAM’S and logic in memories. Since 1984 he has been engaged in the research and development of BiCMOS and CMOS DRAM’S. Dr. Kitsukawa is a member of the Institute of Electronics, Information, and Communication Engineers of Japan.

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Tokuo Kure (A’91) was bom in Osaka, Japan, on September 18, 1952. He received the B.S. degree in chemistry from Osaka University, Osaka, Japan, in 1975 and the M.S. degree in chemistry from Kyoto University, Kyoto, Japan, in 1977. In 1977 he joined the Central Research Laboratory, Hitachi Ltd., Tokyo, Japan, where he has been engaged in the research and development of dryetching technology. Mr. Kure is a member of the Japan Society of Applied Physics.

Masakazu Aoki (M’76S’81-M’82) received the B.S. degree in applied physics and the Ph.D. degree in electronic engineering from Tokyo University, Tokyo, Japan, in 1971 and 1992, respectively, and the M.S. degree in electrical engineering from the University of Michigan, Ann Arbor, in 1982. Since joining the Central Research Laboratory, Hitachi Ltd., Tokyo, Japan, in 1971, he has been engaged in work on linear and area image sensors as well as CMOS memory circuits and devices. Currently he is working on high-density DRAM development. Dr. Aoki is a member of the Institute of Electronics, Information, and Communication Engineers of Japan.