test bench for dynamic range testing of adc

K.Hariharan et. al. / International Journal of Engineering Science and Technology Vol. 2(12), 2010, 6922-6930

TEST BENCH FOR DYNAMIC RANGE TESTING OF ADC K.HARIHARAN Electronics and Communication Engineering Dept., Thiagarajar College Of Engineering, Madurai-625015 Madurai, Tamil Nadu, India [email protected].

E.BENITTA HUBERT Electronics and Communication Engineering Dept., Thiagarajar College Of Engineering, Madurai-625015 Madurai, Tamil Nadu, India [email protected] K.V.O.DIVYA LAKSHMI Electronics and Communication Engineering Dept., Thiagarajar College Of Engineering, Madurai-625015 Madurai, Tamil Nadu, India [email protected] K.SHAMALLA Electronics and Communication Engineering Dept., Thiagarajar College Of Engineering, Madurai-625015 Madurai, Tamil Nadu, India [email protected]

Dr.V.ABHAI KUMAR Electronics and Communication Engineering Dept., Thiagarajar College Of Engineering, Madurai-625015 Madurai, Tamil Nadu, India Abstract: A built-in self-test (BIST) approach based on a direct digital frequency synthesizer (DDFS) for the dynamic range testing of ADC is proposed. Testing analog components using spectral techniques requires a coherent sinusoidal stimulus. The sinusoidal test stimulus is generated using a direct digital frequency synthesizer, which is based on a new novel approach of using extended Taylor series approximations. The merit of DDFS is that the output frequency can be precisely and rapidly manipulated under digital control. The BIST method aims at full dynamic characterization of an ADC under test (DUT), while maintaining low area overhead. A low complexity DDFS has been proposed in this paper and the design approach for BIST of ADC is discussed. Keywords: Built-In Self Test (BIST); Direct Digital Frequency Synthesis (DDFS); dynamic range. 1. INTRODUCTION A mixed signal systems-on-Chip (SoCs) are generally composed of data converters (Analog to Digital converters and Digital to Analog converters) [Emmert et al, (2003)] for interfacing with the real world. Constant increase of analog circuit density, the nature of analog faults, and the embedding of analog functions within large digital systems, makes on system testing inevitable. Reuse of SoC resources is advantageous and desirable when characterizing the ADC parameters. External sinusoidal source is suitable for more dedicated setups, where high volume testing is required but built-in DDFS is idle for evaluating the ADC performance on the bench. ADC is characterized by its static and dynamic performances. Static characters include offset error, gain error, differential non- linearity (DNL) error and integral non- linearity (INL) error, while the dynamic characters include total harmonic distortion (THD), spurious-free dynamic range (SFDR), signal-to-noise ratio (SNR) and signal-to noise

ISSN: 0975-5462

6922

K.Hariharan et. al. / International Journal of Engineering Science and Technology Vol. 2(12), 2010, 6922-6930 and distortion ratio (SINAD).Dynamic characterization of the ADC is important in the field of communication and embedded systems. These dynamic parameters can be computed from the harmonic values and the noise value. Harmonic and noise values of a given converter can be evaluated from its spectral analysis wherein a single tone sine wave is applied to the converter input and FFT of the output signal is computed. A complete Built-In Self Test procedure that utilizes the SoC inbuilt resources is a good alternative to reduce test costs when compared to external mixed-signal testers. Section 2 deals with the proposed BIST technique. Test pattern is generated using Direct Digital Frequency Synthesizer using extended Taylor Series approximation and is discussed in Section 3. The condition for coherent sampling is briefed in Section 4. Section 5 deals with the pseudo code for the BIST controller. ADC testing methodology is dealt in section 6. 2. PROPOSED BIST TECHNIQUE A back-to back testing methodology is proposed, in which the output of the DAC is fed to the ADC (Device under Test) [Dai et al, (2006)] [Yang et al, (2005)]. The proposed BIST architecture is shown in Fig.1.The architecture consists of a DDFS based test pattern generator (TPG). Input clock (CLK) and the frequency control word (FCW) are controlled by the BIST controller. The test vectors can either be fed into a register manually or it can be generated through the DDFS. The digitized test pattern from DDFS or the DAC register is fed to a DAC through the digital multiplexer. The input to the ADC (DUT) is either the output response from the DAC or the user input (analog input) which is controlled by the analog multiplexer. The ADC is triggered by the Start Conversion signal from the BIST controller. The digital response from the ADC is stored in the memory, whose address pointer is controlled by the BIST controller. 3. TEST PATTERN GENERATION USING EXTENDED TAYLOR SERIES APPROXIMATED DDFS Sine waves are commonly used in ADC testing. Sine wave sources are readily available and it is relatively easier to establish the quality of the sine wave (e.g., with a spectrum analyzer). Sine waves are generated using direct digital frequency synthesizers. In this paper, a new novel method towards the generation of sine waves using DDFS is presented. Taylor series expansion with an approximation algorithm is used to generate the sine waves. The proposed DDFS design provides two improvements over the traditional DDFS while maintaining the performance. First, minimizing the size of the ROM lookup table by using an approximation algorithm, and second, reducing the complexity of the system. The primary objective for using such an approach is that precision can be achieved with relatively less hardware overhead, as compared to other techniques. The spectral purity achieved by this method is 72 dBc. Memory User output

User input

Analog Mux

Digital Mux DAC Register

ADC

DAC Sine Wave Generator

S2 S1

Start conversion

FCW BIST Controller CLK

Memory Pointer

Fig. 1. Proposed BIST architecture

ISSN: 0975-5462

6923

K.Hariharan et. al. / International Journal of Engineering Science and Technology Vol. 2(12), 2010, 6922-6930 Sine function can be implemented based on the following Taylor series approximations, Sin (θ) = Sin (γ) + (θ - γ) * Cos (γ) + . . .

(1)

Cos (θ) = Cos (γ) - (θ - γ) * Sin (γ) + . . .

(2)

Another form of Taylor series expansion for sine and cosine function is, Sin (γ) = γ – ( γ 3 / 3! ) + ( γ 5 / 5! ) – ( γ 7 / 7!) + . . . (3) Cos (γ) = 1 – ( γ 2 / 2! ) + ( γ 4 / 4! ) – ( γ 6 / 6! ) + . . .

(4)

Prior algorithms are based on Eq. (1), Eq. (2) which utilize the sample magnitude of Sin (θ) stored in a ROM and its slope Cos (θ) [Hai et al, (2005)]. Typically, the sine function generation is realized by using a look up table (LUT) provided by a ROM [Vankka, (1997)]. The phase and amplitude quantization errors are determined by the number of words and the number of bits in each word in the ROM respectively. Thus it is desirable to increase the resolution of the ROM for a high spectral purity sine output. This leads to larger ROM size, which means higher power consumption and chip area, low reliability, lower speed and increased costs. The proposed algorithm is aimed to develop DDFS for low power, reduced ROM size and high speed operation using limited hardware. The higher order terms in Eq. (1) and Eq. (2) are neglected thus, Sin (θ) ~ Sin(γ)+(θ - γ)*Cos (γ)

(5)

Cos (θ) ~ Cos(γ)-(θ - γ)*Sin (γ)

(6)

2

For N bits precision, the terms after (1–(γ /2!)) in cos γ expansion and γ in sin γ expansion can be ignored (because they are less than 2-(N+1)). The approximations for sine and cosine functions can be simplified as follows: From Eq. (3) and Eq. (4), it can be inferred [Chih et al, (2001)] that, Sin (γ) ~ γ

(7) 2

Cos (γ) ~ 1 – ( γ / 2! )

(8)

Using Eq. (7) and Eq. (8) in Eq. (5), Sin (θ) ~ γ + (θ - γ) *(1 – (γ 2 / 2!)) = θ – ((γ 2 / 2) * θ) + γ 3 / 2 Neglecting higher order terms, Sin (θ) ~ (1 – (γ 2 / 2)) * θ

(9)

The γ value for sine wave, denoted as γs can be obtained using Eq. (9) as,

γs = √ (2 * (1- (sin θ/ θ)))

(10)

Where θ holds good from 1º to 45º. Similarly, using Eq. (7) and Eq. (8) in Eq. (6), Cos (θ) ~ (1 + (γ * γ / 2)) - (θ * γ)

(11)

The γ value for cosine wave denoted as γc can be obtained using Eq. (11) as, γc 2 -2 (θ* γc ) – 2 (cos θ – 1) = 0

(12)

where θ holds good for 1º to 45º. The minimum of the two roots from Eq. (12) is used for the computation. The most common method of sine compression that reduces the ROM size is to employ sine / cosine symmetry [Linhui et al, (2008)]. The sine/cosine waveform is symmetrical between the range [Π, 2Π] and [0, Π]. Also, the sine waveform from Π /2 to Π /4 is the same as the cosine from zero to Π /4, and the cosine waveform from Π /2 to Π /4

ISSN: 0975-5462

6924

K.Hariharan et. al. / International Journal of Engineering Science and Technology Vol. 2(12), 2010, 6922-6930 is the same as the sine from zero to Π /4. Thus, it is sufficient to compute the sine and cosine values from zero to Π/4 using Eq. (9) and Eq. (11). The entire sine wave is generated from the translations given in Table. 1. Fig.2. shows the proposed architecture of DDFS based on the algorithm described in section 2. The N-bit frequency control word to the accumulator from the system controller determines the phase step and the frequency resolution. Generally, the linearly increasing output of the phase accumulator is used to access the sine amplitude values stored in the look-up table [Essenwanger and Reinhardt, (1998)]. In the proposed architecture, the phase accumulator output is the actual phase value itself. After the phase value reaches 360º, the accumulator content is reset to 0º. The proposed method consists of a simple computational hardware which generates sine wave from 0-45º. The 45º modulo counter detects the number of 45º increments of the phase word. The full cycle is generated by using the symmetry of sine wave [Lin-hui et al, (2008)]. The number of 45º roll over in the counter, a three bit value, is used to map one eighth of the sine wave to full wave i.e., 360º. The three bits decide the quadrant of the given phase value and the data required for mapping (90, 180, 270 or 360) to 45º is obtained from ROM. The mapping with the three bits is done according to Table.1. The LSB of the counter value is used to complement (2’s complement) the phase value, that is, if LSB is 1, the phase angle is complemented (-θ). The sine and cosine amplitude values are computed using the proposed algorithm. The second and third bits are XOR'ed to select sine or cosine function, through MUX. The generation of positive half or negative half of the sine wave is controlled by first bit of the counter value, and it is done using the sign magnitude DAC. 1 – γ2/2 3rd MSB

FCW N bits

Phase Accumulator

1st MSB

X

Mux

Complement

Sign Magnitude DAC

+

θ

0º 90º -90º 180º -180º 270º -270º 360º

45º modulo Counter

X Sin θ output

γ

1 + γ2/2

3

2

3

Fig. 2. Proposed test pattern generation architecture

ISSN: 0975-5462

6925

K.Hariharan et. al. / International Journal of Engineering Science and Technology Vol. 2(12), 2010, 6922-6930 Table 1. Translation of phase values.

Counter value (bits)

Phase

Phase word (θ) degrees

word mapped to

1

2

3

0

0

0

0≤θ≤45

θ

0

0

1

45