proposed by Seshadri and Hsiao (26). Rule 2: Use "Case" statements with explicitly enumerated choices rather than nested "if - then - else" statements with a.
Effect of RTL Coding Style On Testability* Yu Huang'
Chien-Chung Tsai2 Nilanjan Mukherjee'
Wu-Tung Cheng2
Sudhakar M. Reddy
'
' Department of Electrical & Computer Engineering, University of Iowa, Iowa City, IA 52242 2Mentor Graphics Corporation, 8005 S.W. Boeckman Rd., Wilsonville, OR 97070 Abstract This paper illustrates the effect of functional Register Transfer - Level (RTL) coding styles on the testability of synthesized gate-level circuits. Thus, the advantage of having a RTL code analyzer to reduce the number of untestable faults, thereby improving the overall testability of a design is presented. In addition, it has been also observed that writing efficient RTL code to improve testability reduces the total silicon area of the gate-level circuit as well. Experimental results presented in this paper demonstrate the benefits of having a proposed RTL code analyzer.
I. Introduction With the rapidly increasing complexity of VLSICs, designfor-test is becoming an important consideration much earlier in the design process. This is unlike the conventional practice where circuit modifications for manufacturing test are done at a later stage in the design, when any change may actually prove to be very expensive. Logic redundancy is one of the major factors that degrade the testability of a design. The problems associated with redundant logic are as follows
(1,2,3). (I) It may invalidate some tests for non-redundant faults. (11) It may degrade fault coverage to unacceptable levels. (111) Large amount of test generation time can be spent in trying to generate tests for redundant faults. (IV) Additional delay may be introduced in signal propagation paths that degrades the performance of the design. (V) It may result in a significant increase in gate count, which leads to wasted silicon area.
Due to the above reasons, redundancy identification and removal have constantly been a very important step in testing and logic synthesis. These studies can be classified into two categories: combinational redundancy removal (1 1-21) and sequential redundancy removal (4-1 1). In this paper we only consider combinational redundancy because we target mostly full scan designs that have become the most pervasive DlT technique in the micro-electronics industry today. To the best of our knowledge, all the existing redundancy removal methods (4-21) are performed at the gate-level circuit. Two problem arise in this scenario:
* This work is supported through
(I) Logic redundancies are sometimes deliberately introduced into the design in order to improve its performance, such as timing closure (e.g. elimination of hazards) and fault tolerance (e.g. Triple Modular Redundant (TMR) systems). Therefore, redundancy removal at the gatelevel could jeopardize the intended functionality of the original circuit. (11) Most of the combinational redundancy identification methods (11-18) resort to ATPG, which is a NP-complete problem (22). Hendricx and Claesen (19) proposed a redundancy identification methodology based on formal verification. However, for some circuits, the computational complexity of this method suffers from an exponential explosion in the size of the BDD-representations. Tsai and M.-Sadowska (20) proposed a method to identify redundancy by using a pre-determined set of input patterns which are generated by the methods proposed by Reddy (23) and Saluja (24). However, the Reed-Muller canonical forms may not be applied to practical designs because the silicon area of an XOR gate can not be made as small as an AND (OR) gate yet. A method to identify redundant faults without using ATPG was proposed in (21). This method identifies only a subset of redundant faults. Given the factors that mandate some redundancy in a design, commercial synthesis tools usually don't remove all the combinational redundancies. This, in effect, leads to a design for which a high fault coverage can not be guaranteed. In this paper we analyze the relationship between RT-Level coding styles and the redundancies in the corresponding postsynthesized gate-level circuit. Some guidelines for RTL coding are presented in order to reduce the number of untestable faults in the gate-level circuits. The primary intention is not to eliminate all combinational redundancies at the RT-Level, but reduce them so that the burden of redundancy identification and removal at the gate-level is significantly reduced. The advantages of the method are as follows. (I) The redundancies targeted at the RT-level are not the ones that are intentionally introduced by designers. Moreover, redundancies introduced during synthesis to improve design performance are not affected as well.
a research grant from Mentor Graphics Corporation.
12-2-1 0-7803-6591-7/01/$10.00 0 2001 IEEE
IEEE 2001 CUSTOM INTEGRATED CIRCUITS CONFERENCE
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The search space for the solution at RTL is much smaller than at the gate-level, thereby preventing exponential increase in identifying redundancies. (111) The synthesis tool can synthesize the improved RTL code under desired area and performance constraints to generate a gate-level circuit that meets the goals of higher performance and reduced silicon area. (11)
The paper is organized in the following manner. First, a set of rules for RTL coding is given, and the relationship between RTL coding style and the quality of the corresponding synthesized gate-level circuit is illustrated through several examples. Finally, experimental results are presented, followed by the conclusion section. 11. Guidelines for RTL Coding to improve Testability Although there are many advantages of reducing redundancy at RTL as described in Section 1 , there is no well-known published research on this topic. It is traditionally believed that redundancy is always structure dependent, and redundancy removal has to be accomplished at the gate-level. However, as pointed in (25), based on statistical data, the testability of a gate-level circuit is strongly correlated to its architectural description at the RT-Level, and therefore, area and performance driven logic optimizations do not significantly impact it. In other words, as long as the RTL code follows certain testability related coding styles, the testability of synthesized gate-level circuits can be improved without being limited by the synthesis tool used and / or constraints desired.
We have developed a rule-based coding style at the functional RT-Level to improve overall testability of the circuit. In this section, we illustrate some of these rules through examples. Note, in this paper we have used VHDL to illustrate the concepts, but the concepts are equally applicable to Verilog code as well.
w: Declare the value range of a signal or variable as needed. Otherwise, it may introduce redundancy. The application of this rule is illustrated in Example 1 below. Examole 1:Declarationof Inaooromiate Value Ranee entity example is port( reset: in bit; output : out bit; clock : in bit ); end example; architecture BEHAV of example is begin process(clock,reset) variable number: integer n n g e 255 downto 0; begin if reset=:l' then number:=O; output 10 then number := number mod 16; output 9 then number := number - 10; else number := 3 1 - number; end if; if number > 27 then output 23 then output number := number - 20; 19 =>number := number - 10; 9 =>number := 31 -number; end case; case number is when 28 29 30 31=>outputoutputoutputoutput10000), we can use a “for” loop c o n s t r u c t as follows. for 1 in 1 to n loop if number = i then ; end if; end loop;
exit;
Note that a single level “if-then” with an equality operator is identical to a “Case” statement. As a by-product, the circuit becomes faster because parallel comparisons are much faster than priority encoders (27). Consequently, the HDL simulation also speeds up significantly (28).
Rule:Initialize memory elements Example 3 illustrates Rule 3. F
. P. . .
S
After synthesizing the above RTL netlist for a ROM reader, a gate-level circuit with a total area of 1804.88 units is obtained, and the fault coverage is 98.24%. There are 15 ATPG untestable faults in the circuit. In contrast, if we initialize the “ADDR’to a fixed number (e.g. to 0) when the circuit is reset, a gate-level circuit with total area of 1745.73 units is obtained, which has 100% fault coverage. This example clearly shows the necessity of memory initialization statements in a RTL description of a circuit.
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zntity example is CI.OCK: in hit; RESET: in bit; port( OUTPUT: out integer range 255 downto -256); and example; architecture BEHAV of example is type rom is array (0 to 3 I ) of integer range 255 downto -256; --32 arbitraiy 9-bit integers. constant MEM: rom := (. . . . . .); begin process (CLOCK,RESET) variable ADDR: integer rangc 3 1 downto 0; if RESET = ‘1’ then OUTPUT
