Custom Integrated Circuits Conference (CICC), one of the leading international conferences in the field of integrated circuit development, which was held in San ...
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 56, NO. 8, AUGUST 2009
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Guest Editorial Special Section on 2008 IEEE Custom Integrated Circuits Conference
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ELCOME to this Special Section in IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS (TCAS-I). This section comprises a collection of selected papers presented at the 2008 IEEE Custom Integrated Circuits Conference (CICC), one of the leading international conferences in the field of integrated circuit development, which was held in San Jose, CA, from September 21–24, 2008. CICC is sponsored by IEEE Solid-State Circuits Society (SSCS), and each year the IEEE JOURNAL OF SOLID-STATE CIRCUITS (JSSC) devotes a special issue to the Selected Papers from CICC. The goal of this Special Section in IEEE TCAS-I is to enhance the cross-fertilisation between the two communities, namely the IEEE Circuits and Systems Society (CASS) and IEEE Solid-State Circuits Society (SSCS). We would like to thank Professor Bram Nauta and Professor Gianluca Setti, the Editors-in-Chief of JSSC and TCAS-I, respectively, for their involvement in the genesis of this initiative as well as their support of the idea. Professors Lawrence Clark, Payam Heydari, and Anthony Chan Carusone (Guest Editors for the IEEE JSSC Special Issue on CICC) have also been of great help. Particularly in coordination with Tony, we have selected and invited papers that are distinct from and complement those that were invited to JSSC and have targeted the papers that are more focused on system level, innovative design methodologies, modeling, and/or forward-looking ideas. For this Special Section, we have selected nine papers. In the first paper, entitled “The Role of PLLs in Future Wireline Transmitters,” Behzad Razavi discusses phase-locking issues in emerging high-speed wireline transmitters and proposes circuit and architecture techniques as well as new ideas to alleviate these issues. The second paper, “A 32/16 Gb/s Dual-Mode Pulsewidth Modulation Pre-Emphasis (PWM-PE) Transmitter With 30-dB Loss Compensation Using a High-Speed CML Design Methodology,” by Cheng et al. presents a design methodology that combines relatively large logic swings and incomplete switching of the tail current in current-mode logic (CML) circuits to achieve very high-speed operation in PWM-PE transmitters. Furthermore, in addition to binary mode transmission, the relatively new PWM-PE technique is extended to 4-PAM (pulse-amplitude modulation) systems. In the third paper, entitled, “A 9 Gb/s Serial Transceiver for On-Chip Global Signaling over Lossy Transmission Lines,” Park et al. describe techniques for global serial signalling over lossy on-chip transmission lines, as an alternative way to the
Digital Object Identifier 10.1109/TCSI.2009.2029653
use of global parallel buses with repeaters. Based on these techniques a 9Gbit/s serial link transceiver for on-chip global signaling is presented. The technique of injection locking has recently gained substantial attention in CMOS communication circuits. The fourth paper, “Strong Injection Locking in Low-Q LC Oscillators: Modeling and Applications in a Forwarded-Clock I/O Receiver,” Shekhar et al. present a general model for injection-locked LC oscillators (LC-ILOs) that is valid for any tank quality factor and injection strength. Based on the presented model, an LC-ILO together with a half-rate data sampler is successfully implemented as a forwarded-clock I/O receiver in 45 nm CMOS. Wideband voltage-controlled oscillators (VCOs) enable low-cost low-power multi-standard, multi-band multi-function, and emerging software-defined wireless systems. In the fifth paper, entitled “Wideband Multi-Mode CMOS VCO Design Using Coupled Inductors,” Safarian and Hashemi use coupled inductors in a multi-mode VCO to enable frequency generation over a wide range in a small chip area. They also discuss design guidelines for optimizing the performance while maintaining a low power consumption throughout the entire tuning range. Clocked comparators have found widespread use in noise-sensitive applications including analog-to-digital converters, wireline receivers, and memory bit-line detectors. However, their nonlinear time-varying dynamics have discouraged the use of traditional linear time-invariant (LTI) small-signal analysis and noise simulation techniques. In the sixth paper, “Simulation and Analysis of Random Decision Errors in Clocked Comparators,” by Kim et al., a linear time-varying (LTV) model of clock comparators is presented that can accurately predict the decision error probability without resorting to more general stochastic system models. The presented LTV analysis framework together with the linear periodically time-varying (LPTV) simulation algorithms available from RF circuit simulators provide insights into the intrinsic sampling and decision operations of such comparators. The next two papers focus on device modeling techniques. Multiple-gate (MG) MOSFETs have been regarded as a leading candidate to extend the scaling limit of conventional bulk MOSFETs to 10-nm gate length and beyond, due to their excellent control over the short-channel effects and high current driving ability. In the paper, “A Review on Compact Modeling of Multiple-Gate MOSFETs,” Song et al. review recent developments in compact modeling of MG MOSFETs, present detailed description of an important core model of such devices, and extend the core model to various MG structures. Aggressive semiconductor scaling has reduced the susceptibility of most deep-submicron CMOS technologies to ionizing
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 56, NO. 8, AUGUST 2009
radiation damage. In the next paper, “Modeling Ionizing Radiation Effects in Solid State Materials and CMOS Devices,” Barnaby et al. present a general analytical model for ionizing radiation damage in semiconductor materials. They also demonstrate how these models can be used to simulate the radiation response of bulk CMOS devices and parasitic structures in ICs as well as support the optimal implementation of radiation-hardening-by-design approaches. The last paper of this Special Section focuses on future trends in lithography for chip fabrication. In 2008, three major technological lithography options have been considered for high volume manufacturing at the 32-nm half-pitch node. In the last paper, “Lithography Options for the 32 nm Half Pitch Node and beyond,” Ronse et al. discuss the evolution of these three options. Several important issues regarding extendibility of these options beyond 32-nm half pitch are also discussed. We are confident that this Special Section of TCAS-I will be highly appreciated by our readership and hopefully the special section will become a tradition both for CICC and for our journal. We would like to sincerely thank all the authors for their contributions and all our dedicated reviewers for their prompt and
thorough technical comments which ensured timely publication of these high-quality manuscripts. Happy reading!
SHAHRIAR MIRABBASI, Guest Editor Department of Electrical and Computer Engineering University of British Columbia Vancouver, BC V6T 1Z4 Canada GENNADY GILDENBLAT, Guest Editor Department of Electrical Engineering, Ira A. Fulton School of Engineering Arizona State University Tempe, AZ 85287 WOUTER SERDIJN, Guest Editor Department of Microelectronics Delft University of Technology Delft, 2600 AA The Netherlands
Shahriar Mirabbasi (M’02) received the B.Sc. degree in electrical engineering from Sharif University of Technology, Tehran, Iran, in 1990, and the M.A.Sc. and Ph.D. degrees in electrical and computer engineering from the University of Toronto, Toronto, ON, Canada, in 1997 and 2002, respectively. Since August 2002, he has been with the Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada where he is currently an Associate Professor. His current research interests include analog, mixed-signal, and RF integrated circuit and system design for wireless and wireline data communications applications, low-power integrated transceivers, mm-wave circuits, data converters, and biomedical circuits. In 2008, he was a visiting researcher at the Swiss Federal Institute of Technology (ETH) Zurich, Switzerland, and subsequently, in 2009 at the Laboratoire d’Intégration du Matériau au Système (IMS Lab) in Bordeaux, France. Dr. Mirabbasi is a member of Analog Signal Processing Technical Committee of the IEEE Circuits and Systems Society and also serves on Technical Program Committee of several conferences, including ISCAS and CICC. He is currently an Associate Editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS.
Gennady Gildenblat (M’83–SM’87) received the M.S.E.E. (with hons.) from the St. Petersburg Electrical Engineering Institute, St. Petersburg, U.S.S.R., in 1975, and the Ph.D. degree in solidstate physics from the Rensselaer Polytechnic Institute, Troy, NY, in 1984. Presently, he is Motorola Professor of Electrical Engineering at the Arizona State University, Tempe. His research interests include semiconductor device physics, transport theory and compact modeling. He has over 150 publications in these fields, including several books, invited papers and US patents. His PSP model of MOS transistors (joint development with Philips and NXP) has been selected as a new industry standard by the Compact Model Council after receiving the first prize in the international competition for the next generation of compact MOSFET models. The MOSVAR compact model of MOS varactor developed by Dr. Gildenblat’s group in collaboration with Jazz semiconductor, Sentinel, and Freescale Semiconductor is another industry standard. Dr. Gildenblat is recipient of the 2006 Semiconductor Research Corporation Technical Excellence Award. He served on the technical program committees of IEDM and CICC.
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Wouter Serdijn (M’98–SM’08) was born in Zoetermeer (’Sweet Lake City’), the Netherlands, in 1966. He received the M.Sc. (cum laude) and Ph.D. degrees from Delft University of Technology, Delft, the Netherlands, in 1989 and 1994, respectively. His research interests include low-voltage, ultra-low-power and ultra wideband analog integrated circuits for wireless communications, pacemakers, cochlear implants, portable, wearable, implantable and injectable ExG recorders and neurostimulators. He teaches analog electronics, analog signal processing, micropower analog IC design and electronic design techniques.He is co-editor and co-author of the books: Ultra Low-Power Biomedical Signal Processing: An Analog Wavelet Filter Approach for Pacemakers (Springer, 2009), Circuits and Systems for Future Generations of Wireless Communications (Springer, 2009), Power Aware Architecting for Data Dominated Applications (Springer, 2007), Adaptive Low-Power Circuits for Wireless Communications (Springer, 2006), Research Perspectives on Dynamic Translinear and Log-Domain Circuits (Kluwer, 2000), Dynamic Translinear and Log-Domain Circuits (Kluwer, 1998) and Low-Voltage Low-Power Analog Integrated Circuits (Kluwer, 1995). He authored and co-authored 6 book chapters and more than 200 publications and presentations. Dr. Serdijn received the Electrical Engineering Best Teacher Award in 2001 and 2004. He has served as an Associate Editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS (2004–2005) and the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS (2002–2003 and 2006–2007), as tutorial session co-chair for ISCAS 2003, as Analog Signal Processing Track Co-Chair for ISCAS 2004 and ISCAS 2005, as chair of the Analog Signal Processing Technical Committee of the IEEE Circuits and Systems society, as Analog Signal Processing Track Chair for ICECS 2004, as Technical Program Committee member for the 2004 International Workshop on Biomedical Circuits and Systems, as International Program Committee member for IASTED CSS 2005 and CSS 2006, as Technical Program Committee member for APCCAS 2006, as Technical Program Committee member for the IEEE Biomedical Circuits and Systems Conference (BioCAS 2006, BioCAS 2007 and BioCAS 2008), as Special-Session Chair for ISCAS 2007, as International Program Committee member of the 2009 International Conference on Biomedical Electronics and Devices, as Special Session Chair for ISCAS 2009, as a member of the CAS Long Term Strategy Committee and currently serves as a member of the Board of Governors (BoG) of the IEEE Circuits and Systems Society (2nd term), a member of the Conference Division of the CAS BoG, a member of the CAS-S Board of Governors Nominations Committee, as Deputy Editor in Chief for IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, Special Session Chair for ICECS 2009 and Technical Program Committee member for ICUWB 2009 and as Technical Program Chair for ISCAS 2010.
