tion of selected papers presented at the 2009 IEEE Custom. Integrated ... development, which was held in San Jose, CA, September .... for WLAN applications.
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Guest Editorial Special Section on 2009 IEEE Custom Integrated Circuits Conference
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ELCOME to this Special Section in IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS (TCAS-I). This section comprises a collection of selected papers presented at the 2009 IEEE Custom Integrated Circuits Conference (CICC), one of the leading international conferences in the field of integrated circuit development, which was held in San Jose, CA, September 13–16, 2009. CICC is sponsored by IEEE Solid-State Circuits Society (SSCS), and each year the IEEE JOURNAL OF SOLID-STATE CIRCUITS (JSSC) devotes a Special Issue to selected papers from CICC. The goal of this Special Section in IEEE TCAS-I is to enhance the cross-fertilization between the two communities, namely the IEEE Circuits and Systems Society (CASS) and IEEE Solid-State Circuits Society (SSCS). We would like to thank Professor Bram Nauta and Professor Gianluca Setti, the former Editors-in-Chief of JSSC and TCAS-I, respectively, for their involvement in the genesis of this initiative as well as Professor Un-Ku Moon and Professor Wouter Serdijn, the current Editors-in-Chief of JSSC and TCAS-I, for their continued support of the idea. Professors Anthony Chan Carusone, Pavan Kumar Hanumolu, and Ramesh Harjani (Guest Editors for the IEEE JSSC Special Issue on CICC) have also been of great help. Particularly in coordination with them, we have selected and invited papers that are distinct from and complement those that were invited to JSSC and have targeted papers that are more focused on system level, innovative design methodologies, architectures, modeling, and/or forward-looking ideas. For this Special Section, we have selected six papers. The first paper, entitled “ADC-Based Serial I/O Receivers,” by Chen et al., discusses the main building blocks of digital receivers that are emerging as a possible solution for next generation wireline receivers in advanced CMOS technologies. More specifically, various designs and architectures for each component of ADCbased receiver and their performance trade-offs are presented. The second paper, “Insights into Wideband Fractional ADPLLs: Modeling and Calibration of Nonlinearity Induced Fractional Spurs,” by Weltin-Wu et al., presents an overview of all-digital PLL architectures, particularly those that use temporal versus voltage encoding of analog signals, and then focuses on the design of a 3 GHz synthesizer that implements a state-of-the-art spurious tone reduction technique. In the third paper, entitled, “47% Power Reduction and 91% Area Reduction in Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking,” Saito et al. describe power and area reduction techniques for 3D integration of NANDbased flash memory. Inductive coupling is used for wireless data and command signal transfer among the stacked chips. Digital Object Identifier 10.1109/TCSI.2010.2071410
Advances in ultralow-power electronics have made it possible to develop lighter weight and lower cost biomedical devices that are ideal for long-term medical measurements and home-based telemonitoring services. In the fourth paper, “Ultralow-Power Electronics for Cardiac Monitoring,” Turicchia et al. present several methods for reducing power consumption in cardiac monitoring systems while retaining the required precision. In particular, they describe a micropower electrocardiograph, an ultralow-power pulse oximeter, an ultralow-power phonocardiograph, an integrated-circuit switched-capacitor model of the heart, and an ultracompact and efficient lithium-ion battery charger. The fifth paper, entitled “A Passive UHF RFID Demodulator with RF Over-Voltage Protection and Automatic Weighted Threshold Adjustment,” by Balachandran and Barnett, presents the design techniques used in a passive RFID that operates over a wide range of input RF power. In this design, the demodulator automatically adjusts between high sensitivity mode for weak RF signal power and overvoltage protection mode for high RF power. As semiconductor technology advances, scaling effects adversely impact ESD protection performance in high-speed circuits. The last paper of this special section, entitled “ESD Design Strategies for High-speed Digital and RF Circuits in Deeply-scaled Silicon Technologies,” by Cao et al., addresses the challenges of ESD protection in deeply scaled silicon technologies. Techniques for improving design, characterization, and modeling of I/O MOSFETs, interconnect, ESD protection and power clamping devices are discussed and recent progress on ESD protection design for both high-speed digital I/O and RF circuits are presented. We are confident that this Special Section of TCAS-I will be highly appreciated by our readership. We would like to sincerely thank all the authors for their contributions and all our dedicated reviewers for their prompt and thorough technical comments which ensured timely publication of these high-quality manuscripts. Happy reading! SHAHRIAR MIRABBASI, Guest Editor Department of Electrical and Computer Engineering University of British Columbia Vancouver, BC V6T 1Z4 Canada JOHN W. M. ROGERS, Guest Editor Faculty of Engineering Carleton University Ottawa, ONCanada GABRIELE MANGANARO, Guest Editor Analog Devices Wilmington, MA USA
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Shahriar Mirabbasi (M02) received the B.Sc. degree in electrical engineering from Sharif University of Technology, Tehran, Iran, in 1990, and the M.A.Sc. and Ph.D. degrees in electrical and computer engineering from the University of Toronto, Toronto, ON, Canada, in 1997 and 2002, respectively. Since August 2002, he has been with the Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, Canada where he is currently an Associate Professor. His research interests include analog, mixed-signal, and RF integrated circuit and system design for wireless and wireline data communications applications, low-power integrated transceivers, mm-wave circuits, data converters, and biomedical circuits. In 2008, he was a visiting researcher at the Swiss Federal Institute of Technology (ETH) Zurich, and subsequently in 2009 at the Laboratoire d’Intégration du Matériau au Système (IMS Lab) in Bordeaux, France. Dr. Mirabbasi is a member of the Analog Signal Processing Technical Committee of the IEEE Circuits and Systems Society and also serves on the Technical Program Committee of several conferences, including ISCAS and CICC. He is currently an Associate Editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS.
John W. M. Rogers (M’95-SM’07) received the Ph.D. degree in electrical engineering from Carleton University, Ottawa, ON, Canada, in 2002. Concurrent with his Ph.D. research he worked as part of a design team with SiGe Semiconductor that developed a cable modem IC for the DOCSIS standard. From 2002 to 2004 he collaborated with Cognio Canada Ltd. doing research on MIMO RFICs for WLAN applications. Since 2002 he has been a Member of the Faculty of Engineering at Carleton University, where he is now an Associate Professor. From 2007–2008 he was on sabbatical and working with Alereon Inc. developing ICs for UWB applications. He is the coauthor of Radio Frequency Integrated Circuit Design 2nd Ed. (Artech House, 2010) and Integrated Circuit Design for High Speed Frequency Synthesis (Artech House, 2006). He holds five U.S. patents. His research interests are in the areas of RFIC and mixed-signal design for wireless applications. Dr. Rogers was the recipient of an IBM faculty partnership award in 2004, and an IEEE SolidState Circuits Predoctoral Fellowship in 2002. He is a Member of the Professional Engineers of Ontario. He has been serving as a member of the technical program committee for the Custom Integrated Circuits Conference since 2006 and the BiCMOS Circuits and Technology Meeting since 2008.
Gabriele Manganaro (S’95–M’99–SM’03) received the Dr.Eng. degree (M.Sc.) in electronic engineering (with full marks) and the Ph.D. degree in electrical engineering from the University of Catania, Italy, in 1994 and 1998, respectively. From 1994 to 1996 he was involved in a joint research program on arrays of nonlinear circuits between the University of Catania and ST Microelectronics, Catania, Italy. From 1996 to 1997 he was a Research Associate and a Lecturer at the Electrical Engineering Department, Texas A&M University, College Station. From 1998 to 2001, he was a Member of the Technical Staff at Texas Instruments Incorporated, Dallas, TX, in the Data Converter Design Dept. From 2001 to early 2004 he was with Engim Inc., Acton, MA, as Director of Analog Baseband Design. In 2004 he joined National Semiconductor, holding various positions including Design Center Manager for the Salem, NH, design center and the Munich, Germany, design center and as Design Director for the High Speed Data Conversion Business Unit. In 2010 he joined Analog Devices, Wilmington, MA, as Engineering Director in the High Speed Data Conversion Product Line. He is author/coauthor of 55 scientific papers in international journals and conferences. He has been granted 12 U.S. patents, 2 European patents, and 1 Japanese patent. He is coauthor of the book Cellular Neural Networks (Springer, 1999) based on his doctoral dissertation. His research and professional interests are in the area of high-performance analog integrated circuits design, in particular data converter and phase-locked loop design, and on the theory, design, and application of nonlinear electronic circuits and systems. Dr. Manganaro is a Fellow of the Institution of Engineering and Technology (formerly IEE), U.K., and a Full Member of Sigma Xi, MIT Chapter. From 1999 to 2001 he served as program chairman and as general chairman for the Dallas chapter of the IEEE Circuits and Systems Society. Over the years he has served in the technical and organizational committees of several IEEE international conferences and has given invited lectures in Italy, U.K., and the United States. Since 2005 he is a member of the
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Data Conversion Subcommittee for the IEEE Solid-State Circuit Conference (ISSCC). He served as Associate Editor for IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART II: EXPRESS BRIEFS from 2006 until 2007 and as Associated Editor for IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART I: REGULAR PAPERS from 2008 until 2009. Since 2010 he has served as Deputy Editor in Chief for IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART I: REGULAR PAPERS. He is also a Guest Editor for the special issues on CICC 2009 and 2009 SoCs technologies on IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART I: REGULAR PAPERS and a Guest Editor for the special issue on ISCAS 2010 to appear in 2011 in the same journal. He was the recipient of the 1994 S. G. S. Thomson (now ST Microelectronics) M.Sc. graduation award, the 1995 CEU Award from the Rutherford Appleton Laboratory (U.K.), the 1999 IEEE Circuits and Systems Outstanding Young Author Award, and the 2000 IEEE Dallas Section Outstanding Service Award and corecipient of the 2007 ESSCIRC best paper award.
