Equivalent Circuit Modeling of Multilayered Power/Ground Planes for Fast Transient Simulation Takayuki WATANABE
Hideki ASAI
School of Administration and Informatics, University of Shizuoka, Shizuoka, Japan
[email protected]
Dept. of System Engineering, Faculty of Engineering, Shizuoka University, Hamamatsu, Japan
[email protected]
Abstract—This paper presents a modeling method for power distribution networks (PDNs) consisting of multilayered power/ground planes of the PCB/Package. Using our proposed method, multiple stacked power/ground plane pairs having holes and apertures can be modeled as an equivalent circuit. The structure of this equivalent circuit is suitable for the Latency Insertion Method (LIM), which is one of the fast transient simulation methods based on the "leapfrog" algorithm. Numerical results show that the leapfrog algorithm enables a speed-up of 105 and 486 times compared to the linear circuit simulator based on the sparse LU-decomposition and HSPICE, respectively, with the same level of accuracy. Keywords-component; power network; leapfrog algorithm; spice
I.
integrity;
power
distribution
INTRODUCTION
In recent years, the power integrity becomes one of the most important problems in the design of high-speed mixed analog and digital circuits. For the verification of power integrity, power distribution networks (PDNs) have to be analyzed in order to estimate unwanted noises, such as ground bounce, delta-I noise, and simultaneous switching noise (SSN). Usually, PDNs of the PCB/Package are designed using multilayered power/ground (P/G) plane pairs. Detailed analysis of the PDN using full-wave electromagnetic simulators provides accurate results. However it takes enormous CPU time and huge memory capacity. In the case of the PCB/Package, the PDN can be modeled as two-dimensional P/G planes in many cases. As is well known, a single P/G plane pair can be discretized spatially into the unit cell models as shown in Fig. 1. Each RLGC parameter of the equivalent circuit of the unit cell is derived by dimensions and medium coefficients [1]. Therefore, instead of full-wave simulators, if a P/G plane pair is modeled as a large number of lumped RLC elements, the conventional circuit simulator, such as the SPICE, is available. However, it is still difficult to analyze them using the SPICE, because of the largescale of the PDN circuit.
978-3-9810801-6-2/DATE10 © 2010 EDAA
M N
Power Ground w d t w
Fig. 1 The unit cell model. On the other hand, the Latency Insertion Method (LIM) is one of the fast transient simulation methods based on the "leapfrog" algorithm [2][3]. In the LIM simulation, the node voltage vector and the branch current vector are computed alternately. It can analyze large-scale RLC circuits very efficiently with much lower calculation cost of solving simultaneous equations in contrast to the implicit numerical integration used in SPICE-like simulators. In [4][5], authors showed that the leapfrog algorithm is suitable for the simulation of the PDN equivalent circuit consisting of the unit cell models with some frequency-dependent dispersions, such as skin effects and dielectric losses. As mentioned above, a single P/G plane pair can be modeled by the unit cell models. However actual PDNs consist of multiple stacked P/G plane pairs which usually have many holes and apertures. Because there are electromagnetic coupling in the vertical direction between two plane pairs through the holes, the unit cell model cannot be simply applied to model actual PDNs. To overcome this problem, the multilayered finite difference method (M-FDM) has been proposed in [6][7]. The M-FDM can model complex plane pairs having holes and apertures as largescale RLC circuits. While these circuits can be solved by the SPICE in time-domain, the computational speed is slow. Additionally, it is difficult for the leapfrog algorithm to solve equivalent circuits produced by the M-FDM, because the leapfrog algorithm has a limitation of the circuit structure to be analyzed. That is to say, every branch must have an inductor and every node must be connected with the grounded capacitor. The equivalent circuits produced by the M-FDM do not meet the LIM conditions.
In this paper, we propose an effective modeling method for power distribution networks (PDNs) consisting of multilayered P/G plane pairs having holes and apertures. In our method, each independent plane pair coupled in a vertical direction is modeled as the lumped RLC equivalent circuit consisting of the unit cell models. At the boundaries of holes or apertures, separatelymodeled circuits are connected by the voltage-controlled voltagesource (VCVS) and the current-controlled current-source (CCCS) according to the relation of electric-fields and magnetic-fields. As a result, the overall equivalent circuit produced by our method can be solved by the leapfrog algorithm without any difficulty. Moreover, the equivalent circuits produced by our method can be solved much faster than ones produced by the M-FDM even using the SPICE. II.
Δt ≤ LC .
⎛i −i van+1 / 2 − vbn+1 / 2 = L⎜⎜ ⎝ Δt n +1 ab
n ab
⎞ n n +1 / 2 , ⎟⎟ + Riab − eab ⎠
Δt n+1 / 2 n n +1 / 2 . va − vbn+1 / 2 − Riab + eab L
(
(1)
)
(2)
Next, each node has a parallel combination of a capacitor, a conductance and a current source to the ground as shown in Fig. 2 (b). Then, the KCL leads to Ma ⎛ v n+1 / 2 − van−1 / 2 ⎞ ⎟⎟ + Gvan+1 / 2 − han = −∑ iakn , C ⎜⎜ a Δt k =1 ⎝ ⎠
(3)
where Ma is the number of branches connected to the node a. Then, the node voltage is updated as Ma C n−1 / 2 va + han − ∑ iakn Δt k =1 . = C +G Δt
(b)
Fig. 2 Branch and node in LIM. (a): branch. (b): node. G
where the superscript n indicates the time index. Then, the branch current is updated, as in n +1 n iab = iab +
(5)
(a)
LATENCY INSERTION METHOD
In this section, we briefly introduce the LIM, which is one of fast transient circuit simulation methods based on the leapfrog algorithm [2][3]. In [4][5], we have already showed that the LIM is suitable for the simulation of the PDN equivalent circuit consisting of the unit cell models. The circuit to be analyzed by LIM requires that each branch has an inductor and each node has a grounded capacitor. For the branch which consists of a series of an inductor, a resistor and a voltage source as shown in Fig. 2(a), the KVL equation is obtained by
van+1 / 2
minimum values of inductance and capacitance in the circuit as follows,
Pair1 P
z
Pair2 G
y
x
Fig. 3 Cross-sectional view of multilayered plane pairs and its models. III.
MULTILAYERED FINITE DIFFERENCE METHOD
Assuming that multiple P/G plane pairs are stacked, each P/G plane pair can be separately modeled as the equivalent circuit consisting of the unit cell models if there are not holes and apertures between plane pairs as shown in Fig. 3. This is because a current in the high-frequency only flows on the surface of conductors due to the skin-effect. On the other hand, actual multilayered P/G plane pairs usually have many holes and apertures. Because there are electromagnetic coupling in the vertical direction between two plane pairs through the holes, the unit cell model cannot be simply applied to model actual PDNs. To overcome this problem, the multilayered finite difference method (M-FDM) has been proposed in [6][7]. At the beginning of this section, we briefly introduce the MFDM. Next, we point out that the M-FDM has room for improvement in the modeling of the conductor loss. R1 C1
plane2
(4)
Finally, the transient simulation is done by the alternate "leapfrog" updates of branch-currents and node-voltages according to (2) and (4) at alternate half-timesteps. To simulate stably, the size of timestep Δt is determined based on the
L1+L2
plane1 plane3
R2
L2
G1
L2 G2
C2
Fig. 4 The M-FDM cell including three planes [6].
A. Modeling of Multilayered Plane Pairs Based on the MFDM The M-FDM models multilayered planes as Fig. 4. In this case, the plane3 is chosen as the common reference terminal. If the partial self inductance of the plane1 and plane2 is L1 and L2 respectively, the partial mutual inductance L2 is introduced between the plane 1 and the plane2. An example of Fig. 5 cannot be simply modeled by the unit cell models because the right-half of middle plane is missing. In contrast, the M-FDM can model it as Fig. 6. Though the equivalent circuit of Fig. 6 can be solved by the SPICE, it is difficult for the leapfrog algorithm to solve it because the leapfrog algorithm has a limitation of the circuit structure to be analyzed. Plane1 Pair1 Plane2
z
Pair2 Plane3
y
x
Fig. 5 An example missing the right-half of middle plane.
Vbn−1 − Vbn = sL2 I an−1 + (R2 + sL2 )I bn−1 ,
(7)
where s = jω. Also, the KCL equations are obtained by
(G + sC )(Van − Vbn ) = I an−1 − I an ,
(8)
(G + sC )Vbn = I bn−1 − I bn + I an−1 − I an .
(9)
Assuming that the conductor loss is ignorable, such as R1=R2=0, we introduce change of variables as follows:
Vabn = Van − Vbn , Vabn−1 = Van−1 − Vbn−1 ,
(10)
′ = I an + I bn , I bn ′ −1 = I an−1 + I bn−1 . I bn
(11)
As a result, (6)-(9) are rewritten as follows:
Vabn−1 − Vabn = sL1I an−1 ,
(12)
′ −1 , Vbn−1 − Vbn = sL2 I bn
(13)
(G + sC )Vabn = I an−1 − I an ,
(14)
(G + sC )Vbn = I bn′ −1 − I bn′ .
(15)
Actually, (12)-(15) are completely same as the KVL and the KCL of the equivalent circuit using the unit cell models as shown in Fig. 7(b). Therefore, we can find equivalence between the MFDM and the unit cell model if R is ignorable. However, the conductor loss is usually not negligible in the high-frequency. In the case including the conductor loss, Fig. 7(a) does not mathematically equal to Fig. 7(b). Therefore, we modify the equivalent circuit based on the M-FDM to Fig. 8 in order to correct the treatment of the conductor loss. In this modification, mutual resistances are introduced between the plane 1 and the plane2. The KVL equations of Fig.8 are written as
Fig. 6 An equivalent circuit of Fig. 5 using the M-FDM.
Van−1 − Van = (R1 + R2 + sL1 + sL2 )I an−1 + (R2 + sL2 )I bn−1 , (16)
Vbn−1 − Vbn = (R2 + sL2 )I an−1 + (R2 + sL2 )I bn−1 .
(17)
Using (10) and (11), (16) and (17) are rewritten as follows: (a)
(b)
Fig.7 A simple one-dimensional example. (a): Using the M-FDM. (b): Using the unit cell model. B. Equivalence between the Unit Cell Model and the M-FDM If there are no holes and apertures between multilayered plane pairs, an equivalent circuit produced by the M-FDM should mathematically equal to ones consisting of the simple unit cell models. For instance of a simple one-dimensional case including three planes as shown in Fig. 7, the KVL equations of the equivalent circuit produced by the M-FDM are obtained by
Van−1 − Van = (R1 + sL1 + sL2 )I an−1 + sL2 I bn−1 ,
(6)
Vabn−1 − Vabn = (R1 + sL1 )I an−1 ,
(18)
′ −1 . Vbn−1 − Vbn = (R2 + sL2 )I bn
(19)
We can find that (18) and (19) are equal to the KVL of the equivalent circuit using the unit cell models as shown in Fig. 7(b). If the equivalent circuit of Fig. 8 will be analyzed by the SPICE, we can use the H-element, which is the current-controlled voltage-source, as the mutual resistances. On the other hand, it is difficult for the LIM to solve equivalent circuits produced by the M-FDM and the modified M-FDM, because they do not meet the LIM conditions.
Fig.11 The overall equivalent circuit(a) produced by our proposed method for Fig. 5.
Ian-1 Ian L +L L +L Van-1 1 2 R1+R2 1 2 R1+R2 Van R 2 R2 L2 L2 G C C L2 R2 L2 R2 Vbn-1 Vbn I Ibn-1 bn G
G
C
G
L1
G L2
C
L1
R1
L1+L2 R1
Vz1
Ix1 C
R2
L2
Ix1 G R2 Vz2
C
L1+L2 R1
Ia Vz1 G/2
C/2
G/2
C/2
Vz2
Fig.8 An equivalent circuit using our modified M-FDM. IV.
R1
SUITABLE MODELING OF MULTILAYERED PLANE PAIRS FOR LEAPFROG ALGORIHTM
In this section, we propose an effective modeling method for multilayered P/G plane pairs having holes and apertures. In our method, each independent plane pair coupled in a vertical direction is modeled as the lumped RLC equivalent circuit consisting of the unit cell models. For example of Fig. 5, the plane1 and 3 are coupled at the right-half of the planes. Therefore, this pair is modeled as an independent equivalent circuit. Also, because there are two plane pairs at the left-half of the planes, three independent equivalent circuits can be obtained as shown in Fig. 9.
G
C
G
C
Ia
Fig.12 The overall equivalent circuit(b) produced by our proposed method for Fig. 5. Next, it is necessary to properly connect three equivalent circuits. Though the reference [6] mentioned that it is difficult to realize interconnections between plane pairs, it is not difficult to properly connect them if we think this problem at the electromagnetic level. First, voltages, currents and magneticfields are defined as shown in Fig. 10. Here, Δx, Δy and Δz denote the unit cell size in the x-, y- and z-direction, respectively. For example, the relation between Vz1 and Iz1 can be represented as
ΔxΔy ⎞ ⎛ ΔxΔy I z1 = ⎜ σ + sε ⎟Vz1 = (G + sC )Vz1 , Δz ⎠ Δz ⎝
(20)
where σ and ε are dielectric loss and permittivity, respectively. Next, the vertical currents Iz1 and Iz2 can be approximated by the Ampere's low as follows:
Fig.9 Three independent equivalent circuits for Fig. 5.
Ix1 Hy1 Vz1
Iz1
Ix2 Hy2 Vz2
Iz2
Ia Hy3 (ε,μ,σ)
z y x
I z1 ≈ H y1Δy − H y 3 Δy = I x1 − I a ,
(21)
I z 2 ≈ H y 2 Δy − H y 3 Δy = I x 2 − I a ,
(22)
where the magnetic fields in x-direction are omitted. As a result, three equivalent circuits as shown in Fig. 9 can be connected by the VCVS and the CCCS as illustrated in Fig. 11. Also, Fig. 12 is mathematically same as Fig. 11. Though the Fig. 5 is typical example, our method can model more complicated structures without any difficulty. Furthermore, equivalent circuits produced our proposed method can be solved by the leapfrog algorithm, such as the LIM.
Fig.10 The definition of variables in order to connect the three equivalent circuits of Fig. 9.
Fig. 13 An example of PDN.
[V] 1 0.5 0
0
2
4
[nsec]
Fig. 14 The voltage waveform at Vin. V.
NUMERICAL RESULTS
First, in order to verify the validity of our modeling method, we simulated a PDN as illustrated in Fig. 13. The source point of Vin was excited with a triangular waveform as plotted in Fig. 14. The P/G plane pairs are modeled by three different modeling methods, namely the M-FDM, the modified M-FDM and our proposed method in Section IV. To verify our modeling validity and efficiency, we compared the transient responses simulated using the Synopsys's Star-HSPICE. All simulations were performed on an Intel Core2Duo 2.33GHz personal computer with 32bit-WindowsVista operating system. HSPICE uses a fixed timestep size, which is selected as 3.54 psec from (5). Also, we set the ACCURATE option to 1. In HSPICE, if the ACCURATE option sets to 1, more detailed simulation can be performed, but it would take longer simulation time [8].
Next, in order to verify the efficiency of the leapfrog algorithm, we simulated transient responses of a PDN. Its layout is same as Fig. 13, but the depth of planes changed 25mm to 100mm. The transient response simulated using our transient circuit simulator based on the leapfrog algorithm is compared with FALCON [9], which is our linear circuit simulator based on the sparse LU-decomposition [10], and HSPICE. In this simulation, the HSPICE simulation was performed by changing the timestep option in twice. Our two simulators were compiled using the MS-Visual C++ compiler version 2008. In the FALCON and HSPICE simulation, number of nodes for the equivalent circuit produced by our proposed modeling method became to 76,860. [V]
π fμ , 2 + 2 σt σ
Proposed modeling
0.2 0 –0.2 0
2
4
[nsec]
Fig. 15 The voltage waveform at Vout.
(23)
[V]
where f is the signal frequency. Of course we can use the frequency-dependent unit cell model proposed in [5], but the frequency-independent model is used for simplification. In this simulation, assuming f = 1GHz, conductor loss is R ≅ 0.182 Ω.
0.3
The voltage waveforms at Vout simulated using HSPICE are plotted in Fig. 15. The waveform for our proposed modeling method is in good agreement with the others. Next, in order to verify the correctness of modeling the conductor loss, we purposely increase the conductor loss 10 times larger. After this modification, we performed HSPICE simulations again. The voltage waveforms at Vout are plotted in Fig. 16. The waveforms for our proposed modeling method and the modified M-FDM agree completely, but the waveform for the M-FDM is different from the others, because of the reason described in Section III. Table 1 shows the CPU time of the each HSPICE simulation. We can find that the equivalent circuit produced by our proposed method can be solved faster than ones produced by the M-FDM and the modified M-FDM, because the number of fill-ins for our modeling method is the smallest. The reason for the smallest fillin numbers is that all capacitors in our equivalent circuit are grounded.
Modified M–FDM
0.4
The dimensions and medium coefficients of the unit cell are w = 1.0mm, d = 0.2mm, t = 0.02mm, σ = 5.8×107, εr = 4.5 where w, t and d are defined in Fig. 1. The conductor loss is calculated from
R =
M–FDM
M–FDM
Modified M–FDM
Proposed modeling
0.1
–0.1 0
2
4
[nsec]
Fig. 16 The voltage waveform at Vout with 10 times larger conductor loss. Table 1 The CPU time comparisons of HSPICE simulation. M-FDM CPU time(sec) Num. of Nodes Num of Fill-ins
68.05 19,354 189,313
Modified M-FDM 319.7 39,954 499,251
Proposed modeling 46.12 19,560 112,838
VI.
[V] HSPICE with fixed timestep Our LU linear simulator (FALCON) Our leapfrog simulator
0.4 0.2 0
CONCLUTIONS
In this paper, we proposed an effective modeling method for multilayered P/G plane pairs having holes and apertures. From the numerical results, the equivalent circuits produced by our method can be solved faster than ones produced by the M-FDM even using the SPICE. Also, it is obvious that our modeling method can correctly model the conductor loss. Furthermore, the leapfrog algorithm enables a speedup of 486 times compared to the HSPICE with the same level of accuracy. ACKNOWLEDGMENT
–0.2 0
5
10 [nsec]
This work was supported, in part, by Semiconductor Technology Academic Research Center (STARC), Japan.
Fig. 16 The voltage waveform at Vout.
REFERENCES [1]
[V] HSPICE with fixed timestep 0.4
HSPICE with variable timestep
0.2 0 –0.2 0
5
10 [nsec]
Fig. 17 The voltage waveform at Vout. The voltage waveforms at the Vout are plotted in Fig. 16. From Fig. 16, the waveform calculated by our simulator is in good agreement with FALCON and HSPICE with the fixed timestep. Table 2 shows that our simulator is about 105 and 486 times faster than FALCON and HSPICE, respectively, with the same timestep size. If HSPICE uses the variable timestep, the CPU time is improved, but the accuracy of simulation is reduced as shown in Fig. 17. Table 2 The CPU time comparisons of HSPICE and Our leapfrog simulator. CPU time(sec) HSPICE with fixed timestep
1138.26
HSPICE with variable timestep
96.26
Our LU linear simulator (FALCON)
246.16
Our leapfrog simulator
2.34
L.D. Smith, R. Anderson, and T. Roy, "Power Plane SPICE Models and Simulated Performance for Materials and Geometries," IEEE Trans. on Advanced Packaging, vol. 24, no. 3, pp.277-287, Aug. 2001. [2] J.E.Shutt-Aine, "Latency Insertion Method (LIM) for the Fast Transient Simulation of Large Networks," IEEE Trans. on Circuits and Systems-I, vol. 48, no.1 pp. 81--89, Jan. 2001. [3] Z. Deng and J. E. Schutt-Aine, "Stability analysis of latency insertion method (LIM)," in Proc. of IEEE Topical Meeting on Electrical Performance of Electronic Packaging (EPEP) 2004, pp. 167-170, 2004. [4] T.Watanabe, Y.Tanji, H.Kubota, and H.Asai, "Parallel-Distributed TimeDomain Circuit Simulation of Power Distribution Networks with Frequency-Dependent Parameters," in Proc. of Asia and South Pacific Design Automation Conference (ASP-DAC) 2006, Jan. 2006. [5] T.Watanabe, Y.Tanji, H.Kubota and H.Asai, “Fast Transient Simulation of Power Distribution Networks Containing Dispersion Based on ParallelDistributed Leapfrog Algorithm,” IEICE Trans. on Fundamentals of Electronics, Com-munications, Vol.E90-A, No.2, pp.388-397, Feb. 2007. [6] E.Engin, K.Bharath and M.Swaminathan, "Multilayered finite-difference method (MFDM) for modeling of package and printed circuit board planes", IEEE Trans. on EMC, Vol.27, No2. 2007. [7] K.Bharath, E.Engin, M.Swaminathan, K.Uriu, T.Yamada, "Signal and Power Integrity Co-Simulation for Multi-layered System on Package Modules," in Proc. of IEEE International Symposium on Electromagnetic Compatibility 2007, pp.1-6, July 2007. [8] Synopsys Corporation, "HSPICE Simulation and Analysis User Guide," pp.312, June 2006. [9] Y.Tanji, T.Watanabe, H.Asai, "Implementation of Linear Circuit Simulator FALCON on Multi-Core CPU," IEICE Technical Report, vol. 109, no. 167, NLP2009-58, pp. 77-81, Aug. 2009 (in Japanese). [10] K.Kundert, "SPARSE1.4", http://sparse.sourceforge.net/
