FPGA Implementation of Boolean. Neural Networks using UML. Roman Kohut,
Bernd Steinbach, Dominik Fröhlich. Freiberg University of Mining and ...
FPGA Implementation of Boolean Neural Networks using UML Roman Kohut, Bernd Steinbach, Dominik Fröhlich Freiberg University of Mining and Technology Institute of Computer Science Freiberg (Sachs), Germany
Outline • Introduction • Boolean Neural Networks • UML-Models • Experiment results • Conclusion FPGA Implementation of Boolean Neural Networks using UML 2 th Kohut, R., Steinbach, B., Fröhlich, D. 7 International Workshop on Boolean Problems, Freiberg, Sept. 21-22, 2006
Introduction •FPGAs y = f (x), x ={x1, x2,…, xNx},
Nx ≤ 4
5
slice
Nx ≤ 5
6
CLB
Nx ≤ 6
Slice structure FPGA Implementation of Boolean Neural Networks using UML 3 th Kohut, R., Steinbach, B., Fröhlich, D. 7 International Workshop on Boolean Problems, Freiberg, Sept. 21-22, 2006
Introduction • The Problem • Connectivity problems, • Structured problems • limited number of logic gates • and interconnections, • On-Chip learning problems (sequential computations), •… Large number of CLBs (10th-100th) are required for one single neuron GANGLION - (640-784) CLBs, Gschwind NN - 22 CLBs, Xilinx-NN 51 CLBs, Hopfield NN - 26 CLBs.
Large number of CLBs
type of data
number of inputs
complex tranfer function
FPGA Implementation of Boolean Neural Networks using UML 4 th Kohut, R., Steinbach, B., Fröhlich, D. 7 International Workshop on Boolean Problems, Freiberg, Sept. 21-22, 2006
Boolean Neural Networks •Boolean Neuron Inputs
y = f ( x, w )
x1
w1 w2 w3
x2
yB = f B (xB , w B )
Weights of synaptic connections
x3
wNx
Transfer function
fB
Output
y = f ( x, w)
xNx
{
x B = x1 , x2 ,..., x N x
{
w B = w1 , w2 ,..., wN x
fB yB
}
}
xi ∈ {0,1}
wi ∈ {0,1}
- Boolean transfer function - output signal
f B , y B ∈ {0,1}
General structure of Boolean neuron
Advantages of the BN: • speeding up of calculation significantly, • reduction of necessary memory size,
• possibility to map the BN into one single CLB of FPGAs.
FPGA Implementation of Boolean Neural Networks using UML 5 th Kohut, R., Steinbach, B., Fröhlich, D. 7 International Workshop on Boolean Problems, Freiberg, Sept. 21-22, 2006
y
Boolean Neural Network • Structure x1
Nk1
k1
• LUT of CLB
y1
N1
inputs
x1
Nk2
x2
…
N2
k2
…
xNx
…
LUT: Slice: CLB:
x2 x3 x4
… yNy
kZn NkZn NkZn, NkZn, NkZn,
y2
NNy ≤ 4 NNy ≤ 5 NNy ≤ 6
weight coefficients w1 w2 w3 w4
fB
output y y = fB (xB, wB)
transfer function
NNy
Nx=4
LUT
Training algorithm FPGA Implementation of Boolean Neural Networks using UML 6 th Kohut, R., Steinbach, B., Fröhlich, D. 7 International Workshop on Boolean Problems, Freiberg, Sept. 21-22, 2006
Boolean Neural Networks • Mapping of BNN to FPGA LUT1
BN1
LUT2
BN2
LUT3
BN3 …
…
BN4
BN6
…
…
LUT4 LUT5
BN5 LUT6
FPGA Implementation of Boolean Neural Networks using UML 7 th Kohut, R., Steinbach, B., Fröhlich, D. 7 International Workshop on Boolean Problems, Freiberg, Sept. 21-22, 2006
UML Models • Example
• Structure of BNN y0
x 1 x2 x3
k1 k 2 k 3 k 4
0 0 0 0 1 1 1 1
0 1 0 1 0 1 1 0
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 0 0 0 1 0 0 0
1 1 0 0 0 0 0 0
0 0 1 0 0 1 0 1
y 0 y1 y2 y3 y4 y5 y6 y 7 y 8 y9 k1 k2 k3 k4
1 0 0 0
1 1 0 0
0 0 1 1
1 0 1 0
0 1 0 1
1 0 0 1
1 1 1 0
0 1 1 0
0 1 1 1
0 0 0 1
k1
x1 y1
k2
x2 …
k3
x3 y9 k4
FPGA Implementation of Boolean Neural Networks using UML 8 th Kohut, R., Steinbach, B., Fröhlich, D. 7 International Workshop on Boolean Problems, Freiberg, Sept. 21-22, 2006
UML Models • Design Model Main
-app
+create() :Main Main 1 +destroy() : void -app ... +main() : int 1 +create() : Main +destroy() : void +main() : int boolean[] x=new boolean[Nx]; boolean[] y=new boolean[Ny]; Bnn net = new Bnn(); ... net.init_x(x); if(net.calculate()) { y=net.get_y(); ... } destroy net; destroy y; destroy x; return 0;
Bnn
calculate -bnn Bnn +a : boolean 1 +b : boolean calculate -bnn ... +c : boolean 1 +create() :||Bnn return (!a&&!c || a&&!b&&c a&&b&&!c); +y00 : boolean +destroy() : void +y01 : boolean +calculate() : boolean ... ...
return k01 || k02;
k01=k1(); k02=k2(); ... y00=y0(); y01=y1(); ... y09=y9(); return true;
y[0]=y00; y[1]=y01; ... y[9]=y09; return y;
a=inputs[0]; b=inputs[1]; c=inputs[2];
+create() : Bnn +destroy() : void +k1() : boolean +k2() : boolean +...() +y0() : boolean +y1() : boolean +...() +calculate() : boolean +init_x( x : boolean[] ) : void +get_y() : boolean[] ...
FPGA Implementation of Boolean Neural Networks using UML 9 th Kohut, R., Steinbach, B., Fröhlich, D. 7 International Workshop on Boolean Problems, Freiberg, Sept. 21-22, 2006
UML Models • Deployment Model Implementations platforms: • C++ • VHDL Hardware platform: • Pentium IV processor ¾ 2.4 GHz • Xilinx Virtex-II FPGA ¾ 3 million gates ¾ 100 MHz
C++
VHDL
h0
- master
Communication Path
-slave
1
1
h1
Main
main.exe
BNN bnn.bit
Communication Path: •PCI-Bus ¾33 MHz
Main
Bnn
FPGA Implementation of Boolean Neural Networks using UML 10 th Kohut, R., Steinbach, B., Fröhlich, D. 7 International Workshop on Boolean Problems, Freiberg, Sept. 21-22, 2006
Experiment results • Device Utilization Summary compilation/synthesis time: • 3 - 5 minutes Logic Utilization # Slices: # Flip Flops: # LUTs: # IOBs:
Used for Bnn 64 (49) 92 (79) 91 (56) 102
Bnn::calculate: • 21 (14) LUTs, • execution time: 0.200 µs
Method Bnn::calculate Bnn::create Bnn::destroy Bnn::k1 Bnn::k2 Bnn::k3 Bnn::k4 Bnn::y0 Bnn::y1 Bnn::y2 Bnn::y3 Bnn::y4 Bnn::y5 Bnn::y6 Bnn::y7 Bnn::y8 Bnn::y9
# Slices 18 1 1 4 3 2 3 2 2 2 2 2 2 2 2 2 2
#Flip Flops 27 1 1 5 4 4 5 3 3 3 3 3 3 4 3 4 3
#4-input LUTs 21 0 0 7 5 3 4 2 3 3 3 3 3 3 3 3 2
FPGA Implementation of Boolean Neural Networks using UML 11 th Kohut, R., Steinbach, B., Fröhlich, D. 7 International Workshop on Boolean Problems, Freiberg, Sept. 21-22, 2006
Experiment results • Technology schematic of Bnn::k4()
FPGA Implementation of Boolean Neural Networks using UML 12 th Kohut, R., Steinbach, B., Fröhlich, D. 7 International Workshop on Boolean Problems, Freiberg, Sept. 21-22, 2006
Conclusion • Results (1) UML based hardware/software co-design of Boolean neural networks, (2) decreasing of the required number of configurable logic blocks (CLB) for the realizing of Boolean neuron, (3) Boolean neuron can be mapped directly to lookup table (LUT) and configurable logic block (CLB) of FPGAs, (4) efficient FPGA implementations of BNNs in terms of performance and gate count.
FPGA Implementation of Boolean Neural Networks using UML 13 th Kohut, R., Steinbach, B., Fröhlich, D. 7 International Workshop on Boolean Problems, Freiberg, Sept. 21-22, 2006
Conclusion •Future work • •
optimal presentation of Boolean functions by BNNs, automated hardware/software synthesis with MOCCA and UML, • optimization of FPGA implementation of Boolean neural networks, • design and develop of mapping methodology for Boolean neural networks with on-chip learning.
FPGA Implementation of Boolean Neural Networks using UML 14 th Kohut, R., Steinbach, B., Fröhlich, D. 7 International Workshop on Boolean Problems, Freiberg, Sept. 21-22, 2006
