FPGA Implementation of Various Image Processing Algorithms Using Xilinx System Generator M. Balaji and S. Allin Christe
Abstract This paper makes an comparison between two architectures existing and modified for various image processing algorithms like image negative, image enhancement, contrast stretching, image thresholding, parabola transformation, boundary extraction for both grayscale and color images. The synthesis tool used is Xilinx ISE 14.7 and designed in simulink (MATLAB 2012a) workspace. The existing and modified architectures is implemented using Xilinx System Generator (XSG) and hardware software co-simulation is done using Spartan 3E FPGA board. The results and resource utilization for both the architectures is obtained the results shows that the modified architectures shows an average 39 % less resource utilization than that of the existing architecture also for boundary extraction the modified architectures produced refined results while comparing visually with the existing architecture results. Keywords Co-simulation system generator
Image processing MATLAB Simulink Xilinx
1 Introduction Image processing is a method to convert an image into digital form and perform some operations on it, in order to get an enhanced image or to extract some useful information from it. It is a type of signal dispensation in which input is image, like video frame or photograph and output may be image or characteristics associated with that image. Usually Image Processing system includes treating images as two M. Balaji (&) S.A. Christe Department of ECE, PSG College of Technology, Peelamedu, Coimbatore 641004, India e-mail:
[email protected] S.A. Christe e-mail:
[email protected] © Springer India 2015 L.C. Jain et al. (eds.), Computational Intelligence in Data Mining - Volume 2, Smart Innovation, Systems and Technologies 32, DOI 10.1007/978-81-322-2208-8_7
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dimensional signals while applying already set signal processing methods to them. It is one-among the rapidly growing technologies today, with its applications in various aspects of a business. Image Processing forms core research area within engineering and computer science disciplines too. Image processing basically includes three steps importing the image with optical scanner or by digital photography, then analyzing and manipulating the image which includes data compression and image enhancement and spotting patterns that are not visible to human eyes like satellite photographs, finally output is the last stage in which result can be altered image or report that is based on image analysis. The purpose of image processing can be visualization, image sharpening and restoration, image retrieval, measurement of pattern, image recognition. Digital Image Processing techniques help in manipulation of the digital images by using computers. As raw data from imaging sensors from satellite platform contains deficiencies. To get over such flaws and to get originality of information, it has to undergo various phases of processing. The three general phases that all types of data have to undergo while using digital technique are pre-processing, enhancement and display, information extraction. This paper focus on developing algorithmic models in MATLAB using Xilinx blockset for specific purpose, creating workspace in MATLAB to process image pixels in the form of multidimensional image signals for input and output images, performing hardware implementation [1] of given algorithms on FPGA.
2 Xilinx System Generator XSG [2] is an Integrated Design Environment (IDE) for FPGAs, which uses simulink [3], as a development environment and is presented in the form of model based design. The Xilinx System Generator for DSP is a plug-into Simulink that enables designers to develop high-performance DSP systems for Xilinx FPGAs. Designers can design and simulate a system using MATLAB, Simulink, and Xilinx library of bit/cycle-true models. The tool will then automatically generate synthesizable Hardware Description Language (HDL) code mapped to Xilinx pre-optimized algorithms. This HDL design can then be synthesized for implementation in FPGA. As a result, designers can define an abstract representation of a system-level design and easily transform this single source code into a gate-level representation. Additionally, it provides automatic generation of a HDL testbench, which enables design verification upon implementation.
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3 Proposed Design The proposed architecture for various image processing algorithms using simulink and Xilinx blocks is divided into 3 phases. In the proposed design the input image used for all the algorithms is of the size 256 × 256 but this proposed method can be used for any size of images. The image format used in this paper is png, jpg formats but the proposed method can be applied for any image formats. • Image pre-processing • FPGA based implementation of image processing algorithms • Image post-processing Generally image will be in the form of matrix but in the hardware level implementation this matrix must be an array of one dimension hence we need to pre-process [4] the image but in the case of software level simulation using simulink blocksets alone, the image can be taken as a two-dimensional arrangement such as m × n, there is no need for any image pre-processing. Also image postprocessing blocks which are used to convert the image output back to floating point type is done using Simulink blocksets whose model based design in [4] is used here. The algorithm steps that is followed for all the implemented algorithms is given below. Step 1 Image pre-processing using simulink blocksets • • • • •
Image from file: Fetches the input image from a file. Resize: Resizes the input image to a defined size. Convert 2-D to 1-D: Converts 2-D image to a single array of pixels. Frame conversion: Converts entire set of elements to a single frame. Unbuffer: Converts frame to scalar samples output at a higher sampling rate.
Step 2 Implementation of image processing algorithms using Xilinx blocksets • Gateway In: Used for Xilinx fixed point data type conversion. • Hardware blocks: Here only the real processing starts. Depending on the algorithms these blocksets will change. • Gateway Out: Convert Xilinx fixed point data type back to simulink integer. Step 3 Image post-processing using simulink blocksets • Data type conversion: Converts image signal to unsigned integer format. • Buffer: Converts scalar samples to frame based output at lower sampling rate. • Convert 1-D to 2-D: Convert 1-D image signal back to 2-D image. • Video Viewer: To display the processed output image.
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The few improved design using Xilinx blocksets for various image processing algorithms is given below. (a) Algorithm for grayscale and color image negative, image enhancement, contrast stretching, image thresholding, parabola transformation using M-Code block The existing architecture [4, 5] which is implemented for the image negative, image enhancement, contrast stretching, image thresholding, parabola transformation algorithm is replaced with M-code block in this modified architecture shown in Figs. 1 and 2. In proposed method why we go for M-code block is that in the existing method the above mentioned algorithms is implemented using various number of Xilinx blocksets but if we use M-code block those various number of blocksets can be replaced with a single Xilinx block which results in reduction of various factors for example resource utilization in this case. (b) Algorithm for image boundary extraction The existing architecture [4] which is implemented for the image thresholding algorithm is replaced with the architecture shown in Fig. 3.
Fig. 1 Implementation for image negative, image enhancement, contrast stretching, image thresholding, parabola transformation using M-Code block for grayscale images
Fig. 2 Implementation for image negative, image enhancement, contrast stretching, image thresholding, parabola transformation using M-Code block for color images
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Fig. 3 Implementation for image boundary extraction
4 Results The different image processing algorithms which are discussed above are implemented using Spartan 3E FPGA board and their corresponding hw/sw co-simulation level outputs for grayscale image which is implemented is shown in Figs. 4, 5, 6, 7 and 8. The input and hw/sw co-simulated output images of various image processing algorithms for color image implemented using Spartan 3E FPGA board is shown in Figs. 9, 10, 11, 12 and 13. The resources that are utilized by Spartan 3E FPGA board while implementing existing and modified architectures for various image processing algorithms for both grayscale and color images and percentage of reduction in resource utilization for proposed architecture with the existing architecture [4, 5] is given in Table 1.
Fig. 4 Grayscale image negative. a Input image. b Output image
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Fig. 5 Grayscale image contrast stretching. a Input image. b Output image
Fig. 6 Grayscale image thresholding. a Input image. b Output image
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Fig. 7 Grayscale image parabola transformation. a Input image. b Output image
Fig. 8 Image boundary extraction. a Input image. b Output image
Fig. 9 Color image negative. a Input image. b Output image
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Fig. 10 Color image enhancement. a Input image. b Output image
Fig. 11 Color image contrast stretching. a Input image. b Output image
Fig. 12 Color image thresholding. a Input image. b Output image
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Fig. 13 Color image parabola transformation. a Input image. b Output image
Table 1 Resource utilization by Spartan 3E FPGA board for existing and modified architectures Algorithm
Resource utilization by Spartan 3E for existing and proposed architectures Existing method Proposed method Slices FF’s LUT’s IOB’s Slices FF’s LUT’s IOB’s
Image 17 0 25 negative Color image 51 0 75 negative Image 16 0 2 enhancement Color image 48 0 12 enhancement Contrast 85 0 82 stretching Color contrast 255 0 246 stretching Image 6 1 12 thresholding Color image 18 3 36 thresholding Parabola 908 0 1,779 transformation Color 8,502 0 16,422 parabola transformation Boundary 882 1,386 947 extraction
Percentage of reduction in resource utilization (%)
65
0
0
0
64
40.19
195
0
0
0
192
40.19
65
7
0
2
65
10.84
195
21
0
6
195
12.94
98
28
0
36
69
49.81
294
84
0
108
207
49.81
64
6
0
11
40
31.33
192
18
0
33
120
31.33
195
155
0
298
108
80.53
585
756
0 1,437
324
90.13
64
879
40
1.25
1,376
943
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5 Conclusion In this paper two architectures existing and modified for various image processing algorithms like image negative, image enhancement, contrast stretching, image thresholding, parabola transformation, boundary extraction for both grayscale and color images is implemented. Also resource utilization for the two implemented architectures is tabulated and compared. It can be seen from the above results that the modified methodology shows an average 39 % less resource utilization when compared with the existing methodology [4, 5]. Also when comparing visually for boundary extraction the modified methodology produces refined boundaries while comparing with the existing methodology. This modified methodology could also be extended for different image processing algorithms and also for higher end boards with proper user configuration.
References 1. Christe, S.A., Vignesh, M., Kandaswamy, A.: An efficient FPGA implementation of MRI image filtering and tumor characterization using Xilinx system generator. Int. J. VLSI Des. Commun. Syst. 2(4) (2011) 2. Xilinx System Generator User’s Guide. http://www.Xilinx.com 3. MATLAB. http://www.mathworks.com 4. Neha, P.R., Gokhale, A.V.: FPGA implementation for image processing algorithms using xilinx system generator. IOSR J. VLSI Signal Process. 2(4), 26–36 (2013) 5. Elamaran, V., Rajkumar, G.: FPGA implementation of point processes using xilinx system generator. J. Theoret. Appl. Inf. Technol. 41(2) (2012)
