Vol.31 No.5
JOURNAL OF ELECTRONICS (CHINA)
October 2014
OPTIMIZED REVERSIBLE ARITHMETIC LOGIC UNITS1 Payman Moallem
Maryam Ehsanpour*
Ali Bolhasani**
Mehrdad Montazeri***
(Department of Electrical Engineering, University of Isfahan, Isfahan, Iran) (Department of Computer, Falavarjan Branch, Islamic Azad University, Falavarjan, Iran) ** (Department of Computer, Arak Branch, Islamic Azad University, Arak, Iran) *** (Department of Computer, Faculty of Engineering, Polytechnic University of Turin, Turin, Italy) *
Abstract Arithmetic Logic Unit (ALU) as one of the main parts of any computing hardware plays an important role in digital computers. In quantum computers which can be realized by reversible logics and circuits, reversible ALUs should be designed. In this paper, we proposed three different designs for reversible 1-bit ALUs using our proposed 3×3 and 4×4 reversible gates called MEB3 and MEB4 (Moallem Ehsanpour Bolhasani) gates, respectively. The first proposed reversible ALU consists of six logical operations. The second proposed ALU consists of eight operations, two arithmetic, and six logical operations. And finally, the third proposed ALU consists of sixteen operations, four arithmetic operations, and twelve logical operations. Our proposed ALUs can be used to construct efficient quantum computers in nanotechnology, because the proposed designs are better than the existing designs in terms of quantum cost, constant input, reversible gates used, hardware complexity, and functions generated. Key words gates
Reversible Arithmetic Logic Unit (ALU); Full Adder (FA); Control unit; Reversible logic
CLC index
TN47
DOI 10.1007/s11767-014-4081-y
I. Introduction In the regard of power dissipation, irreversible computation inherently leads to the energy losses due to the missing data bit. Landauer[1] demonstrated that, the amount of heat dissipated for operation of every bit of information, regardless of its realization technique, is given by kTln2, where k is the Boltzmann’s constant (1.38×10–23JK–1) and T is the absolute temperature. Bennett[2] showed that the energy loss in a logic circuit can be avoided by designing reversible logic circuits with an acyclic combinational logic gates[3] in which all gates are reversible, and are interconnected without explicit fan-outs and loops. Reversible gates can be realized by quantum circuits[1–4]. If the function F is reversible then unique one-to-one mapping is existed 1
Manuscript received date: March 29, 2014; revised date: August 18, 2014. Communication author: Payman Moallem, born in 1970, male, Ph.D., Associate Professor. Department of Electrical Engineering, University of Isfahan, Hezarjerib Street, 81746, Isfahan, Iran. Email:
[email protected].
between an n-input vector and a corresponding n-output vector[4–7]. Quantum logic gates are inherently reversible and that are construct based on reversible logic. Reversible logic is considered as a novel alternative for reduction of the physical entropy gain[5–9]. Reversible computing is one of the aspects of quantum computer. Reversible logic is a new developed field of study that holds promise for quantum computing[5,8]. In quantum computing, any state of the computation is described by a state pattern that is a complex linear superposition of all binary digit states. A qubit is the quantum of a classical bit, which can be in a state of superimposition of zero and one. A reversible logic gate is an m-input, m-output circuit which generates a unique output vector OV for each possible input vector IV where IV = (I 0 , I 1, I 2 , ", I m −1, I m ) and OV = (O0 , O1, O2 , ", Om −1, Om ). A brief review on reversible logics fundamentals and corresponding parameters are presented in the appendix. There are many reversible logic gates which have been presented in the state
MOALLEM et al. Optimized Reversible Arithmetic Logic Units
of the art literatures, like: Feynman Gate (FG)[6] with quantum cost of 1, Peres Gate (PG)[5] with quantum cost of 4, Toffoli Gate (TG)[7] with quantum cost of 5, Fredkin Gate (FRG)[8] with quantum cost of 5, Haghparast Navi Gate (HNG)[9] with quantum cost of 6, Thapliyal Ranganathan Gate (TRG)[10] with quantum cost of 4, and Reversible Multiplexer (RMUX1) gate[11] with quantum cost of 4. Also, other beneficial gates were presented in previous works. Among them, 4×4 Double Peres Gate (DPG)[12] with quantum cost of 6, 4×4 Morrison Ranganathan Gate (MRG)[13] with quantum cost of 6, and 3×3 Yarlagadda Alapati Gate (YAG)[14] with quantum cost of 4 can be mentioned. Fig. 1 presents some of these reversible gates including their logical operations as well as quantum implementations.
Fig. 1 Some reversible gates including FG, PG, TG, TRG, RMUX1, and HNG
There are some major issues for determining the complexity and performance of reversible circuits. To evaluate reversible logic circuits, researchers considered different cost metrics such as the number of gates, garbage outputs, constant inputs, quantum cost, and hardware complexity[15–19]. In the analysis of a reversible logic circuit, these different cost metrics should be determined and compared to other similar circuits. Quantum cost is
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referred as the number of 1×1 and 2×2 gates. The quantum cost and the hardware complexity should be minimized. Secondly, the number of gates, constant inputs and garbage outputs, which are utilized for maintaining the reversibility of the logic circuit, must be diminished[5–7]. Minimization of the cost parameters is also required. Reduction of the number of gates, garbage outputs, constant inputs, quantum cost, and hardware complexity is needed to improve design and costs[2,15–18]. Reversible circuits for different purposes e.g. HA (Half Adder), FA (Full Adder)[16], and multiplier[17–19] have been proposed recently. Among these reversible circuits, Arithmetic Logic Unit (ALU) is very important in the digital processing. ALU is a main structure of a Central Processing Unit (CPU) in any computing system. It can be generate to Boolean functions, such as XOR, NAND, and OR. The ALU is central for the design of the instruction set of a programmable computing device. Consequently, optimized ALUs are on demand in computer system and DSP (Digital Signal Processor). Fig. 2 shows a basic ALU composed of two inputs for the operands, one input for selecting the control operation, and one output for the product. An ALU performs one of the several possible functions on two operands A and B depending on control inputs. In addition, the ALUs are suitable for different quantum technology and embedded processors.
Fig. 2
General form of ALU
This paper focuses on the design of reversible ALUs that can be part of a programmable reversible computer. Reversible ALUs help us to build more complex systems and low-power digital circuit in nanotechnology and quantum computers. In this study, we propose three new designs of reversible ALU which could handle different elementary arithmetic and logical operations. According to the classical ALU, a reversible
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ALU can be constructed with a multiplexer (MUX) to select one of the operations of ALU. In an ALU, ADD and SUB are basic arithmetic operations, while NOT, OR, AND, NOR, NAND, XOR, and MUX functions are basic logical operations. Arithmetic operations are first performed in parallel and the desired product called main result is selected using by a MUX. The other main product outputs are Carry out and Sum. In this regard, we present three optimized designs for reversible ALU. The basic set of arithmetic and logical operations we want to realize by the ALUs are as follows: • ADD (Addition): (A,B)→(A,A + B) • SUB (Subtraction): (A,B)→(A,A−B) • XOR (Bitwise exclusive-OR): (A,B)→ (A,A⊕ B) • AND (Bitwise AND): (A,B)→(A,AרB) • OR (Bitwise OR): (A,B)→(A,AשB) • NOP (No-operation): (A)→(A) In addition, two new reversible logic gates are suggested which are used in realization of the proposed ALU designs. The remainder of the paper is organized as follows. A briefly description of the previous designs in reversible ALU is presented in Section II. Our proposed reversible ALUs are also described in Section III. Results and comparisons of the proposed designs with the previous ones are described in Section IV, and finally Section V concludes the paper.
II.
Related Works
Related to the irreversible ALU circuit, a reversible ALU can be designed using a multiplexer to select one of the operations of ALU. Usually, in a conventional ALU, ADD, and SUB are basic arithmetic operations, while NOT, OR, AND, and XOR are basic logical operations. In a conventional ALU design that is shown in Fig. 3, arithmetic operations are first carried out in parallel and then the desired product is selected using a 4×1 multiplexer. This structure has two select lines namely S0, S1, and three data inputs which are A, B, and Cin. Researchers have studied on the various aspects of reversible ALU, such as designing of 1-bit ALU[13,14,20–22]. In Ref. [13], two reversible ALUs were proposed which contain 6 gates (2×FG, 2×FRG, 1×HNG, and 1×MRG) and have quantum cost of 24. They produce 2 garbage outputs and
require 2 constant inputs. The hardware complexity is 19α + 11β + 2δ where α, β, and δ are defined in the Appendix. These circuits produce 8 inputs and 8 outputs. Inputs of S4, S3, S0, and A propagates to the outputs. It generates 6 Boolean functions and includes 7 fixed inputs as selector.
Fig. 3
1-bit conventional ALU
In Ref. [14], two types for reversible ALUs were presented, Type1 and Type2. The Type1 which composed of 9 gates (3×PG, 2×FG, and 4×FRG) and 5 constant inputs produces 6 garbage outputs. The hardware complexity of Type1 is 19α + 16β +3δ and its quantum cost is 34. In the Type2 which also has 5 constant inputs and produces 6 garbage outputs, the quantum cost is 30 and it requires 7 gates. The hardware complexity is 19α +16β + 3δ, which is the same as Type1. This circuit needs lower gates and the quantum cost is also lower. These two circuits have 10 inputs and generate 10 outputs and also include 6 fixed inputs as selectors. In Ref. [20], a reversible 1-bit ALU was presented that is realized using four 3×3 FRGs, two FG, one HNG and proposed a reversible logic gate namely Morrison Gate (MG). This circuit includes 8 gates and its quantum cost is 35, this circuit also produces 4 garbage outputs and requires 3 constant inputs. The hardware complexity is 22α + 20β + 8δ. This circuit has 8 inputs and produces 8 outputs. Inputs of S4, S3, S0, and A propagates to the outputs. It generates 6 Boolean functions and includes 7 fixed inputs as selectors. In Ref. [21], another type of reversible 1-bit ALU was presented. This structure is the multioperations ALU based on reversible gates. It contains the reversible Control Unit (CU) and FA which are cascaded. The quantum cost of this ALU is 29 and it composed of 10 gates (3×NOT, 2×FG, 2×FRG, 2×TG, and 1×DPG) and 4 constant in-
MOALLEM et al. Optimized Reversible Arithmetic Logic Units
puts. It produces 8 garbage outputs and its hardware complexity is 15α + 13β + 8δ. This circuit has 10 inputs which includes 6 fixed inputs as selectors and generates 10 outputs. This ALU circuit can produce 8 arithmetic operations and 4 logic operations. In Ref. [22], an n-bit reversible ALU was suggested which is cascaded with reversible function generators, reversible controlled units or DXOR circuit and eight 3×3 Toffoli gates. The reversible ALU circuit performs logical operations on 2 binary numbers A and B.
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which are defined as follows: P=A, Q=(A⊕B), R=(A⊕B⊕C), and S=(AB⊕D). The block diagram of the MEB4 gate is depicted in Fig. 5(a). The quantum cost of the MEB4 gate is 5. Fig. 5(b) shows the quantum representation of the MEB4 gate which hardware complexity is 4α + β. The truth table of this 4×4 gate, MEB4, is shown in Tab. 2.
III. Our Proposed Designs for ALUs In this section, we have described our proposed designs for efficient reversible ALUs using new reversible logic gates and approaches. 1. New reversible logic gates In this study, we have presented two new reversible gates that are used in our ALUs designs. (1) Proposed 3×3 reversible gate We suggest a new 3×3 reversible logic gate named MEB3 (Moallem Ehsanpour Bolhasani) gate. The MEB3 gate generates 3 outputs that are defined as follows: P=A, Q=(A⊕B) ′ ⊕C and R= (AB⊕A ′ C). The block diagram of MEB3 gate is shown in Fig. 4(a). The quantum cost of the MEB3 gate is 4. Fig. 4(b) shows the quantum realization of this gate. The truth table of this 3×3 MEB3 gate is shown in Tab. 1. The hardware complexity and quantum cost of this gate are 3α + 2β + 2δ and 4, respectively. Tab. 1
Fig. 4
Proposed design of a 3×3 reversible MEB3 gate
Tab. 2
Truth table of a 4×4 reversible logic MEB4 gate
A
B
C
D
P
Q
R
S
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
1
0
0
1
1
0
1
0
0
0
1
1
0
0
1
0
1
0
1
1
1
0
1
1
0
0
1
0
0
0
1
1
1
0
1
0
1
1
0
0
0
1
1
1
0
1
0
0
1
1
1
1
1
1
0
1
0
1
1
0
0
1
0
1
1
1
1
0
1
1
1
0
0
1
0
0
1
1
1
0
1
1
0
0
0
1
1
1
0
1
0
1
1
1
1
1
1
1
0
1
0
Truth table of MEB3 gate
A
B
C
P
Q
R
0
0
0
0
1
0
0
0
1
0
0
1
0
1
0
0
0
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
1
0
1
(2) Proposed 4×4 reversible gate In this subsection, a new 4×4 reversible gate named MEB4 gate is presented which is shown in Fig. 5. The MEB4 gate produces four outputs
Fig. 5
Proposed design of a 4×4 reversible MEB4 gate
2. First proposed reversible ALU (Design I) The first proposed ALU design produces 6 Boolean functions: ADD, SUB, XOR, XNOR, AND, NAND, OR, and NOR. This ALU contain 6 gates (2×FG, 1×PG, 1×HNG, 1×MEB3, and 1×MEB4), it requires 8 inputs and 8 outputs. The inputs in-
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clude 3 data inputs (A, B, and Cin) and 5 fixed inputs control where defined as selectors, and two constant inputs. The quantum cost of this reversible 1-bit ALU which is shown in Fig. 6, is 21. This design generates 8 outputs: S4, S3, S0, and A which are propagated to the output, A⊕B, Sum, Cout, and Product. This circuit has 10 circuit lines and produces 6 Boolean functions on the output that are shown in Tab. 3. The inputs consist of 3 data inputs: A, B, and Cin, and 5 fixed select lines: S0, S1, S2, S3, and S4. This circuit has 2 constant inputs and 2 garbage outputs, as shown in Fig. 6.
A⊕B, Sum, Cout, and Product result. In this design, quantum cost is 33. The Boolean function results are also shown in Tab. 4. Tab. 4 Arithmetic and logic operations of the second proposed ALU (Design II) Product
S0
S1
S2
S3
S4
S5
S6
ADD
0
0
0
0
0
0
0
SUB
1
0
0
0
0
0
0
A+B
0
0
0
0
1
0
0
(A+B)'
0
0
0
1
1
0
0
A⊕B
0
0
0
0
0
1
0
A=B
0
1
0
0
0
1
0
AB
0
0
0
0
1
1
0
(AB)'
0
0
1
0
1
1
0
Slt
0
0
0
0
0
0
1
Fig. 6 The first proposed design of reversible 1-bit ALU using MEB3 and MEB4 gates (Design I) Tab. 3
Logic operations of the first proposed ALU (Design I)
Product
S0
S1
S2
S3
S4
AND and XOR
0
0
0
0
0
NAND
0
1
0
0
0
OR and XNOR
0
0
0
1
0
NOR
0
0
1
1
0
ADD
0
0
0
0
1
SUB
1
0
0
0
1
3. Second proposed reversible ALU (Design II) The quantum implementation of the second proposed reversible ALU is shown in Fig. 7. This second ALU generates 8 Boolean functions: ADD, SUB, NAND, AND, XOR, XNOR, NOR, and OR. This design produces main functions and can be working as FA and full subtractor. In addition, this ALU has 13 circuit lines with 10 outputs and 10 inputs. The inputs include of 3 data inputs (A, B, and Cin) and 7 fixed inputs as select lines (S0, S1, S2, S3, S4, S5, and S6). This circuit has 2 constant inputs and 4 garbage outputs. It generates 9 outputs: A, S0, S4, S5, and S6 which are propagated to the output,
Fig. 7 The proposed quantum realization of the second proposed reversible 1-bit ALU (Design II)
4. Third proposed reversible ALU (Design III) The main architecture of our third proposed reversible ALU, which is shown in Fig. 8, is based on the proposed design in Ref. [21]. This third proposed reversible ALU which has quantum cost of 25 includes 6 gates, 4 constant inputs and produces 5 garbage outputs and the hardware complexity of the this design is 12α + 13β + 10δ. This ALU circuit has 10 circuit lines, produces 4 arithmetic, and 8 logic operations and includes 6 inputs and 6 outputs. The inputs include of 3 data inputs (A, B, and Cin) and 3 fixed inputs as selector lines (S0, S1, and S2). The main outputs are: Func and Cout (Product 2 and Product 1 in Fig. 11). This design is totally better than the first and second
MOALLEM et al. Optimized Reversible Arithmetic Logic Units
design and also the other existing ones[13,14, 20–22].
Fig. 8 Block diagram of our third proposed reversible 1-bit ALU which is based on the design presented in Ref. [21]
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implemented. This circuit has three select control signals with a provision for realizing 8 logic operations and 4 arithmetic operations. Three control variables S0, S1, and S2 along with Cin select 12 various arithmetic logical calculations. In fact, the S2 distinguishes between arithmetic and logic operations. Next, we have proposed a new design of reversible CU. We also use a reversible FA design that was presented in Ref. [16]. Finally, the existing reversible FA circuit and our proposed reversible CU have been used to design of reversible ALU.
Fig. 10 Fig. 9 Our proposed block diagram of reversible CU which outputs are Fx, Fy, and Fz
Accordingly, the function of reversible 1-bit ALU has been designed with reversible gates, which includes the reversible logic CU and the reversible FA. The reversible CU includes A and B inputs which are altered depending on the S0, S1, and S2 values and applied as input to reversible FA based on HNG. By controlling one of the inputs to FA, different arithmetic and logic operations can be
Existing block diagram of reversible FA in Ref. [16]
(1) Proposed reversible CU The presented reversible CU includes 5 reversible gates (one FG, two RMUX1 gate, one TRG, and one 4×4 TG), and its quantum cost is 19. It needs 3 constant inputs (Cint1, Cint2, and Cint3) and produces 3 garbage outputs (G) which are depicted in Fig. 9. The function of the presented reversible ALU, the comparison of the existing 1-bit CU[21,22], and our proposed reversible CU is shown as Tab. 5. Hardware complexity of our design is 7α + 11β + 10δ.
Tab. 5 Comparison of our proposed CU with the existing ones Control unit designs The proposed design Existing design in Ref. [21] Existing design in Ref. [22]
Gate count
Constant inputs
Garbage outputs
Quantum cost
Hardware complexity
5
3
3
19
7α + 11β + 10δ
9
3
6
23
8α + 11β + 7δ
15
8
8
41
12α + 11β + 9δ
The proposed reversible 1-bit ALU has two inputs A and B, at which various operations are performed, depending on the values of S0, S1, S2, and Cin. (2) Previous reversible FA circuit FA is the fundamental structure in every ALU. Therefore, a reversible logic gate that can work as an FA will be useful to make other developed logic
circuits. The existing reversible gates that called MKG[23], TSG[24], PFAG[17], and HNG[16] can be used as an FA. Among them, the HNG has least hardware complexity which is T = 5α + 2β. The quantum cost of this gate is 6. The HNG can be considered as a reversible FA gate with inputs A, B, C, D and producing P=A, Q=B, R=A⊕B⊕C, and S=(A⊕B)C⊕AB⊕D that is shown in Fig. 1. The
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JOURNAL OF ELECTRONICS (CHINA), Vol.31 No.5, October 2014
HNG can work singly as an FA circuit when its fourth input is set to zero (D=0) as shown in Fig. 10. The HNG is also used in Ref. [9] as an FA for a reversible multiplier circuit. (3) Proposed reversible ALU The proposed reversible 1-bit ALU is shown in Fig. 11 which includes 6 gates (1×FG, 1×TG, 1×TRG, 2×RMUX1, and 1×HNG,). The total operations for this circuit are also listed in Tab. 6.
The presented reversible ALU includes 2 reversible elements, CU and FA. The proposed design of third reversible ALU has quantum cost of 25 and it includes 6 gates. It produces 4 constant inputs and 5 garbage outputs which are shown in Fig. 11. The function of the presented reversible ALU and the comparison with the other reversible 1-bit ALUs are shown in Tab. 7. The hardware complexity of our third design is 12α + 13β + 10δ, which shows a low hardware complexity.
Fig. 11 The third proposed reversible 1-bit ALU circuit
ALU operations
ALU op-code results
S2
S1
S0
Cin
F=A
Transfer A
0
0
0
0
F=A+1
Increment A
0
0
0
1
F=A+B
Addition
0
0
1
0
posed designs of ALUs. The 3×3 MEB3 gate has quantum cost of 4 and hardware complexity of T = 3α + 2β + 2δ. It can be used to design any reversible multiplexer and can be produced equation of d-latch in sequential circuit. Also, the 4×4 MEB4 gate has quantum cost of 5 and hardware complexity is T = 4α + β. Evaluation of the proposed designs for ALUs is described as follows.
F=A+B+1
Add with carry
0
0
1
1
1. Design I
F=A–B–1
Sub with borrow
0
1
0
0
F=A–B
Subtraction
0
1
0
1
F=A–1
Decrement A
0
1
1
0
F=A or B
Transfer A or B
0
1
1
1
F=A ∨ B
OR
1
0
0
0
F=A ⊕ B
XOR
1
0
1
1
F=A ∧ B
AND
1
1
0
0
F=A'
Complement A
1
1
1
1
Tab. 6 Total ALU operations of our third reversible ALU for Fig. 11: arithmetic and logical operations
IV. Evaluation Results In this section, evaluation of the proposed reversible ALUs with respect to the existing designs is described. Tab. 7 lists the characteristics of the presented circuits and the existing counterparts. The proposed reversible gates can be used to pro-
The quantum cost of the first proposed reversible ALU is 21. It requires two constant inputs and produces two garbage outputs and hardware complexity is 15α + 6β + 2δ. This design generates 8 inputs and 8 outputs. Also, inputs of S3, S0, A, and S4 propagated to the outputs, XOR, Sum, and Cout. It generates 6 Boolean functions and requires 7 fixed inputs as selectors and 6 gates. This ALU composed of 8 outputs: S0, S3, A, and S4 propagated to the output, A⊕B, Sum, Cout, and Product output. It includes 10 circuit lines. The inputs consist of 3 data inputs (A, B, and Cin) and 5 fixed select input lines (S0, S1, S2, S3, and S4). The presented first design is better than previous circuits[14,20–22] in terms of the number of gates, constant inputs, garbage outputs, quantum cost, and the hardware complexity. This design is better than the existing counterparts[13,14, 20–22] in term of the
MOALLEM et al. Optimized Reversible Arithmetic Logic Units
hardware complexity. The proposed third design is better than the existing circuit[13] in terms of quantum cost and the hardware complexity. 2. Design II The quantum cost of the second proposed reversible ALU is 33. It requires 2 constant inputs and produces 4 garbage outputs and hardware complexity is 19α + 11β + 8δ. This design generates 10 inputs and 10 outputs. All inputs of S3, S0, A, and S4 propagated to the outputs, and also XOR, Sum, and Cout. It generates 8 Boolean functions which is better than previous works in produces logical calculation. It includes 7 fixed inputs as selectors and 8 gates. It has 13 circuit lines. The inputs include of 3 data inputs (A, B, and Cin) and 7 fixed inputs as select input lines (S0, S1, S2, S3, S4, S5, and S6). The A, S0, S4, S5, and S6 propagated to the output, Sum, Cout, Product output. The presented second circuit is better than previous circuits[20–22] in terms of the number of gates, constant inputs, garbage outputs, quantum cost and the hardware complexity. The proposed design is better than the existing circuits[13] in produced Boolean operations. The design is better than the existing circuit[14] in terms of the constant inputs, garbage outputs, hardware complexity, and the produced Boolean operations. 3. Design III The quantum cost of the third proposed reversible ALU is 25. It requires 6 gates, 4 constant inputs and produces 5 garbage outputs. The hardTab. 7
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ware complexity is 12α + 13β + 10δ that is very low. This design consists of 10 circuit lines and includes 6 fixed inputs as selectors and produces 12 logical calculations. It can be produce 4 arithmetic functions and 4 logical operations. The inputs composed of 3 data inputs (A, B, and Cin) and 3 fixed inputs as select lines (S0, S1, and S2). In this design, the inputs of A, B, and Cin reproduced onto the outputs. The presented third design is better than previous circuits[14,21,22] in terms of the number of gates, constant inputs, garbage outputs, quantum cost and the hardware complexity. We achieved an efficient design of reversible ALUs is better than the existing counterparts [13,14,20–22] in term of the hardware complexity. The proposed third design is better than the existing circuit[13] in terms of the hardware complexity and produced logical and arithmetic operations. This design is better than previous design[20] in terms of the number of gates, quantum cost, hardware complexity, produced Boolean functions, and arithmetic operations. Comparison results show that our designs are better than the existing designs[13,14,20,21], in term of number of gates, constant inputs, garbage outputs, quantum costs, and hardware complexity. Also, the proposed designs can produce all Boolean functions. Among them, our third proposed reversible 1-bit ALU is more efficient than the other designs and existing circuits. The comparison of the proposed designs with the existing circuits[13,14,20–22] is given in Tab. 7.
Total comparative results for different reversible 1-bit ALU circuits
Designs
Gate count
Constant inputs
Garbage outputs
Quantum cost
Hardware complexity
Number of arithmetic and logical* function results
This study: Design I
6
2
2
21
15α + 6β + 2δ
6
This study: Design II
8
2
4
33
19α + 11β + 8δ
8
This study: Design III
6
4
5
25
12α + 13β + 10δ
4+8*=12
Existing design in Ref. [13]
6
2
2
24
19α + 11β + 2δ
6
Existing design in Ref. [14]
7
5
6
30
19α + 16β + 3δ
6
Existing design in Ref. [20]
9
3
4
35
22α + 20β + 8δ
8
Existing design in Ref. [21]
10
4
8
29
15α + 13β + 8δ
8+4*=12
Existing design in Ref. [22]
22
12
13
53
16α + 16β + 7δ
8+4*=12
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In Ref. [13], two designs for reversible ALUs were presented. These includes 6 gates, have quantum cost of 24 with 2 garbage outputs and 2 constant inputs. The hardware complexity is 19α + 11β + 2δ. These circuits generate 8 inputs and 8 outputs. All inputs of S3, S0, A, and S4 propagated to the outputs. It generates 6 Boolean functions and includes 7 fixed inputs as selectors. In Ref. [14], two types for reversible ALUs were proposed. In the first design, quantum cost is 34. It includes 9 gates, 6 constant inputs and produces 8 garbage outputs. The hardware complexity is 19α + 16β + 3δ. In the second design, quantum cost is 30. It includes 7 gates, 5 constant inputs and produces 6 garbage outputs. The hardware complexity is 19α + 16β + 3δ. This design is more efficient than first design. We evaluated the first design which was realized by DPG and YAG. In Ref. [20], one reversible ALU was proposed that is realized based on four 3×3 FRGs, two Feynman gate, one HNG and suggested a reversible logic gate namely MG (shown in Fig. 6). It composed of 8 gates and has quantum cost of 35 which produces 4 garbage outputs and requires 3 constant inputs. The hardware complexity of this circuit is 22α + 20β + 8δ. This design produces 8 inputs and 8 outputs. Inputs of S3, S0, A and S4 propagated to the outputs. It generates 6 Boolean functions and includes 7 fixed inputs as selectors. In Ref. [21] another new type of reversible 1-bit ALU was proposed. This structure is the multi-operations ALU using reversible logic gates. It includes the reversible CU and the reversible FA gate. The reversible CU and the FA circuit are cascaded. These units are depicted in Figs. 8 and 9. It composed of 10 gates and has quantum cost of 29 which produces 8 garbage outputs and requires 4 constant inputs. The hardware complexity of this circuit is 15α + 13β + 8δ. This design produces 12 logical calculations. In Ref. [22], n-bit reversible ALU was proposed that is realized by reversible function generators, reversible controlled units based on DXOR circuit by Not and Cnot gates and different 3×3 Toffoli gates. This circuit with (13n+6) input/output uses (7n) NOT gates, (12n) 3×3 Toffoli gates and (n) 4×4 Toffoli gates. There are a total of 13n reversible gates (excluding NOT gates) and (12n+1)
garbage outputs. Next, we have calculated this circuit as one bit (n=1). This structure composed of 22 gates and has quantum cost of 53 which produces 13 garbage outputs and requires 12 constant inputs and 19 circuit lines. The hardware complexity of this circuit is 16α + 16β + 7δ. This design produces 12 logical calculations. The total comparison results are shown in Tab. 7. It clearly shows that proposed designs of reversible 1-bit ALU requires less number of gates, constant inputs, and garbage outputs. It also reduces quantum cost quantum and hardware complexity. Also, our designs could handle total 16 arithmetic and logical operations.
V.
Conclusion
In this paper, new architectures are proposed for reversible 1-bit ALU. The proposed designs are more cost effective than the existing designs. Also, arithmetic and logical unit using reversible CU has been presented. We have compared these proposed designs with the existing ones[13,14,20–22] in terms of the number of reversible gates, garbage outputs, quantum cost, constant inputs, arithmetic-logical operations, and hardware complexity, which can be used for low power applications. Arithmetic and logical unit using our proposed reversible CU has improved over previous designs[21,22]. In fact, three different designs for reversible ALUs are presented in this paper. In first design, the proposed ALU performs total 6 logical operations. In second design, the proposed ALU handles total 8 arithmetic and logical operations. In third design, the proposed ALU performs total 16 logical operations. The third type proposed ALU composed of 16 operations, including 4 arithmetic and 12 logical calculations. The first type proposed reversible ALU is better than the existing designs in Refs. [14,20–22] in term of quantum cost. It is the most optimized design in terms of gates count, garbage outputs, constant inputs and the hardware complexity with compared with the existing ones. The second type proposed reversible 1-bit ALU circuit is better than the existing designs in Refs. [14,20–22] in terms of constant inputs and garbage outputs. It could handle total 8 arithmetic and logical calculations which is better than the existing designs in Refs.
MOALLEM et al. Optimized Reversible Arithmetic Logic Units
[13,14]. This design is better in term of number of gates than the existing designs in Refs. [21,22]. The hardware complexity of this design is better than the existing circuits in Refs. [14,20]. The third type proposed ALU can perform total sixteen operations including 4 arithmetic and 12 logical operations that is better than the existing designs in Refs. [13,14,20–22]. It is better than the existing ones in Refs. [13,14,20–22] in term of hardware complexity and better than the Refs. [14,20– 22] in term of quantum cost. The third design is better than previous designs in Refs. [14,21,22], in terms of the number of gates, constant inputs, garbage outputs, quantum cost and the hardware complexity. The design is better than the existing circuit in Ref. [13] in terms of the hardware complexity and produced logical and arithmetic functions. This design is better than previous design in Ref. [20] in terms of the number of gates, quantum cost, hardware complexity, produced Boolean functions, and arithmetic functions. The number of gates in this circuit is also better than Refs. [20–22]. This ALU is better in terms of constant inputs and garbage outputs than the existing circuits in Refs. [14,22]. The presented reversible ALU has great significance for realizing of a reversible divider circuit.
APPENDIX A Reversible logic is one of the major goals in modern digital circuit design having promising applications in quantum computing, optical computing, cellular automata, low power VLSI, and nanotechnology. In this section we present some basic concepts and ideas related to reversible logic. Quantum realization of some popular reversible logic circuits has been shown in this section. A.I. Reversible logic If there is unique correspondence between inputs vector and outputs pattern in function G (G has m input and m output), then function of G is reversible. So, the inputs vector is uniquely, determinable from outputs pattern[2]. There are some important parameters in designing an efficient reversible logic circuits including: Gate count The number of gates used to imple-
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ment the circuit. Garbage output If the output of a reversible gate is used nowhere of a reversible circuit, this output is named by garbage output. Constant input In reversible logic circuits constant inputs refer to inputs which is permanently 1 or 0. Quantum cost The number of 1×1 or 2×2 reversible logic gates, required to make the reversible gate because the quantum logic gates larger than 2×2 are not directly realizable in the quantum technology and also 1×1 reversible logic gate is called NOT gate which has no quantum cost[15]. Hardware complexity The number of gates (AND, NOT, and XOR gates) used to synthesize the given logical function. To compute the hardware complexity of the proposed design, let: α = A two input XOR gate calculation β = A two input AND gate calculation δ = A NOT gate calculation T = Total logical calculation In synthesis of reversible circuits, following requirements should be considered as possible[2]: • Minimum number of garbage outputs, • Minimum number of constant inputs, • Minimum hardware complexity, • Minimum number of gates, • Minimum quantum cost of the circuit. A.II. Controlled-V and V+ Gates The V operation is square root of NOT gate and the Controlled-V+ gate is inverse of square root of NOT gate as shown in Fig. A.1. When controlled-V gate and Controlled-V+ gates are in successive order then, it results in identity matrix. If controlled-V gates are connected in series, acts as NOT gate. On the other hand, in the Controlled-V+ gate when the control signal A is zero, then the qubit B will pass through the controlled part unchanged, i.e., we will have Q=B and if A=1 then the unitary operation V + = V–1 is applied to the input B, i.e., Q=V+(B). In the controlled-V gate, as well as, when the control signal A is zero, then the qubit B will pass through the controlled part unchanged, i.e., we will have Q=B. Also, the Square Root of Not (SRN) gates utilize the single operators to generate reversible logic calculation when a control line is set at one.
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The controlled-V and the Controlled-V+ gates are the two types of SRN gates[25]. The quantum cost of 1×1 fundamental reversible logic gate namely Not gate is zero and the quantum cost of each of 2×2 fundamental reversible gate is one[15,25]. When a controlled-V gate and Controlled-V+ gate are activated, they work as an identity and the quantum cost of the integrated qubit gate is 1. The V gates, named SRN, have properties expressed form Eqs. (A.1) and (A.2).
References [1]
[2]
[3]
[4]
Fig.A.1 Quantum implementation of integrated qubit gates
[5]
V=
i + 1 ⎪⎧⎪ 1 −i ⎪⎫⎪ ⎪⎧⎪0 1⎪⎫⎪ ⎨ ⎬=⎨ ⎬ 2 ⎪⎪⎩−i 1 ⎪⎪⎭ ⎪⎪⎩1 0⎪⎪⎭
1 2
(A.1)
[6] [7]
V +× V + = NOT, V× V + = Ι, V× V = NOT (A.2)
The quantum cost of a reversible circuit to be computed by counting the number of 2×2 reversible logic gates such as Feynman gate, V and V+ gates[15–19,25]. Two types of quantum implementation of these two integrated qubit gates are shown in Fig. A.2. The quantum cost of these circuits is 1[2,15,20–22,25].
[8]
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Fig. A.2 Quantum equivalent implementation of two integrated qubit gates
Fig. A.2 represents the integrated qubits gates, which will serve as another fundamental gate used in the Eqs. (A.1) and (A.2)[25]. In this case, a CNOT or a single NOT gate with the controlled-V or Controlled-V+ gate share the same input and output lines, and are in series. These are important gates can be used to reduce the quantum cost of reversible circuits.
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