Reversible Arithmetic Logic Unit for Quantum Arithmetic

Reversible Arithmetic Logic Unit for Quantum Arithmetic Michael Kirkedal Thomsen, Robert Glück and Holger Bock Axelsen DIKU, Department of Computer Science, University of Copenhagen, Denmark E-mail: [email protected], [email protected], [email protected] Abstract. This paper presents the complete design of a reversible arithmetic logic unit (ALU) that can be part of a programmable reversible computing device such as a quantum computer. The presented ALU is garbage-free and uses reversible updates to combine the standard reversible arithmetic and logical operations in one unit. Combined with a suitable control unit, the ALU permits the construction of an r-Turing complete computing device. The garbage-free ALU developed in this paper requires only 6n elementary reversible gates for the 5 basic arithmetic-logic operations on two n-bit operands. This remarkable low resource consumption was achieved by generalizing the V-shape design first introduced for quantum ripple-carry adders and nesting multiple V-shapes in a novel integrated design. This paper shows that the realization of an efficient reversible ALU for a programmable computing device is possible and that the V-shape design is a very versatile approach to the design of quantum networks.

Reversible ALU for QA

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1. Introduction Since the earliest programmable computing devices, two main combinatorial units are distinguished in a computer: the control unit and the arithmetic-logic unit (ALU). The former derives from instructions the control signals that determine the operation of the ALU, which then combines the operands of the instruction to produce a result. Which instruction is selected next by the control unit may depend on the result calculated by the ALU. This feedback from the ALU to the control unit has the far-reaching consequence for the computations that can be programmed. The ALU is central for the design of the instruction set of a programmable computing device. The functionality provided by the ALU determine the possible set of data instructions (control instructions, the other part of an instruction set, are determined by the operation of the control unit). The basic structure of a stored-program computer, also known as von Neumann architecture, has remained remarkably stable since its inception in the 1940s [1] despite the rapidly changing technology used for its implementation (e.g., relays, vacuum tubes, transistors). This provides ample justification to study this fundamental scheme in the context of reversible computing [2] and reversible logic as realized today, among others, by quantum gates [3]. 1.1. The Quantum Leap Reversible logic is a core part of the quantum circuit model: A reversible logic gate has a corresponding quantum version, whose effect is completely defined by the truth table for the classical version. This means that reversible circuits are also quantum circuits, and as such the hope is that lessons from reversible circuit design may contribute to improving quantum circuits. The generic approach to implementing a function f in a quantum circuit is to implement the quantum operation Uf (|xi|yi) = |xi|y ⊕ f (x)i (where ⊕ is bitwise exclusive-or). If we instantiate |yi to |0i then applying Uf yields |xi|f (x)i. This is essentially the quantum equivalent of the Bennett trick, originally used for Turing machines [4]. However, in practice it has become clear that for many important classes of functions the Bennett trick does not provide a satisfactory solution, and that much better solutions are available. There is thus a good case to be made for studying reversible operations on their own terms, and not just as embedded version of classical (irreversible) operations. The same is true in quantum computing, and the circuits presented here takes this philosophy. The arithmetic and logic operations described below form a class where we can avoid naïvely using the Bennett trick when implementing quantum (reversible) embeddings of classical functions. So, while we still implement reversible versions of irreversible operators, we can do so with markedly better embeddings than those provided by the generic approach.

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Reversible ALU for QA A B

A A⊕B

A B

A A−B

A B

A A+B

Control A B

Control A Result

Figure 1. Reversible circuits each implementing a single function and the desired reversible controlled circuit that conditionally performs one of several functions.

1.2. Control Structure in Reversible Logic In this paper we focus on the design of a reversible ALU that can be part of a programmable reversible computer. An ALU is a multi-functional circuit that conditionally performs one of several possible functions on A and B depending on a control input. In contrast to a conventional reversible circuit that unconditionally performs a function on two operands A and B, for example, binary addition (+) or bitwise exclusive-or (⊕). This is illustrated abstractly in Fig. 1, where several singlefunction circuits are shown on the left-hand side and an ALU capable of performing the same functions on the right-hand side. One of the operands is preserved in the output (here, A) because the circuits are based on reversible logic. For the same reason, the control is not changed by the ALU and passed through to the output. The addition of control to a reversible circuit is an essential and necessary transition to form the next, higher level of control in a reversible computing system that integrates many elementary controlled gates (e.g., Fredkin-, Feynman-, Toffoli-gates) into a more complex controlled system. This can be compared to the addition of control to an elementary logic operation on a lower system level, such as ⊕, to obtain an elementary controlled logic gate, say a Feynman- or Toffoli-gate, except that the design of the functionality and control of an entire unit is more complex. The integration of multiple functions into a single circuit comes at the expense of logical depth and the number of gates. It is therefore important for the design of a reversible ALU to maximize performance and to minimize resource costs, and on the other hand to identify a set of reversible data instructions that is expressive for programming while making it easy to build the device. Our main goal is, firstly, to have a simple design and, secondly, to reduce the logic depth and number of gates of the reversible ALU, rather than to provide a large set of data instructions. Nevertheless, the ALU presented in this paper, combined with a suitable control unit, permits the construction of a (in principle) r-Turing-complete and fully programmable reversible computing device [5]. The complete design of a simple, but versatile reversible ALU is developed in this paper. The number of reversible logic gates required by our design is linear in the size of the two operands. An n-bit ALU with 5 basic arithmetic-logic instructions requires 6n − 2 elementary reversible logic gates (Fredkin-, Toffoli- and Feynman gates, [6]). As

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Reversible ALU for QA

an example, an ALU with 16-bit operands requires only 94 elementary reversible gates. The main result shown in this papers is that the addition of control and the combination of multiple functions into an ALU does not necessarily require large number of gates, ancillae, and garbage and the ALU can be easily extended to support more non-basic arithmetic operations. The very low resource consumption was achieved by generalizing the V-shape circuit design introduced by Barenco et al. [7] for quantum ripple-carry addition circuits and optimized by Cuccaro et al. [8] to other functions, and by nesting multiple V-shapes into a single, integrated reversible circuit design. This also demonstrates the generality and potential of the V-shape design for quantum circuit design. It appears that this rarely used design principle is much more general than previously thought. This confirms that many familiar design principles from Boolean logic circuits are not necessarily suited for quantum logic circuits. This paper is organized as follows. After reviewing modular arithmetic (Sect. 2), the binary number representation, and the V-shape design of quantum addition circuits (Sect. 3), the main design choices for a reversible ALU are investigated (Sect. 4). The reversible data instructions is introduced and our novel ALU design is stepwise developed (Sect. 5). Finally, we discuss related work (Sect. 6) and present our conclusions (Sect. 7). We assume that readers are familiar with the basics of reversible logic networks, e.g., as presented by Barenco et al. [6]. 2. Modular Arithmetic In this section we briefly review reversible modular arithmetic with binary numbers. We use reversible updates [9, 5] to ensure the reversibility of the operations. 2.1. Modular Addition An immediate problem to the design of a reversible binary adder is that addition is not an injective function. The sum A + B does not uniquely determine the operands A and B. However, addition is injective in one of the operands, which means that preserving A or B is sufficient to uniquely determine the other operand from the sum. The definition of addition for a reversible adder then takes the form of a reversible update: (A, B) 7→ (A, B + A) . In an implementation of the adder that must rely on a representation using a finite size of integers, the sum may overflow the largest representable number. To preserve reversibility of the adder, we use n-bit modular addition def.

B +n A = (B + A) mod 2n , and thus define the reversible update as (A, B) 7→ (A, B +n A) .

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Reversible ALU for QA 2.2. Modular Subtraction We can easily define the reversible update for modular subtraction as (A, B) 7→ (A, B −n A) .

When using binary numbers modular subtraction is closely related to modular addition and bitwise negation and we have the following equations: B −n A = B +n A +n 1 = B +n A −n 1 , where A is the bitwise negation of A. The first equation is actually the usual way of calculating subtraction in a conventional ALU. This is, however, not a suitable approach for a reversible operation. To define modular subtraction as a reversible update we know that the updating value, A, must be kept unchanged and both of these require a bitwise negation of A that must be uncomputed. Using the two equations we can, however, redefine modular subtraction as B −n A = 0 −n (A −n B) = 0 +n A −n B −n 1 = A +n (B +n 1) −n 1 = B +n A . This equation leaves A unchanged while only updating B. It is worth noticing that modular subtraction is the inverse operation of modular addition (such that B = (B +n A) −n A) as one would expect. 2.3. Modular Negative Using conventional subtraction it is possible to calculate both the positive and negative difference (B − A and A − B) between two numbers. But using the reversible update for subtraction (and A must be preserved) it is only possible to calculate the first of these. We will therefore define a second modular subtraction (modular negative), using one of the previous equations, as A −n B = A +n B +n 1 with the reversible update (A, B) 7→ (A, A −n B) . Notice, that opposite to modular subtraction which is the inverse operation of modular addition, modular negative is its own inverse as one would expect of a value negate (and thus the name). In the special case where A is equal to zero this will be a negative of B.

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Reversible ALU for QA G S0 A0 G S1 A1

Full-Adder Full-Adder

Bn−1 An−1 0

Full-Adder

Ai ⊕ Bi Ai Si Ci+1

Bi Ai 0 Ci

Cin B0 A0 0 B1 A1 0

G Sn−1 An−1 Cout

Figure 2. The left figure shows an implementation of full-adder in reversible logic [10] while the right shows an n-bit adder using the conventional ripple-carry principle.

3. Reversible Adders Let Ai denotes the i’th bit of an n-bit binary number A (0 ≤ i < n). The i’th bit of the n-bit sum and the carry-over sequence are then calculated by the two conventional formulas, Si

= Ci ⊕ Ai ⊕ Bi ,

Ci+1 = Ci · (Ai ⊕ Bi ) ⊕ Ai · Bi .

(1) (2)

3.1. Ripple-carry Adder in Reversible Logic Early implementations of binary adders using reversible logic, such as [10] (Fig. 2), suffered from the generation of garbage bits (n in the case of an n-bit ripple-carry adder). In fact, there is no reversible realization of a 1-bit full-adder that can avoid an extra garbage bit because the desired function (Ci , Ai , Bi ) 7→ (Si , Ai , Ci+1) is non-injective. Therefore, the conventional method of using such a 1-bit full-adder as the basic block for building n-bit adders is not well suited for implementing reversible adders. 3.2. The Reversible V-shaped Ripple-carry Adder The novel approach to ripple-carry adders introduced by Vedral et al. [7] (VBE-adder ) solves the problem with generation of garbage. The approach is based on the observation that the calculation of Ci+1 and Si are independent; see (1) and (2). It is therefore possible to calculate the carry-over bit (C1 , ..., Cn ) before calculating the sum bits (S1 , ..., Sn ). Three functions are defined for this purpose: the sum function, which calculates sum Si while leaving Ci and Ai unchanged, (Ci , Ai , Bi ) 7→ (Ci , Ai , Si ) ,

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Reversible ALU for QA Ci Ai Bi 0

Ci Ai Ai ⊕ Bi Ci+1 Majority Circuit

Unmajority Circuit

Ci Ci Ai Ai Si Bi 0 0 Sum calculation Circuit

Figure 3. Bit-slice of the VBE-adder.

Ci ⊕ Ai Ci+1 Ai ⊕ Bi

Ci Ai Bi Majority Circuit

Ci Ai Si Unmajority and Sum Circuit

Figure 4. Bit-slice of the CDKM-adder.

Ci Ai Bi Majority circuit

Ai Bi ⊕ (Ai ⊕ Bi )Ci Ci Ci+1 Ai Si Ai ⊕ Bi Unmajority and sum circuit

Figure 5. Bit-slice of the VanRentergem-adder.

the majority function, which calculates the carry-out Ci+1 and a temporrary Ai ⊕ Bi , (Ci , Bi , Ai , 0) 7→ (Ci , Ai ⊕ Bi , Ai , Ci+1 ) , and the unmajority function, which is the inverse of the majority function, and can therefore undo the calculation of the majority function. A reversible implementation of these three injective functions is shown in Fig. 3. When reading the three circuits from the left to the right, they form a 1-bit adder circuits (called a bit-slice) that can be duplicated to an n-bit adder. The net effect of the bit-slice is to calculate Si . All other inputs, Ci, Ai , and the ancilla 0, are unchanged in the output. Note that Ci+1 is available right after the majority circuit, and here the next majority circuit can use it as carry-in to calculate the next carry-out Ci+2 , and so forth. The task of the unmajority circuit following the majority circuit is only to restore the original input and to pass it to the sum circuit, which then calculates the final Si . An n-bit modular adder (Fig. 6) can be implemented by a forward ripple of majority circuits (calculates the carry-over bits) followed by a backward ripple of a pair of unmajority and sum circuits (calculates the sum bits). When the last carry-out Cn is available at the end of the forward ripple, the calculation proceeds upward and calculates the sum bits in reverse order (we consider optimizing this below). We call this structure of a forward ripple and a backward ripple a V-shape. The n-bit modular adder in Fig. 6 has n+1 ancillae bits, but no garbage bits. There is no carry-out because

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Reversible ALU for QA SUM

UNMAJ SUM

UNMAJ

MAJ SUM

UNMAJ

MAJ

An−1 Bn−1 0

MAJ

Cin A0 B0 0 A1 B1 0

Cin A0 S0 0 A1 S1 0 An−1 Sn−1 0

Figure 6. n-bit V-shaped ripple-carry of the VBE-adder. MAJ is the majority circuit, UNMAJ is the unmajority circuit, and SUM the is the sum calculation circuit. An obvious optimization is to remove the majority and unmajority circuits of the most significant bit. This has not been done in this figure for clarity, but will be used in the ALU.

it is a modular adder and instead Cin is returned unchanged (we discuss the use of a carry-in later). The CDKM-adder It is obvious that the VBE-adder is not optimal in the number of gates, logic width and logic depth. Firstly, the unmajority circuit and the sum circuits can be merged into a combined unmajority-and-sum circuit and secondly, no ancillae are locally required, thereby reducing the logic width. Two n-bit adders based on this optimization were suggested by Cuccaro et al. [8]. The first variant, which we call the CDKM-adder (Fig. 4), has a lower complexity in the number of gates and the logical depth when compared to the VBE-adder. The second variant, which we call the improved CDKM-adder, has a lower logical depth at the cost of more gates than the CDKM-adder (for a detailed description of the second variant and further improvements, see [11, 12]). Both n-bit modular adders need only a single ancilla. The costs of these adders are summarized in Tab. 1. The VanRentergem-adder Another improvement is the VanRentergem-adder [13, 14], which has the lowest gate costs compared to the VBE-adder and the two CDKMadders. Here two gates (a Feynman and a Toffoli gate) are replaced with a single Fredkin gate. This changes the temporary value, but this is not relevant for the output since the intermediate value will be uncomputed inside the adder. Comparison The VanRentergem-adder has the lowest gate count of the V-shape adders. It is remarkable that is uses only 4n gates for an n-bit modular adder. The improved CDKM-adder has a shorter delay than the VanRentergem-adder, but uses almost twice as many gates. The costs of all four garbage-free V-shape adders are summarized in Tab. 1.

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Reversible ALU for QA

Table 1. Costs of garbage-free reversible n-bit adder-circuits. These costs are calculated with the use of the V-shape ripple using n bit-slice blocks. Gate cost Ancilae bits Circuit width Delay in gates

VBE [7] 8n n+1 3n + 1 5n + 3

CDKM [8] 6n 1 2n + 1 5n + 1

Imp. CDKM [8] 7n 1 2n + 1 2n + 7

VanRentergem [14] 4n 1 2n + 1 3n + 1

3.3. Two’s Complement Numbers Modular addition is extendable to negative integers using two’s complement numbers, today’s standard binary number representation [15]. Two’s complement numbers are n-bit binary numbers where the lowest value, 0, has been shifted to −2n−1 . Modular addition on n-bit two’s complement numbers is then defined by adjusting the values by adding and subtracting 2n−1, def.

n−1 A +tc ) mod 2n ) − 2n−1 . n B = ((B + A + 2

One of the reasons that two’s complement numbers are much used is that the order of the numbers are unchanged and, thus, binary adders circuits can be used for addition. This does not change for modular addition and all the above adders can implement a reversible adder for two’s complement numbers. The formulas for modular subtraction and negative from Sect. 2 are also valid for two’s complement numbers and when having both positive and negative numbers negation can be more useful. 4. The Arithmetic Logic Unit In a conventional design of an ALU (Fig. 7), the arithmetic-logic operations are first performed in parallel and then the desired result is selected by a multiplexer - a circuits that chooses one out of more inputs depending on a control bit. All other results are lost. This destructive approach is suitable for conventional Boolean circuits, but not for reversible circuits where we wish to have no garbage generation. It is therefore necessary to develop a new design for a reversible ALU. We examine the basics of the parallel and the serial design approach for a reversible ALU in this section. 4.1. Parallel ALU Design A parallel design of a reversible ALU (Fig. 8) follows a strategy similar to the conventional ALU. Using two reversible multiplexers the input is first directed to the desired arithmetic-logical operation and afterwards reversibly directed to the result line. Ancillae bits are used for the rest of the logical operations and it is important that the operations are organized such that the ancillae bits are unchanged over the operations.

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Reversible ALU for QA Control Multiplex

A B

Result

Figure 7. Design of a conventional ALU. The operations are done in parallel and a multiplexer selects the desired result depending on the control signal. Control Fredkin Multiplex

0 0 0

Fredkin Multiplex

A B

Control A Result 0 0 0

Figure 8. Design of a parallel reversible ALU. As in the conventional ALU the operations are done in parallel, but two multiplexers are needed to direct the input through the desired operation to the output.

Control A B

Control A Result

Figure 9. Design of a sequential reversible ALU. The control ensures that only the desired operation is performed.

This design looks much like the conventional ALU. It is simple to design and understand because it consists of independent subcircuits. As it is parallel, it is expected to be fast, but this comes at the expense of a very large number of ancillae bits and a large logic width. 4.2. Sequential ALU design Another option is to use a sequential design. The logical operations are performed on the same lines and, instead of using the control to select the desired result after calculating all operations in parallel, the desired operation in a series of operations is turned on by the control (Fig. 9.) It is not always trivial how this is done. However, many operations (like ⊕) can be implemented with one gate and an extra control can therefore be added to this gate. A serial ALU can be expected to be slower and more complex than a parallel ALU, but it

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Reversible ALU for QA

will use less ancillae bits. We will however see that a ALU with few arithmetic and logical operations can benefit from a sequential design. Of course, the reduced number of ancillae bits is also consistent with our goal of having a minimal design. An ALU design for more complex arithmetic instructions may benefit from a combination of the parallel and sequential designs, but as we will see the depth of our sequential ALU design is only a small constant higher than the binary adders. 5. An Arithmetic Logic Unit using the V-shape This section presents the design of a reversible n-bit ALU based on a controlled and nested V-shape with a sequential arrangement of operations. First, we introduce the basic set of operations and then develop the ALU design step-by-step starting from a reversible binary modular adder. 5.1. Basic Operations The basic set of reversible arithmetic and logic operations that we intend to implement by the ALU is small, but expressive. Later we will see that the final ALU design allows more than these five operations. Each operation has the format of a reversible update and has two n-bit arguments A and B: Modular addition (ADD): Modular subtraction (SUB): Modular negative (NEG): Bitwise exclusive-or (XOR): No-operation (NOP):

(A, B) 7→ (A, B +n A) (A, B) 7→ (A, B −n A) (A, B) 7→ (A, A −n B) (A, B) 7→ (A, B ⊕ A) (A, B) 7→ (A, B)

5.2. Choice of Binary Adder The backbone of the ALU design is an n-bit binary adder. There are two interesting candidates: (1) the improved CDKM-adder because it has the smallest delay and (2) the VanRentergem-adder because is has the smallest gate count. We choose the VanRentergem-adder because it has useful properties compared to the optimized CDKM-adder when it comes to the implementation of exclusive-or and no-operations in the ALU. We will return to this point when we extend the ALU with exclusive-or and no-operation. The used VanRentergem-adder is slightly improved by using only the sum circuit in the most significant bit-slice. Applying first the majority and then the unmajority circuit implements the identity function and can thus be removed for modular arithmetic. This improvement can be applied to all V-shaped adders. The initial design is shown in Fig. 10, where the carry-in is set to 0.

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Reversible ALU for QA

A0 B0

0

0 A0 R0

A1 B1

A1 R1

An−2 Bn−2

An−2 Rn−2

An−1 Bn−1

An−1 Rn−1 Figure 10. The n-bit VanRentergem-adder is the backbone of the reversible ALU design. At this stage, the ALU can only perform the operation ADD.

5.3. Subtraction and Negation The definition of modular subtraction that we introduced in Sect. 2.2 makes use of two bitwise negations and one modular addition. By extending the design with two arrays of Feynman gates at each side of the VanRentergem-adder (the light blue boxes in Fig. 11), bitwise negation can be performed on input B and output R by setting the controls CN egA and CN egR to TRUE, respectively. Otherwise, they are not changed by the two Feynman-gate arrays. Thus, if both controls CN egA and CN egR are TRUE, the extended ALU in Fig. 11 performs B −n A; otherwise, B +n A. Using the definition of modular negative, we need a bitwise negation of B and the addition of 1. Bitwise negation of B has already been added to the ALU. The ancilla bit that is used in the adder (see the top of Fig. 10) can be used as carry-in to the adder. Setting the carry-in to TRUE performs an addition by 1. Thus, if the controls CN egB and CCarryIn are both TRUE, the extended ALU in Fig. 11 calculates A−n B. We therefore have an ALU extended with operations for modular subtraction and negation in Fig. 11. 5.4. Bitwise Exclusive-Or The bitwise exclusive-or (XOR) is an elementary operation in reversible logic and its reversible update is also called a controlled NOT, but implementing it in the extended ALU is more involved. We need to ensure that the binary adder does not interfere. Recall that the sum is defined by S = A ⊕ B ⊕ Cin .

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Reversible ALU for QA CN egR CCarryIn CN egB

CN egR CCarryIn CN egB

A0 B0

A0 R0

A1 B1

A1 R1

An−2 Bn−2

An−2 Rn−2

An−1 Bn−1

An−1 Rn−1

Figure 11. Reversible ALU with addition, subtraction and negation. Subtraction and negation is added with a blue line. Can perform the operations ADD, SUB, and NEG.

CCarryXor CN egR CCarryIn CN egB

CCarryXor CN egR CCarryIn CN egB

A0 B0

A0 R0

A1 B1

A1 R1

An−2 Bn−2

An−2 Rn−2

An−1 Bn−1

An−1 Rn−1

Figure 12. Reversible ALU with addition, subtraction, negation and exclusive-or. Exclusive-or is added with the green line. (ADD, SUB, NEG, and XOR.)

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Reversible ALU for QA CAxorB CCarryXor CN egR CCarryIn CN egB

CAxorB CCarryXor CN egR CCarryIn CN egB

A0 B0

A0 R0

A1 B1

A1 R1

An−2 Bn−2

An−2 Rn−2

An−1 Bn−1

An−1 Rn−1

Figure 13. Reversible ALU with addition, subtraction, negation, exclusive-or, and no-operation. No-operation is added with the magenta line. (ADD, SUB, NEG, XOR, and nop.)

This means that the binary adder calculates A ⊕ B, if we make sure that the second exclusive-or (⊕ Cin ) is not performed. This is achieved by extending the ALU with the control line CCarryXor (Fig. 12) that controls if this exclusive-or is performed or not. Thus, the new ALU performs B ⊕ A when control CCarryXor is TRUE and the other are FALSE. It is important to note that the optimized CDKM-adder can not be used for calculating bitwise exclusive-or with this method because part of the sum calculation is moved to before the unmajority circuit. 5.5. No-Operation No-operation (NOP) is not an operation in itself, but some instructions in a computing system will require that the values are unchanged through the ALU. Most gates in the ALU are already conditioned by a control-line. The only gates that are not, are the ones that does the exclusive-or, A ⊕ B in the majority circuit of the adder. To extend the ALU with no-operation we only need a control for the gate that does the XOR. This is shown in Fig. 13 with a magenta line. If we had used the optimized CDKM-adder we would need to add more control lines to control the higher number of gates. The slightly longer delay of the VanRentergem-

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Reversible ALU for QA

Table 2. Controls for the ALU and some interesting operations resulting from the extra combinations. In all cases B is updated while A is unchanged. ALU operation

CN egB

CCarryIn

CAxorB

CCarryXor

CN egR

0 1 1 0 0

0 0 1 0 0

1 1 1 1 0

1 1 1 0 0

0 1 0 0 0

B +n A B −n A A −n B B⊕A B

0 1 1 0 0

1 1 0 0 0

1 1 1 1 0

1 1 1 0 0

0 1 0 1 1

B +n A +n 1 B −n A −n 1 A −n B −n 1 B⊕A B

ADD SUB NEG XOR NOP

adder is thus a small price for this more elegant and simple design. 5.6. Controlling the Sequential ALU The final ALU as shown in Fig. 13 has in total 5 control lines to handle the 5 arithmetic and logical operations. Tab. 2 gives an overview of what the control lines must be in order to do the calculations. Having 5 control lines and 5 combinations can seem like a waste (3 lines should be enough to give 8 combinations.) But as the ALU has a sequential design some of the other 27 combinations can result in some useful operations. These operations can either be used to extend the instruction set or used by an optimizing compiler to combine simpler instructions into more complex ones. I Tab. 2 the five most interesting operations resulting from these extra combinations have been listed. These operations include bitwise logical negation and increment, decrement operations. 5.7. Cost of the ALU The cost of the ALU is very much dominated by the binary adder which sets the Vshape and thus the logical depth. The other logical operations can be added with only a constant delay. This is surprisingly efficient compared to what we would expect of a sequentially design (as in Fig. 9). In fact, our design is just as fast as the parallel design, but uses much fewer ancillae bits and gates. In Tab. 3 there is a detailed list of costs for the ALU. 6. Related work Previous work on reversible logic has mainly focused on designs and algorithms for one specific purpose. The idea of having an ALU to perform some quantum operations is not

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Reversible ALU for QA

Table 3. Cost of the n-bit and 16 bit ALU compared to the VanRentergem-adder. VanRentergem-adder (n-bit)v

ALU (n-bit)

VR-adder (16-bit)

ALU (16-bit)

Gate count Feynman gates Toffoli gates Fredkin gates

4n − 2 2n 0 2n − 2

6n − 2 2n 2n 2n − 2

62 32 0 30

94 32 32 30

Logic depth Logic width Ancillae bits

3n − 1 2n + 1 1

3n + 1 2n + 5 0

47 33 1

49 37 0

new and has been presented by Oskin et al. [16] as an element in a quantum computer architecture. Their ALU design can perform eight basic quantum transformations where only the exclusive-or (the controlled NOT) is also included in our design. None of these transformations are arithmetic operations and no design has been suggested. For circuits in CMOS we know only of the Pendulum processor [17] where a full ALU has been designed. The Pendulum implements a reversible architecture even though it does not use reversible gates. Their ALU follows a more conventional ALU design and uses a logical inverse ALU to uncompute the temporary values (also called Bennetts trick [4]) and this design is therefore much different from what we have presented. A much used approaches to reversible circuit design uses reversible logic synthesis [18, 19, 20]. Often conventional circuits (such as the ALU) is extended with garbage bits and synthesized to reversible gates. This approach is, however, not very useful due to the differences between conventional operations and reversible operations using reversible updates. 7. Conclusion In this paper we have presented an ALU with five useful arithmetic and logical operations adapted to a two input reversible updates. The arithmetic operations include modular addition, subtraction, and negation and the logical operation exclusive-or. All the suggested operations are self-inverse or has an easy inverse operation. This makes the operations suitable as data instructions in a reversible assembly language as local inversion [9] is a key feature in design of reversible languages. The developed ALU uses a sequential design that has a logical depth that is only a small constant larger than that of a reversible ripple-carry adder circuit, using only 50% more gates. The reversible ALU will be a key element in a future design of a fully reversible architecture designed using only reversible logic. To achieve this other key elements must be designed. These include a reversible control and program counter update, and a new approach to reversible memory.

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7.1. The Quantum Leap The design concretizes the idea of “classical control, quantum data”: If we use the control lines for classical (i.e., computational basis) states only, the result will be a separable state where the control lines are conserved, and the specified operation has been applied to the data (which can be in quantum superposition). Thus, the qubits for the control lines can be prepared according to some program to be executed, and standard implementations of the quantum gates can be used throughout the circuit. This is the most likely use of a quantum ALU. However, our design is oblivious to this, and actually supports several different concepts of quantum parallelism. Firstly, in the sense above, where only the data may be placed in a superposition, and a single operation is then applied to it using the ALU. This is the concept of quantum parallelism used in the majority of quantum algorithms. In this context the interest in having an ALU stems mostly from that fact that we may “hardwire” the quantum circuit, and use a single circuit for many different algorithms. Secondly, we may use the ALU in a regime where the control data is also allowed to be in superposition. The interpretation of this is that the circuit would apply a superposition of classical (reversible) arithmetic operators on the quantum data. Of course, this can lead to entanglement of the control and the data. This usage comes intriguingly close to the fundamental ideas of the quantum Turing machine model of quantum computing [21], where the configuration (data) has a definite influence on the action taken (control). However, quantum Turing machines are difficult to analyse, and this has in part led to the focus on the quantum circuit model, and so this aspect of quantum parallelism has been largely ignored. We hope that this paper might provide inspiration for novel quantum circuit algorithms: Quantum parallelism is not limited to the data, but can also be utilized for the operators to be applied. Finally, the current ALU design implements only classical operations. The authors believe that most common general quantum operations (Walsh-Hadamard, phase shift, π/8, etc.) can be added as register operations for essentially the cost of a control line for each operation, and a small constant increase in logic depth, by using the V-shape design. References [1] Arthur W. Burks, Herman H. Goldstine, and John von Neumann. Preliminary discussion of the logical design of an electronic computing instrument. Technical report, Institute of Advanced Study, U.S. Army, 1947. [2] R. Landauer. Irreversibility and heat generation in the computing process. IBM Journal of Research Development, 5(3):183–191, 1961. [3] Michael Nielsen and Isaac L. Chuang. Quantum Computation and Quantum Information. Cambridge University Press, 2000. [4] Charles H. Bennett. Logical reversibility of computation. IBM Journal of Research and Development, 17:525–532, 1973. [5] Tetsuo Yokoyama, Holger Bock Axelsen, and Robert Glück. Principles of a reversible programming language. In Conference on Computing Frontiers. Proceedings, pages 43–54. ACM Press, 2008.

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[6] Adriano Barenco, Charles H. Bennett, Richard Cleve, David P. DiVincenzo, Norman Margolus, Peter Shor, Tycho Sleator, John A. Smolin, and Harald Weinfurter. Elementary gates for quantum computation. Physical Review A, 52(5):3457–3467, 1995. [7] Vlatko Vedral, Adriano Barenco, and Artur Ekert. Quantum networks for elementary arithmetic operations. Physical Review A, 54(1):147–153, Jul 1996. [8] Steven A. Cuccaro, Thomas G. Draper, Samuel A. Kutin, and David Petrie Moulton. A new quantum ripple-carry addition circuit. arXiv:quant-ph/0410184v1, 2005. [9] Holger Bock Axelsen, Robert Glück, and Tetsuo Yokoyama. Reversible machine code and its abstract processor architecture. In Volker Diekert, Mikhail V. Volkov, and Andrei Voronkov, editors, Computer Science – Theory and Applications. Proceedings, volume 4649 of LNCS, pages 56–69. Springer-Verlag, 2007. [10] Richard P. Feynman. Quantum mechanical computers. Optical News, 11:11–20, 1985. [11] Michael Kirkedal Thomsen and Holger Bock Axelsen. Parallelization of reversible ripple-carry adders. Parallel Processing Letters, 19(1):205–222, June 2009. [12] Michael Kirkedal Thomsen and Holger Bock Axelsen. Parallel optimization of a reversible (quantum) ripple-carry adder. In C. S. Calude, J. F. Costa, R. Freund, M. Oswald, and G. Rozenberg, editors, Proceedings of the 7. International Conference on Unconventional Computing, volume 5204 of LNCS, pages 229–242, Vienna, August 2008. Springer-Verlag. [13] Yvan Van Rentergem and Alexis De Vos. Optimal design of a reversible full adder. International Journal of Unconventional Computing, 1(4):339–355, 2005. [14] Mariusz Skoneczny, Yves Van Rentergem, and Alexis De Vos. Reversible Fourier transform chip. In Proceedings of the 15th International Conference Mixed Design of Integrated Circuits and Systems, pages 281–286, Lódz, 2008. [15] Richard K. Richards. Arithmetic Operations in Digital Computers. D. Van Nostrand Company, Inc., New York, 1955. [16] Mark Oskin, Frederic T. Chong, and Issac L. Chuang. A practical architecture for reliable quantum computers. Computer, 35(1):79–87, Jan 2002. [17] Carlin James Vieri. Reversible Computer Engeneering and Architecture. PhD thesis, Massachusetts Institute of Technology, 1999. [18] Alexis De Vos, Yves Van Rentergem, and Koen De Keyser. The decomposition of an arbitrary reversible logic circuit. Journal of Physics A: Mathematical and General, 39:5015–5035, 2006. [19] Robert Wille, Hoang M. Le, Gerhard W. Dueck, and Daniel Große. Quantified synthesis of reversible logic. In DATE ’08: Proceedings of the conference on Design, automation and test in Europe, pages 1015–1020, New York, NY, USA, 2008. ACM. [20] Dmitri Maslov and Gerhard W. Dueck. Reversible cascades with minimal garbage. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 23(11):1497–1509, 2004. [21] D. Deutsch. Quantum theory, the church-turing principle and the universal quantum computer. Proceedings of the Royal Society of London. Series A, Mathematical and Physical Sciences, 400(1818):97–117, 1985.