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Reversible arithmetic logic unit for quantum arithmetic
This content has been downloaded from IOPscience. Please scroll down to see the full text. 2010 J. Phys. A: Math. Theor. 43 382002 (http://iopscience.iop.org/1751-8121/43/38/382002) View the table of contents for this issue, or go to the journal homepage for more
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IOP PUBLISHING
JOURNAL OF PHYSICS A: MATHEMATICAL AND THEORETICAL
J. Phys. A: Math. Theor. 43 (2010) 382002 (10pp)
doi:10.1088/1751-8113/43/38/382002
FAST TRACK COMMUNICATION
Reversible arithmetic logic unit for quantum arithmetic ¨ and Holger Bock Axelsen Michael Kirkedal Thomsen, Robert Gluck DIKU, Department of Computer Science, University of Copenhagen, Denmark E-mail:
[email protected],
[email protected] and
[email protected]
Received 20 February 2010, in final form 27 July 2010 Published 16 August 2010 Online at stacks.iop.org/JPhysA/43/382002 Abstract This communication presents the complete design of a reversible arithmetic logic unit (ALU) that can be part of a programmable reversible computing device such as a quantum computer. The presented ALU is garbage free and uses reversible updates to combine the standard reversible arithmetic and logical operations in one unit. Combined with a suitable control unit, the ALU permits the construction of an r-Turing complete computing device. The garbage-free ALU developed in this communication requires only 6n elementary reversible gates for five basic arithmetic–logical operations on two n-bit operands and does not use ancillae. This remarkable low resource consumption was achieved by generalizing the V-shape design first introduced for quantum ripple-carry adders and nesting multiple V-shapes in a novel integrated design. This communication shows that the realization of an efficient reversible ALU for a programmable computing device is possible and that the V-shape design is a very versatile approach to the design of quantum networks. PACS numbers: 03.67.Lx, 03.67.Ac, 89.20.Ff Mathematics Subject Classification: 68M07, 68Q12, 81P68 (Some figures in this article are in colour only in the electronic version)
1. Introduction Since the earliest programmable computing devices, two main combinatorial units are distinguished in a computer: the control unit and the arithmetic logic unit (ALU). The former derives from instructions the control signals that determine the operation of the ALU, which then combines the operands of the instruction to produce a result. Which instruction is selected next by the control unit may depend on the result calculated by the ALU. This feedback to the control unit is essential for the computations that can be programmed. The ALU is central for the design of the instruction set of a programmable computing device. The functionality 1751-8113/10/382002+10$30.00 © 2010 IOP Publishing Ltd Printed in the UK & the USA
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A B
A A⊕B
A B
A A−B
A B
A A+B
Control A B
Control A Result
Figure 1. Reversible circuits each implementing a single function and the desired reversible controlled circuit that conditionally performs one of several functions.
provided by the ALU determines the possible set of data instructions (control instructions, the other part of an instruction set, are determined by the operation of the control unit). The basic structure of a stored-program computer, also known as von Neumann architecture, has remained remarkably stable since its inception in the 1940s [1] despite the rapidly changing technology used for its implementation, such as relays, vacuum tubes and transistors. This provides ample justification to study this fundamental scheme in the context of reversible computing [2] and reversible logic as realized today, among others, by quantum gates [3]. Reversible logic is a core part of the quantum circuit model: a reversible logic gate has a corresponding quantum version, whose effect is completely defined by the truth table for the classical version. This means that reversible circuits are also quantum circuits, and as such the hope is that lessons from reversible circuit design may contribute to improving quantum circuits. The generic approach to implementing a function f in a quantum circuit is to implement the quantum operation Uf (|x|y) = |x|y ⊕ f (x) (where ⊕ is bitwise exclusive-or). If we instantiate |y to |0, then applying Uf yields |x|f (x). This is essentially the quantum equivalent of the Bennett trick, originally used for Turing machines [4]. However, in practice it has become clear that for many important classes of functions the Bennett trick does not provide a satisfactory solution and that much better solutions are available. There is thus a good case to be made for studying reversible operations on their own terms and not just as an embedded version of classical (irreversible) operations. The same is true in quantum computing and the circuits presented here take this philosophy. The arithmetic and logical operations described below form a class where we can avoid na¨ıvely using the Bennett trick when implementing quantum (reversible) embeddings of classical functions. So, while we still implement reversible versions of irreversible operators, we can do so with markedly better embeddings than those provided by the generic approach. 1.1. Control structure in reversible logic In this communication we focus on the design of a reversible ALU that can be part of a programmable reversible computer. An ALU is a multi-functional circuit that conditionally performs one of several possible functions on two operands A and B depending on a control input. This is in contrast to the conventional design of a reversible circuit that unconditionally performs a function on A and B, for example binary addition (+), binary subtraction (−), or bitwise exclusive-or (⊕). This is illustrated abstractly in figure 1, where several single-function circuits are shown on the left-hand side and an ALU capable of performing the same functions on the right-hand side. One of the operands is preserved in the output (here, A) because the circuits are based on reversible logic. For the same reason, the control is not changed by the ALU and passed through to the output. 2
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The addition of control to a reversible circuit is an essential and necessary transition to form the next, higher level of control in a reversible computing system that integrates many elementary controlled gates (e.g. Fredkin, Toffoli and Feynman gates) into a more complex controlled system. This can be compared to the addition of control to an elementary logical operation on a lower system level, such as ⊕, to obtain an elementary controlled logic gate, say a Feynman gate, except that the design of the functionality and control of an entire unit is more complex. The integration of multiple functions into a single circuit (e.g. +, −, ⊕) comes at the expense of logical depth and the number of gates. It is therefore important for the design of a reversible ALU to maximize performance and to minimize resource costs, and on the other hand to identify a set of reversible data instructions that is expressive for programming while making it easy to build the device. Our main goal is, firstly, to have a simple design and, secondly, to reduce the logic width, the logic depth and the number of gates of the reversible ALU, rather than to provide a large set of data instructions. Nevertheless, the ALU presented in this communication, combined with a suitable control unit, permits the design of a r-Turing-complete [5] and fully programmable reversible computing device. The number of reversible logic gates required by our design is linear in the size of the two operands A and B. This n-bit ALU with five basic arithmetic–logical instructions requires 6n−2 elementary reversible logic gates (Fredkin, Toffoli and Feynman gates). As an example, an ALU with two 16 bit operands requires only 94 elementary reversible gates. This shows that the addition of control and the combination of multiple functions into a single ALU do not necessarily require a large number of gates and ancillae. The very low resource consumption was achieved by generalizing the V-shape circuit design introduced by Vedral et al [6] for quantum ripple-carry addition circuits and optimized by Cuccaro et al [7] to functions other than addition, and by nesting multiple V-shapes into a single, integrated reversible circuit design. This also demonstrates the generality and potential of the V-shape design for the quantum circuit design. It appears that this rarely used design principle is much more general than the one previously thought. This confirms that many familiar design principles from Boolean logic circuits are not necessarily suited for quantum logic circuits. Previous work on reversible logic has mainly focused on designs and algorithms for one specific purpose. The idea of having an ALU to perform some quantum operations is not new and has been presented by Oskin et al [8] as an element in a quantum computer architecture. Their ALU can perform eight basic quantum transformations where only the exclusive-or (the controlled NOT) is also included in our design. None of these transformations are arithmetic operations and no logic design has been suggested. For circuits in CMOS technology, we know only of the pendulum processor [9] where a full ALU has been designed. The pendulum implements a reversible architecture even though it does not use reversible logic gates. Their ALU follows a more conventional ALU design and uses a logical inverse ALU to uncompute the temporary values, which is an implementation of the Bennett trick, and this design is therefore much different from what we present. This communication is organized as follows. After reviewing modular arithmetic, the binary number representation and the V-shape design of quantum addition circuits (section 2), the main design choices for a reversible ALU are investigated (section 3). The reversible data instructions are introduced and our novel ALU design is stepwise developed (section 4). Finally, we present our conclusions in section 5. We assume that readers are familiar with the basics of reversible logic networks, e.g., as presented by Barenco et al [10]. 3
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2. Modular arithmetic In this section we briefly review reversible modular arithmetic with binary numbers. We use reversible updates [5, 11] to ensure the reversibility of the operations. Modular addition. An immediate problem to the design of a reversible binary adder is that addition is not an injective function. The sum A + B does not uniquely determine the operands A and B. However, addition is injective in one of the operands, which means that preserving A or B is sufficient to uniquely determine the other operand from the sum. The definition of addition for a reversible adder then takes the form of the reversible update (A, B) → (A, B + A) . In an implementation of the adder that must rely on a representation using a finite size of integers, the sum may overflow the largest representable number. To preserve reversibility of the adder, we use n-bit modular addition def.
B +n A = (B + A) mod 2n and thus define the reversible update as (A, B) → (A, B +n A) . Modular subtraction. The reversible update for modular subtraction is defined as (A, B) → (A, B −n A) .When using binary numbers modular subtraction is closely related to modular addition and bitwise negation. We have the two equalities: B −n A = B +n A +n 1 = B +n A −n 1, where A is the bitwise negation of A. The first equality is actually used for calculating subtraction in a conventional ALU by two additions, one of which is a simple increment. This is, however, not a suitable approach for a reversible operation. To define modular subtraction as a reversible update, the updating value, A, must be kept unchanged and both the above identities require a bitwise negation of A that must be uncomputed later to restore A. Using these two equalities we can, however, redefine modular subtraction as B −n A = B +n A. This leaves A unchanged while only requiring the negation of B and the sum B +n A. Modular subtraction is the inverse operation of modular addition: B = (B +n A) −n A. Modular negative subtraction. Using conventional subtraction one can calculate both the positive and the negative difference: B − A and A − B. But using the reversible update for subtraction (where A must be preserved), it is only possible to calculate the first of these. We therefore define a modular negative subtraction, using one of the previous equations, as A −n B = A +n B +n 1 with the reversible update (A, B) → (A, A −n B) . Again, this definition leaves A unchanged while only negating B and incrementing the sum A +n B. It is worth noting that in contrast to modular subtraction, which is the inverse operation of modular addition, modular negative subtraction is its own inverse: B = A −n (A −n B). In the special case A = 0, this yields the negative of B. Two’s complement number representation. Negative and positive integers can be represented using two’s complement numbers, today’s standard binary number representation1 . One of the reasons why this representation is widely used is that the order of the numbers is unchanged 1
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Two’s complement numbers are n-bit numbers where the base value, 0, has been shifted to −2n−1 .
J. Phys. A: Math. Theor. 43 (2010) 382002
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B
0 0 0 0
Result
(a)
Fredkin Multiplex
Multiplex
A
Fredkin Multiplex
A B
Control
Control A Result 0 0 0 0
(b)
Control A B
Control A Result
(c)
Figure 2. (a) Design of a classical ALU. The operations are done in parallel and a multiplexer selects the desired result depending on the control. (b) Design of a parallel reversible ALU. As in the conventional ALU the operations are done in parallel, but two multiplexers are needed to direct the input through the desired operation to the output. (c) Design of a sequential reversible ALU. The control ensures that only the desired operation is performed.
and, what is important in our context, circuits for modular binary addition and subtraction can be used for two’s complement numbers. The ALU presented in this communication is thus fully functional for integers represented by two’s complement numbers. 3. The arithmetic logic unit In a classical design of an ALU (figure 2(a)), the arithmetic–logical operations are first performed in parallel and then the desired result is selected by a multiplexer—a circuit that chooses one out of several inputs depending on a control. All other results are lost. This destructive approach is suitable for conventional Boolean circuits, but not for reversible circuits where we wish to have no garbage generation. It is therefore necessary to develop a new design for a reversible ALU. We examine the basics of the parallel and the serial design approach for a reversible ALU in this section. 3.1. Parallel ALU design A parallel design of a reversible ALU (figure 2(b)) follows a strategy similar to the conventional ALU. Using two reversible multiplexers2 the input is first directed to the desired arithmetic– logical operation and afterwards reversibly directed to the result line. Ancillae are used for the operations that are not selected and it is important that the operations are organized such that the ancillae are unchanged over the operations. This ALU is simple to design and to verify because it consists of several independent subcircuits. As it is parallel, it is expected to be fast, but this comes at the expense of a large logic width and a large number of ancillae. 3.2. Sequential ALU design In a sequential design of a reversible ALU (figure 2(c)), the arithmetic–logical operations are performed on the same lines and, instead of selecting the desired result by a multiplexer after 2 A reversible multiplexer can be implemented using Fredkin gates which guide the selected input to the output. This approach is in contrast to the conventional multiplexer that selects one of the inputs and discards the others.
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calculating all operations in parallel, the desired operation in a series of operations is turned on by the control. A serial ALU can be expected to be slower because of a larger logic depth and more complex to design than a parallel ALU because of a more involved control, but has a smaller logic width. We will however see that an ALU with few arithmetic and logical operations can benefit from a sequential design. The reduced number of ancillae is also consistent with our goal of having a minimal design. An ALU design for more complex arithmetic instructions may benefit from a combination of the parallel and sequential designs (possibly using ancillae), but as we will see the depth of our sequential ALU design is only a small constant larger than the binary adders. 4. An arithmetic logic unit using the V-shape This section presents the design of a reversible n-bit ALU based on a controlled and nested V-shape with a sequential arrangement of operations. First, we introduce the basic set of operations and then develop the ALU design step-by-step starting from a reversible modular adder based on the V-shape design [6, 7, 12]. 4.1. Basic operations The basic set of reversible arithmetic and logical operations that we intend to implement by the ALU is small, but expressive. These operations can form the basis of a reversible machine code [11]. Later we will see that the final ALU design allows more than these five operations. Each operation has the format of a reversible update and has two n-bit arguments A and B: modular addition (ADD):
(A, B) → (A, B +n A)
modular subtraction (SUB):
(A, B) → (A, B −n A)
modular negative subtraction (NSUB):
(A, B) → (A, A −n B)
bitwise exclusive-or (XOR):
(A, B) → (A, B ⊕ A)
no-operation (NOP):
(A, B) → (A, B).
4.2. Choice of reversible binary adder The backbone of the ALU design is an n-bit V-shaped binary adder first designed by Vedral et al [6] and later improved in several ways [7, 12]. Of the improved adders there are two interesting candidates: (1) the CDKM adder [7] because it has the smallest delay and (2) the VanRentergem adder [12] because is has the smallest gate count. We choose the VanRentergem adder (figure 3) because it has advantages compared to the optimized CDKM adder when it comes to the implementation of exclusive-or operation and no-operation in the ALU. We will return to this point when we extend the ALU with these operations. Detailed descriptions of V-shaped adders can be found in the mentioned literature and summary [13]. 4.3. Subtraction and negation The definition of modular subtraction, B +n A, that we introduced in section 2 requires two bitwise negations and one modular addition. By extending the V-shaped binary adder (figure 3) with two arrays of Feynman gates at each side (the two long-dashed boxes in the final design in figure 4), bitwise negation can be performed on the adder’s input B and output 6
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A0 B0
0
Fast Track Communication 0 A0 R0
A1 B1
A1 R1
An −2 Bn −2
An −2 Rn −2
An −1 Bn −1
An −1 Rn −1
Figure 3. The n-bit VanRentergem adder is the backbone of the reversible ALU design. The adder takes two numbers (A, B) and a carry-in as input and produces the sum (R), one of the numbers (A) and the original carry-in. For addition the carry-in is set to 0.
R by setting the controls CNegB and CNegR to TRUE, respectively. The ALU then calculates B −n A, otherwise B +n A. The definition of modular negative subtraction, A +n B +n 1 (section 2), needs a bitwise negation of B and the addition of 1. Bitwise negation of B has just been added to the ALU for modular subtraction. The ancilla bit used in the adder (see the top of figure 3) can be used as carry-in to the adder. Setting the carry-in to TRUE adds 1 to the operands of the adder. Thus, if the two controls CNegB and CCarryIn are TRUE, the ALU calculates A −n B. We have now an ALU with operations for modular addition, modular subtraction and modular negative subtraction, which are performed by setting the corresponding controls. 4.4. Bitwise exclusive-or The bitwise exclusive-or (XOR) is an elementary operation in reversible logic and its reversible update is a controlled NOT or a Feynman gate, but extending the ALU is more involved. We need to ensure that the binary adder does not interfere. A bit of the sum, Ri, is defined as Ri = Ai ⊕ Bi ⊕ Carryi . This means that the binary adder calculates A ⊕ B, if the second exclusive-or with Cin is not performed. The gates that perform the latter operation are marked with dashed boxes on the right in figure 3. To control these gates, the control line CCarryXor is added (figure 4). The extended ALU thus performs B ⊕ A when all controls are FALSE. 4.5. No-operation No-operation (NOP) is the identity function and used when instructions in a computing system require that the operands remain unchanged by the ALU. Most gates in the ALU already depend on a control line. The only gates that are not, are the ones that do the exclusive-or, A ⊕ B, (the gates in dotted boxes on the left in figure 3) in the adder. To allow the ALU to be idle and not perform an operation, the no-operation, only a control for the gate that does the XOR is needed. This is shown in figure 4 with control line CAx or B . 7
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CAxorB CCarryXor CNegR CCarryIn CNegB
CAxorB CCarryXor CNegR CCarryIn CNegB
A0 B0
A0 R0
A1 B1
A1 R1
An −2 Bn −2
An −2 Rn −2
An −1 Bn −1
An −1 Rn −1
Figure 4. Reversible ALU with addition, subtraction, negation, exclusive-or and no-operation (ADD, SUB, NSUB, XOR and NOP).
Table 1. Controls for the ALU and selected operations resulting from extra combinations. In all cases B is updated while A is unchanged.
CNeg B
CCarryIn
CAx or B
CCarryXor
CNeg R
ALU operation
0 1 1 0 0
0 0 1 0 0
1 1 1 1 0
1 1 1 0 0
0 1 0 0 0
B +n A B −n A A −n B B ⊕A B
0 1 1 0 0
1 1 0 0 0
1 1 1 1 0
1 1 1 0 0
0 1 0 1 1
B +n A +n 1 B −n A −n 1 A −n B −n 1 B ⊕A B
ADD SUB NSUB XOR NOP
If we had used the CDKM adder we would need to add more control lines to control the larger number of gates. The slightly longer delay of the VanRentergem adder is thus a small price for a more elegant and simple design of the ALU. 4.6. Controlling the sequential ALU The final ALU as shown in figure 4 has five control lines selected among five arithmetic and logical operations. The upper part of table 1 shows how the controls must be set to select one of these operations. Having five control lines to select among five operations may seem redundant (three lines would be enough to selected among eight combinations). But as the ALU has a sequential design some of the other 27 combinations can result in some useful operations. These 8
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Table 2. Cost of the n-bit and 16-bit ALU compared to the VanRentergem adder (VR-adder).
VR-adder (n-bit)
ALU (n-bit)
VR-adder (16-bit)
ALU (16-bit)
Gate count total Feynman gates Toffoli gates Fredkin gates
4n − 2 2n 0 2n − 2
6n − 2 2n 2n 2n − 2
62 32 0 30
94 32 32 30
Logic depth Logic width Ancilla bits
3n − 1 2n + 1 1
3n + 1 2n + 5 0
47 33 1
49 37 0
operations can be used to extend the instruction set. The lower part of table 1 lists five additional and practically most interesting operations resulting from these extra combinations. These operations include bitwise logical negation and increment, decrement operations. 4.7. Cost of the ALU The cost of the ALU is dominated by the binary adder which defines the V-shape and thus the logical depth. The other logical operations only add a constant delay. This is surprisingly efficient compared to what one would expect of a sequentially design (as in figure 2). In fact, our design is just as fast as the parallel design, but uses much fewer ancillae and gates. Table 2 gives a detailed list of the costs of the ALU. 5. Conclusion We presented the design of an ALU for a programmable computing device starting with five versatile arithmetic–logical operations. The arithmetic operations include modular addition, subtraction, negation and the logical operation exclusive-or. All suggested operations are self-inverse or have an easy inverse operation. This makes the operations suitable as data instructions in a reversible assembly language as local inversion [11] is a key to the design of reversible programming languages. The final design of the ALU allows several additional operations resulting from extra combinations of the control lines. The results show that the realization of an efficient reversible ALU is possible with much fewer reversible logic gates and fewer ancillae than previously thought. The logical depth of the ALU is only a small constant larger than that of a reversible ripple-carry adder circuit, using only 50% more gates. The introduction of an ALU in a reversible computing device is thus less costly than one might expected. This was achieved by generalizing and nesting the V-shape design originally invented for reversible adders, which shows that the V-shape is a very versatile design approach. The reversible ALU will be a central unit in a future design of a fully reversible architecture using only reversible logic elements. For a complete architecture, more key elements must be designed including a reversible control unit and a new approach to reversible memory. 5.1. Using the ALU for quantum computing The above ALU has two kinds of signals (control lines and data lines) both of which are considered classical bits. However, the design also concretizes the idea of ‘classical control, 9
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quantum data’: if we use the control lines for classical (i.e. computational basis) states only, the result will be a separable state where the control lines are conserved and the specified operation has been applied to the data (which can be in quantum superposition). Thus, the bits for the control lines can be prepared according to some program to be executed, and standard implementations of quantum gates can be used throughout the circuit. In this context the interest in an ALU design stems mostly from that fact that we may ‘hardwire’ the quantum circuit, and use a single circuit for many different algorithms. The current ALU design implements only classical operations and it is still an open question if most common general quantum operations (Walsh–Hadamard, phase shift, π/8, etc) can be added as register operations for essentially the cost of a control line for each operation and a small constant increase in logic depth, by using the V-shape design. References [1] Burks A W, Goldstine H H and von Neumann J 1947 Preliminary discussion of the logical design of an electronic computing instrument Technical Report Institute for Advanced Study, Princeton, NJ, USA [2] Landauer R 1961 Irreversibility and heat generation in the computing process IBM J. Res. Dev. 5 183–91 [3] Nielsen M and Chuang I L 2000 Quantum Computation and Quantum Information (Cambridge: Cambridge University Press) [4] Bennett C H 1973 Logical reversibility of computation IBM J. Res. Dev. 17 525–32 [5] Yokoyama T, Axelsen H B and Gl¨uck R 2008 Principles of a reversible programming language Conf. on Computing Frontiers (New York: ACM) pp 43–54 [6] Vedral V, Barenco A and Ekert A 1996 Quantum networks for elementary arithmetic operations Phys. Rev. A 54 147–53 [7] Cuccaro S A, Draper T G, Kutin S A and Moulton D P 2005 A new quantum ripple-carry addition circuit arXiv:quant-ph/0410184v1 [8] Oskin M, Chong F T and Chuang I L 2002 A practical architecture for reliable quantum computers Computer 35 79–87 [9] Vieri C J 1999 Reversible computer engineering and architecture PhD Thesis Massachusetts Institute of Technology [10] Barenco A et al 1995 Elementary gates for quantum computation Phys. Rev. A 52 3457–67 [11] Axelsen H B, Gl¨uck R and Yokoyama T 2007 Reversible machine code and its abstract processor architecture Computer Science—Theory and Applications. Second International Symposium on Computer Science in Russia (Lecture Notes in Computer Science vol 4649) (Berlin: Springer) pp 56–69 [12] Skoneczny M, Van Rentergem Y and De Vos A 2008 Reversible Fourier transform chip 15th Int. Conf. on Mixed Design of Integrated Circuits and Systems pp 281–86 [13] Thomsen M K and Axelsen H B 2009 Parallelization of reversible ripple-carry adders Parallel Process. Lett. 19 205–22
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