Journal of Circuits, Systems, and Computers Vol. 22, No. 1 (2013) 1250071 (14 pages) # .c World Scienti¯c Publishing Company DOI: 10.1142/S0218126612500715
REALIZATION OF FIRST-ORDER CURRENT-MODE ¤ FILTERS WITH LOW NUMBER OF MOS TRANSISTORS
J CIRCUIT SYST COMP 2013.22. Downloaded from www.worldscientific.com by 211.144.81.67 on 06/16/14. For personal use only.
ERKAN YUCE Pamukkale University, Department of Electrical and Electronics Engineering, Denizli, Kinikli 20070, Turkey
[email protected] SHAHRAM MINAEI† Dogus University, Department of Electronics and Communications Engineering, Acibadem, Kadikoy 34722, Istanbul, Turkey
[email protected] NORBERT HERENCSAR‡ and JAROSLAV KOTON§ Brno University of Technology, Department of Telecommunications, Purkynova 118, 612 00 Brno, Czech Republic ‡
[email protected] §
[email protected] Received 9 October 2011 Accepted 29 June 2012 Published 14 January 2013 In this paper, a new current-mode (CM) circuit for realizing all of the ¯rst-order ¯lter responses is suggested. The proposed con¯guration contains low number of components, only two NMOS transistors both operating in saturation region, two capacitors and two resistors. Major advantages of the presented circuit are low voltage, low noise and high linearity. The proposed ¯lter circuit can simultaneously provide both inverting and non-inverting ¯rst-order low-pass, high-pass and all-pass ¯lter responses. Computer simulation results achieved through SPICE tool and experimental results are given as examples to demonstrate performance and e®ectiveness of the proposed topology. Keywords: NMOS; ¯rst-order ¯lter; current-mode.
1. Introduction The use of current-mode (CM) active devices o®ers some important potential advantages called as higher usable gain, reduced voltage excursion at sensitive nodes, *This paper was recommended †Corresponding author.
by Regional Editor Majid Ahmadi.
1250071-1
J CIRCUIT SYST COMP 2013.22. Downloaded from www.worldscientific.com by 211.144.81.67 on 06/16/14. For personal use only.
E. Yuce et al.
greater linearity, less power consumption, wider bandwidth, better accuracy and larger dynamic range compared to that of voltage-mode counterparts for example operational ampli¯ers.13 It is a well known fact that an all-pass ¯lter (phase shifter) topology like previously reported ¯rst-order signal processing units418 ¯nds wide application areas in analog signal processing systems, control engineering, etc. in order to shift phases of the signals while keeping their amplitudes unchanged. A ¯rstorder all-pass ¯lter requiring at least one capacitive component and one resistive component has a pole on the left half s plane and a zero on the right half s plane. The pole and zero has the same value in magnitude. The ¯lters of Refs. 49 and 18 use CMOS technology but operate in voltage-mode (VM). On the other hand, the circuits in Refs. 10, 13 and 14 operate in CM but employ BJT technology. The CM ¯lter of Ref. 11, which is suitable for high frequency applications, contains three CMOS transistors, a °oating resistor for biasing purpose and a large coupling capacitor for dc isolation of the load. The circuit reported in Ref. 12 is a square-root-domain CM ¯lter which needs two identical bias currents. It is worth to note that a simple squareroot-domain integrator needs more than 30 transistors.12 Further, many phase shifters like circuits in Refs. 1518 using active building blocks such as secondgeneration current conveyors (CCIIs) have been reported in open literature. It should be noted that a CCII typically involves more than ten transistors. In this paper, a novel CM circuit for simultaneously providing both inverting and non-inverting ¯rst-order low-pass, high-pass and all-pass ¯lter responses is suggested. The developed ¯lter structure includes a lower number of elements such as only two NMOS transistors, two capacitors and two resistors. The presented circuit enjoys low voltage, low noise and high linearity. However, it requires matching conditions for
Table 1.
Comparison with previously published CM all-pass ¯lters. Properties
Reference
Number of transistors
Number of R/C
Passive component matching constraint
10 11 12 13 14 15 16 17 This work
6 3 7 12 10 38* 38 32 2
0/1 2/2 0/1 0/1 0/1 2/1 1/1 1/1 2/2
no no no no no yes no no yes
Type of response
Technology
Power supplies
Inverting Non-inverting Non-inverting Non-inverting Inverting Both** Both simultaneously Both*** Both simultaneously
BJT 0.18 m 0.35 m BJT BJT 0.35 m 0.5 m 0.25 m 0.13 m
1:5 V þ1.8 V þ3.3 V þ3.0 V 5:0 V 2:5 V 2:0 V 1:25 V 0:75 V
*Except four NMOS transistors used to obtain two tunable resistors. **There are two di®erent circuits, one of which is inverting while other one is non-inverting. ***Inverting response is obtained by RC-CR transformation.
1250071-2
Realization of First-Order CM Filters with Low Number of MOS Transistors
all-pass responses. Simulation results and experimental measurements are included to verify the theory. Table 1 summarizes the advantages and disadvantages of the previously published CM all-pass ¯lters as well as the proposed one.
J CIRCUIT SYST COMP 2013.22. Downloaded from www.worldscientific.com by 211.144.81.67 on 06/16/14. For personal use only.
2. Proposed CM All-Pass Filter The proposed CM topology for realizing various ¯rst-order ¯lters is shown in Fig. 1. It can be seen that it employs an inverting ampli¯er with the voltage gain of . The employed inverting ampli¯er should possess high input and low output impedances ideally. Such an ampli¯er with unity gain in magnitude can be found in Ref. 5 using two NMOS and three PMOS transistors or in Refs. 6 and 8 using only two NMOS transistors with large dimensions. Analysis of the proposed CM con¯guration of Fig. 1 gives the following responses: (i) Non-inverting low-pass transfer function (TF) and phase response Ilp1 1 ¼ ; 1 þ sC1 R1 Iin
ð1aÞ
’lp1 ð!Þ ¼ tan 1 ð!C1 R1 Þ :
ð1bÞ
(ii) Non-inverting high-pass TF and phase response Ihp1 sC1 R1 ¼ ; Iin 1 þ sC1 R1 ’hp1 ð!Þ ¼ tan 1 ð!C1 R1 Þ : 2
Fig. 1. Developed CM con¯guration for realizing ¯rst-order ¯lters.
1250071-3
ð2aÞ ð2bÞ
E. Yuce et al.
(iii) Inverting low-pass TF and phase response R 1 Ilp2 R2 ¼ ; Iin 1 þ sC1 R1
ð3aÞ
’lp2 ð!Þ ¼ tan 1 ð!C1 R1 Þ :
ð3bÞ
J CIRCUIT SYST COMP 2013.22. Downloaded from www.worldscientific.com by 211.144.81.67 on 06/16/14. For personal use only.
(iv) Inverting high-pass TF and phase response Ihp2 sC2 R1 ¼ ; ð4aÞ Iin 1 þ sC1 R1 ’hp2 ð!Þ ¼ tan 1 ð!C1 R1 Þ : ð4bÞ 2 Here, the pole frequency of the ¯lter from Fig. 1 is found as !o ¼ 1=ðC1 R1 Þ. Further, if ¼ 1 as for the inverting ampli¯ers in Refs. 5 and 6, the following responses can be obtained: (v) Inverting all-pass TF and phase response if R2 ¼ R1 as Iap1 Ihp1 Ilp2 1 sC1 R1 ¼ þ ¼ ; Iin Iin Iin 1 þ sC1 R1
ð5aÞ
’ap1 ð!Þ ¼ 2 tan 1 ð!C1 R1 Þ :
ð5bÞ
(vi) Non-inverting all-pass TF and phase response if C2 ¼ C1 as Iap2 Ilp1 Ihp2 1 sC1 R1 ¼ þ ¼ ; Iin Iin Iin 1 þ sC1 R1
ð6aÞ
’ap2 ð!Þ ¼ 2 tan 1 ð!C1 R1 Þ :
ð6bÞ
It should be noted that the all-pass ¯lters of Refs. 415, 17 and 18 can realize only one all-pass response. In order to obtain output currents at high-output-impedance terminals from the structure in Fig. 1, a current bu®er is required for each current. For this purpose a current follower (CF)19 can be a good choice. However, a CF has an input parasitic resistance denoted by Rp . The output of the developed inverting all-pass ¯lter connected to the input of a CF is shown in Fig. 2. Considering the required conditions for the inverting all-pass response as R1 ¼ R2 and ¼ 1, the corresponding gain and phase responses are computed as Iap1 ¼ Iin
1 sC1 R1 ; Rp 1þ þ sC1 ðR1 þ 3Rp Þ R1 0
ð7aÞ 1
B !C1 ðR1 þ 3Rp Þ C C: ’ap1 ð!Þ ¼ tan 1 ð!C1 R1 Þ tan 1 B @ A Rp 1þ R1 From (7), one should select R1 3Rp to prevent the loading e®ect. 1250071-4
ð7bÞ
J CIRCUIT SYST COMP 2013.22. Downloaded from www.worldscientific.com by 211.144.81.67 on 06/16/14. For personal use only.
Realization of First-Order CM Filters with Low Number of MOS Transistors
Fig. 2. The output of the suggested all-pass ¯lter connected to the input of a CF.
3. Parasitic E®ects The parasitic of the employed ampli¯er can be considered as parallel capacitance and resistance at its input terminal ðRy jjCy Þ and output resistance ðRo Þ in series at its output terminal as shown in Fig. 3. Since Ry and Cy appear in parallel with externally connected R1 and C1 , their e®ects can be neglected selecting R1 Ry and C1 Cy . Considering the output resistance Ro of the inverting ampli¯er, while the current responses Ilp1 and Ihp1 remain undisturbed, Ilp2 and Ihp2 and their
Fig. 3. Inverting ampli¯er with parasitic impedances.
1250071-5
E. Yuce et al.
corresponding phase responses convert to
J CIRCUIT SYST COMP 2013.22. Downloaded from www.worldscientific.com by 211.144.81.67 on 06/16/14. For personal use only.
Ilp2 R1 ; ¼ Iin ð1 þ sC1 R1 ÞðR2 þ Ro þ sC2 R2 Ro Þ 1 1 !C2 R2 Ro ’lp2 ð!Þ ¼ tan ð!C1 R1 Þ tan ; R2 þ Ro Ihp2 sC2 R1 R2 ; ¼ Iin ð1 þ sC1 R1 ÞðR2 þ Ro þ sC2 R2 Ro Þ 1 1 !C2 R2 Ro ’lp2 ð!Þ ¼ tan ð!C1 R1 Þ tan : 2 R2 þ Ro
ð8aÞ ð8bÞ ð9aÞ ð9bÞ
It can be seen that a second pole appears in the TF of the ¯lter due to the nonzero output resistance of the ampli¯er as !p2 ¼
R2 þ R o 1 1 ¼ þ : C2 R2 Ro C2 Ro C2 R2
ð10Þ
Thus one should select Ro R2 in order to neglect the e®ect of the second pole. Similarly, for the all-pass responses we can obtain Iap1 R ð sC1 ðR2 þ Ro Þ s 2 C1 C2 R2 Ro Þ ; ¼ 1 ð1 þ sC1 R1 ÞðR2 þ Ro þ sC2 R2 Ro Þ Iin !C1 ðR2 þ Ro Þ 1 ’ap1 ð!Þ ¼ tan þ ! 2 C1 C2 R2 Ro !C2 R2 Ro tan 1 ð!C1 R1 Þ tan 1 ; R2 þ Ro Iap2 R2 þ Ro sC2 R2 ðR1 Ro Þ ; ¼ ð1 þ sC1 R1 ÞðR2 þ Ro þ sC2 R2 Ro Þ Iin 1 !C2 R2 ðR1 Ro Þ ’ap2 ð!Þ ¼ tan R2 þ Ro !C2 R2 Ro tan 1 ð! C1 R1 Þ tan 1 : R2 þ Ro
ð11aÞ
ð11bÞ ð12aÞ
ð12bÞ
Note that the proposed all-pass ¯lter having no capacitor connected in series to the X terminal of the inverting ampli¯er; accordingly, it can be worked at higher frequencies.20
4. Noise Analysis The inverting ampli¯er used in the structure of the proposed CM all-pass ¯lter can be implemented with two NMOS transistors as shown in Fig. 4(a).8 The gain of the 1250071-6
Realization of First-Order CM Filters with Low Number of MOS Transistors
VDD
VDD
_
dv22 M2
+
M2
Vo
Vo
M1
+
+
+
Vin
_
Vin
_
M1 _
J CIRCUIT SYST COMP 2013.22. Downloaded from www.worldscientific.com by 211.144.81.67 on 06/16/14. For personal use only.
dv21
VSS
VSS (a)
(b)
Fig. 4. (a) NMOS-based inverting ampli¯er. (b) Noise model.
ampli¯er is found as Vo ¼ ¼ Vin
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ðW =LÞ1 ; ðW =LÞ2
ð13Þ
where ðW =LÞi is the ratio of the channel width to channel length of the ith (i ¼ 1; 2) transistor. The inverting ampli¯er including noise sources of the transistors is shown in Fig. 4(b). The noise density sources of the transistors can be represented as: dV 12 ¼ 4kTReff1 df ;
ð14aÞ
¼ 4kTReff2 df ;
ð14bÞ
dV 22
where k is the Boltzmann's constant and T is absolute temperature in Kelvin. Here, Reffi is the e®ective thermal noise resistance of the ith transistor given as
Reffi In (15),
2 3
gm
2 ¼ 3 þ RGi þ RBi ðn 1Þ 2 : gmi
ð15Þ
represents the channel noise e®ect, RG is the poly gate resistor and RB
is the substrate resistance.21 The substrate resistance is multiplied by a factor of ðn 1Þ 2 where n 1 is equal to the ratio of the bulk transconductance to the transconductance of the transistor, i.e., ggmb . m 1250071-7
E. Yuce et al.
The noise voltage of transistor M2 in Fig. 4(b) is visible at its source terminal. Thus the equivalent input noise density of the ampli¯er is found as 2 dVieq ¼ dV 12 þ
g 2m2 1 dV 22 ¼ dV 12 þ 2 dV 22 : 2 g m1
ð16Þ
J CIRCUIT SYST COMP 2013.22. Downloaded from www.worldscientific.com by 211.144.81.67 on 06/16/14. For personal use only.
Assuming matched transistors gm1 ffi gm2 and consequently ¼ 1, the total equiv2 alent input noise density is dVieq ffi 2dV 12 . For the all-pass ¯lter of Fig. 1, there are additional thermal noises due to the external resistors R1 and R2 . Thus, the total equivalent input noise of the proposed CM all-pass ¯lter can be given as: 2 dVieqap ¼ 4kTR1 df þ 2dV 12 þ
1 4kTR2 df : 2
ð17Þ
From (17), an equivalent input resistance ðRieqap Þ for noise calculation purpose can be de¯ned as: 1 Rieqap ¼ R1 þ 2Reff1 þ 2 R2 : ð18Þ The bandwidth (BW) of the equivalent input noise density is limited by the external capacitor C1 . Thus the integrated noise of this resistorcapacitor combination (or all-pass ¯lter) is found by taking the integral over all frequencies as Z 1 2 dVieqap 2 2 ¼ 4kTRieqap BW ; ð19Þ Vieqap ¼ 2 f 0 1þ BW where BW ¼
1 2Rieqap C1
:
ð20Þ
Substituting (20) into (19), the integrated noise is simply found as kT =C1 . For wideband systems the integrated noise is important, thus to reduce the noise we have to select larger capacitances which obviously will increase the power consumption.21
5. Simulation and Experimental Results In this section, simulation results of the proposed ¯rst-order all-pass ¯lter in Fig. 1 based on 0.13 m IBM MOS technology parametersa with 0.75 V dc power supply voltages are demonstrated. The aspect ratios of both NMOS transistors of inverting ampli¯er in Fig. 46 are chosen as 104 m/0.13 m. The aspect ratio of the transistors are selected large to prevent loading e®ect. The non-ideality parameters of the structure given in Fig. 4 are found as ¼ 0:852, Ro ¼ 13:66 , Cy ¼ 221 fF, Ry 1. a http://www.mosis.com/cgi-bin/cgiwrap/umosis/swp/params/ibm-013/t97f
1250071-8
8hp 5lm-params.txt.
Realization of First-Order CM Filters with Low Number of MOS Transistors
Magnitude (dB)
0 -3 -6
90
Ideal
0 1k
Simulation 10k
100k
1M Frequency (Hz)
10M
100M
1G
Fig. 5. Simulated magnitude and phase responses of the Iap1 .
Magnitude (dB)
0 -3 -6 -9 0
Phase (deg.)
J CIRCUIT SYST COMP 2013.22. Downloaded from www.worldscientific.com by 211.144.81.67 on 06/16/14. For personal use only.
Phase (deg.)
-9 180
-90
-180 1k
Ideal
Simulation 10k
100k
1M
10M
100M
1G
Frequency (Hz)
Fig. 6. Simulated magnitude and phase responses of the Iap2 .
Passive components of the all-pass ¯lter depicted in Fig. 1 are taken as R1 ¼ R2 ¼ 12 k and C1 ¼ C2 ¼ 10 pF to obtain the resonance frequency of fo ffi 1:32 MHz. For this purpose, ideal and simulated magnitude and phase responses of the all-pass ¯lter, Iap1 and Iap2 , are shown in Figs. 5 and 6, respectively. Time domain responses of Iap1 and Iap2 are demonstrated in Fig. 7. Total harmonic distortion (THD) variations versus amplitudes of peak values of input current are given in Table 2, where at the outputs of Iap1 and Iap2 . The 20 resistors are connected to simulate the e®ect of the current. Similarly, input and output noise variations against frequency for Iap1 and Iap2 are tabulated in Tables 3 and 4, respectively. Monte Carlo analysis of the introduced all-pass ¯lter with 20% variations of C ¼ 10 pF is achieved after a hundred runs. In addition, the variations of the
1250071-9
E. Yuce et al.
Iin (µA)
20 0
Iap1 (µA)
-20 20 0
J CIRCUIT SYST COMP 2013.22. Downloaded from www.worldscientific.com by 211.144.81.67 on 06/16/14. For personal use only.
Iap2 (µA)
-20 20 0 -20
1
2
3 Time (µs)
4
5
Fig. 7. Time domain responses of the all-pass ¯lter.
Table 2. THD variations of all-pass responses of the ¯lter in Fig. 1 at 1.32 MHz. Magnitude of input current (A)
Iap1 , THD (%)
Iap2 , THD (%)
1 5 10 15 20 25 30 35 40 45 50
0.379 0.582 1.119 1.609 2.046 2.353 2.581 2.782 2.955 3.114 3.232
0.628 1.242 2.306 3.275 4.072 4.684 5.192 5.639 6.050 6.490 7.103
magnitude of all-pass ¯lter at 1.32 MHz are demonstrated in Fig. 8. The magnitudes of Iap1 and Iap2 with respect to frequency are drawn in Fig. 9. In order to con¯rm the simulation results, the behavior of the Iap1 response of the proposed all-pass ¯lter has also been veri¯ed by experimental measurements using network-spectrum analyzer Agilent 4395A, function generator Agilent 33521A, and oscilloscope Agilent DSOX2014A. In measurements the readily available array transistors CD4007UBb by Texas Instruments with 15 V dc supply voltages have been used. To perform the measurements of the proposed CM ¯lter, the circuit was extended by voltage-to-current and current-to-voltage converters realized by OPA860 ICsc by Texas Instruments with dc power supply voltages equal to 5 V as b Datasheet CD4007UB — CMOS Dual Complementary Pair Plus Inverter. Texas Instruments, SCHS018CRev. September 2003. c Datasheet OPA860 — Wide Bandwidth Operational Transconductance Ampli¯er (OTA) and Bu®er. Texas Instruments, SBOS331CJune 2005Rev. August 2008.
1250071-10
Realization of First-Order CM Filters with Low Number of MOS Transistors
Frequency (Hz)
p Output noise (pV/ Hz)
p Input noise (pA/ Hz)
1 10 3 1 10 4 1 10 5 1 10 6 1 10 7 1 10 8
575.64 575.64 575.63 575.04 574.04 574.02
33.81 33.81 33.78 31.98 29.54 29.48
Table 4. Input and output noises of the all-pass ¯lter in Fig. 1 ðIap2 Þ against frequency. Frequency (Hz)
p Output noise (pV/ Hz)
p Input noise (pA/ Hz)
1 10 3 1 10 4 1 10 5 1 10 6 1 10 7 1 10 8
575.77 575.77 575.77 575.72 575.59 572.45
28.79 28.79 28.82 30.67 34.69 35.11
Percent of Samples
12
8
4
0 -0.9
-0.85
-0.8
-0.75
-0.7
-0.65
-0.6
DB(I(Vap1)) n samples = 100 n divisions = 20
mean sigma
= -0.736788 = 0.0765834
minimum 10th %ile
= -0.888412 = -0.844094
median 90th %ile
= -0.722585 = -0.631443
maximum = -0.613337
12 Percent of Samples
J CIRCUIT SYST COMP 2013.22. Downloaded from www.worldscientific.com by 211.144.81.67 on 06/16/14. For personal use only.
Table 3. Input and output noises of the all-pass ¯lter in Fig. 1 ðIap1 Þ against frequency.
8
4
0 -1.8
-1.6
-1.4
-1.2
-1.0
-0.8
-0.6
-0.4
-0.2
0
0.2
DB(I(Vap2)) n samples = 100 n divisions = 20
mean sigma
Fig. 8.
= -0.771189 = 0.475813
minimum 10th %ile
= -1.59304 = -1.45792
median 90th %ile
= -0.834566 = -0.123338
maximum = 0.109475
Variations of the magnitude of all-pass ¯lter at 1.32 MHz.
it is shown in Ref. 22. Since the OPA 860 generally behaves as CCIIþ, the measured voltage compared to the Iap1 is shifted in the phase by 180 . The experiments have been performed with R1 ¼ R2 ¼ 1:2 k and C1 ¼ C2 ¼ 100 pF and the results are shown in Fig. 10. In this case the 90 phase shift is at fo ffi 1:26 MHz, which is very
1250071-11
Magnitude Iap1 (dB)
E. Yuce et al.
0 -3 -6
J CIRCUIT SYST COMP 2013.22. Downloaded from www.worldscientific.com by 211.144.81.67 on 06/16/14. For personal use only.
Magnitude Iap2 (dB)
-9 0 -3 -6 -9 1k
10k
Fig. 9.
100k
1M Frequency (Hz)
10M
100M
1G
The magnitudes of Iap1 and Iap2 with respect to frequency.
Fig. 10. Measured magnitude and phase responses of the Iap1 (color online).
close to the theoretical value of fo ffi 1:3263 MHz. The time-domain response of the measured Iap1 response of the all-pass ¯lter is shown in Fig. 11 in which a sine-wave input of 1 V peak-to-peak and frequency of 1.26 MHz was applied to the ¯lter. From Fig. 11 it can be seen that the phase shift in the Iap1 output against the input is 91 . It is observed from Figs. 57, 10 and 11 that the simulation and experimental results are in close proximity with the ideal ones as expected. Nevertheless, the discrepancy among ideal, simulation and experimental results fundamentally arises from non-idealities of NMOS transistors. 1250071-12
J CIRCUIT SYST COMP 2013.22. Downloaded from www.worldscientific.com by 211.144.81.67 on 06/16/14. For personal use only.
Realization of First-Order CM Filters with Low Number of MOS Transistors
Fig. 11. Measured time domain response of the Iap1 (color online).
6. Conclusion A new CM all-pass ¯lter structure for simultaneously realizing inverting/noninverting ¯rst-order low-pass, high-pass and all-pass ¯lter responses is developed in this paper. The suggested ¯rst-order ¯lter consists of a lower number of components for example two NMOS transistors both in saturation region, two capacitors and two resistors. Major advantages of the proposed con¯guration are low voltage, low noise and high linearity. Nevertheless, it needs matching constraints for all-pass characteristics. Simulation results accomplished via SPICE and experimental tests con¯rm the theoretical ones well as expected. Acknowledgment The research described in the paper was supported by the following projects: P102/ 11/P489, P102/10/P561, P102/09/1681, FEKT-S-11-15, and project SIX CZ.1.05/ 2.1.00/03.0072 from the operational program Research and Development for Innovation. Ing. Norbet Herencsar, Ph.D was supported by the Project CZ.1.07/ 2.3.00/30.0039 of Brno University of Technology. The authors also wish to thank the anonymous reviewers for their useful and constructive comments that helped to improve the paper.
References 1. B. Wilson, Trends in current conveyor and current-mode ampli¯er design, Int. J. Electron. 73 (1992) 573583.
1250071-13
J CIRCUIT SYST COMP 2013.22. Downloaded from www.worldscientific.com by 211.144.81.67 on 06/16/14. For personal use only.
E. Yuce et al.
2. C. Toumazou, F. J. Lidgey and D. G. Haigh, Analog IC Design: The Current-Mode Approach (Peter Peregrinus, London, 1990). 3. G. W. Roberts and A. S. Sedra, All current-mode frequency selective circuits, Electron. Lett. 25 (1989) 759761. 4. B. J. Maundy and P. Aronhime, A novel CMOS ¯rst order all pass ¯lter, Int. J. Electron. 89 (2002) 739743. 5. A. Toker and S. Ozoguz, Tunable allpass ¯lter for low voltage operation, Electron. Lett. 39 (2003) 175176. 6. E. Yuce and S. Minaei, A novel phase shifter using two NMOS transistors and passive elements, Analog Integr. Circuit Signal Process. (ALOG) 62 (2010) 7781. 7. E. Yuce, A novel CMOS-based voltage-mode ¯rst-order phase shifter employing a grounded capacitor, Circuits, Syst. Signal Process. 29 (2010) 235245. 8. S. Minaei and E. Yuce, High input impedance NMOS-based phase shifter with minimum number of passive elements, Circuits, Syst. Signal Process. 31 (2012) 5160. 9. E. Yuce and S. Minaei, Derivation of low-power ¯rst-order low-pass, high-pass and all-pass ¯lters, Analog Integr. Circuits Signal Process. (ALOG) 70 (2012) 151156. 10. R. Arslanalp and E. Yuce, A BJT technology-based current-mode tunable all-pass ¯lter, Microelectron. J. 40 (2009) 921927. 11. A. Mohammadi, A. Ayatollahi and A. Abrishamifar, A new CMOS all-pass phase shifter for phased array systems, IEICE Electron. Express 6 (2009) 504510. 12. S. Ozoguz, T. M. Abdelrahman and A. S. Elwakil, Novel approximate square-root domain all-pass ¯lter with application to multiphase oscillators, Analog Integr. Circuits Signal Process. (ALOG) 46 (2006) 297301. 13. R. Arslanalp, A. T. Tola and E. Yuce, Novel resistorless ¯rst-order current-mode universal ¯lter employing a grounded capacitor, Radioengineering 20 (2011) 656665. 14. R. Arslanalp, A. T. Tola and E. Yuce, Fully controllable ¯rst order current mode universal ¯lter composed of BJTs and a grounded capacitor, Elektronika Ir Elektrotechnika 6 (2011) 6972. 15. B. Metin, K. Pal and O. Cicekoglu, All-pass ¯lter for rich cascadability options easy IC implementation and tunability, Int. J. Electron. 94 (2007) 10371045. 16. S. M. Al-Shahrani, CMOS wideband auto-tuning phase shifter circuit, Electron. Lett. 43 (2007) 804806. 17. S. Minaei and E. Yuce, All grounded passive elements current-mode all-pass ¯lter, J. Circuits, Syst. Comput. 18 (2009) 3143. 18. S. Minaei and E. Yuce, Novel voltage-mode all-pass ¯lter based on using DVCCs, Circuits, Syst. Signal Process. 29 (2010) 391402. 19. W. Tangsrirat and T. Pukkalanun, Digitally programmable current follower and its applications, Int. J. Electron. Commun. (AEU) 63 (2009) 416422. 20. E. Yuce and S. Minaei, Universal current-mode ¯lters and parasitic impedance e®ects on the ¯lter performances, Int. J. Circuit Theor. Appl. 36 (2008) 161171. 21. W. M. C. Sansen, Analog Design Essentials (Springer, Dordrecht, The Netherlands, 2006), pp. 117131. 22. J. Koton, N. Herencsar and K. Vrba, Electronically tunable pure current-mode low-pass ¯lter, Proc. 6th Int. Conf. Electrical and Electronics Engineering (ELECO 2009), Bursa, Turkey (2009), pp. 260262.
1250071-14
