E-mail: vitalij | dmarien | egor | mgoessel @cs.uni-potsdam.de. Abstract. In this paper a new code-disjoint totally self-checking carry-select adder with low area ...
Self-Checking Code-Disjoint Carry-Select Adder with Low Area Overhead by Use of Add1-Circuits ∗ V. Ocheretnij
D. Marienfeld
E. S. Sogomonyan †
M. Gössel
University of Potsdam, Department of Computer Science, Fault Tolerant Computing Group, 14439 Potsdam, Germany E-mail: vitalij | dmarien | egor | mgoessel @cs.uni-potsdam.de Abstract In this paper a new code-disjoint totally self-checking carry-select adder with low area overhead is proposed which is based on the simplified design of carry-select adders by use of Add1-circuits as proposed in [1, 2]. The area overhead for the proposed adder is only 40% of a traditional carry-select adder without error detection.
1. Introduction With the rapidly shrinking dimensions and the diminishing voltage levels of VLSI circuits are becoming increasingly sensitive to temporary or transient faults. These faults are caused for instance by crosstalk, power supply noise, alpha-particles and other reasons. These transient faults can be only detected by on-linedetection or concurrent checking but not by testing [3, 4]. If a transient fault occurs in a node of a combinational circuit an error occurs if, due to this fault, an erroneous value is captured in a latch or a register. According to [5] the effects of transient faults in the combinational parts of a circuit are limited by the following conditions 1. There must be a sensitized path from the location of the fault to the latch 2. There must be a significant duration and amplitude of the faulty signal ∗ This
paper was supported by a research grant of Intel professor of the University of Potsdam
† Guest
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3. The timing of the transient fault must be such that the erroneous value arrives at the input of the latch within the “latching window”. Therefore the memory part of a circuit is much more susceptible to soft errors than the combinational part. If a circuit is concurrently checked then it is therefore very desirable not only continuously to monitor the combinational part but also to monitor the contents of the latches or registers of the circuit. An excellent description of this situation is given for instance in [6]. Adders are essential parts of every computer. Therefore the design of self-checking adders is of special interest. In this paper we are interested in the design of a codedisjoint totally self-checking carry-select adder with a low area overhead for which the registers of the adder also checked. According to [7] carry-select adders belong to the fastest adder types. For carry-select adders very few self-checking designs are known so far. The first self-checking carry-select adder was proposed in [8]. In this design time redundancy was used for error detection. Carry-select adders with concurrent error detection which are not code-disjoint and not totally self-checking are described in [9] and [10]. In [9] modulo 3 checking was used. Taking into account that the outputs of the duplicated adder blocks of a carry-select adder for carry-in signals 0 and 1 differ arithmetically by 1 in [10] the outputs of the duplicated adder blocks are compared by a self-checking two-rail checker. A low area overhead can be achieved for the price that the multiplexers at the outputs are not checked. Recently a code-disjoint totally self-checking carryselect adder was proposed in [11]. In [11] the duplicated
adder blocks of the carry-select adder are implemented as sum-bit duplicated adders. But the area overhead for this design is high. To reduce the area overhead for a code-disjoint totally self-checking carry-select adder we propose in this paper a new self-checking carry-select adder which is based on the simplified design of a carry-select adder by use of Add1circuits as proposed in [2]. Since we need as well the sum-bits as the inverted sum-bits as inputs for the corresponding Add1-circuits according to [2] we implement the adder blocks with the carry-in signals 0 as code-disjoint sum-bit duplicated adders according to [12]. The proposed self-checking adder is code-disjoint with respect to parity encoded operands and besides all internal single stuck-at faults, all odd input errors, all odd and even errors at the outputs which are stored in the output registers are also immediately detected. The paper is organized as follows. In chapter 2 a carryselect adder without error detection is recapitulated. Also the Add1-circuit according to [2] is discussed. In chapter 3 the proposed code-disjoint totally self-checking adder is introduced. The self-checking property of the adder is shortly explained in chapter 4. Experimental results are discussed in chapter 5. Conclusions are drawn in chapter 6. We assume that the reader is familiar with the basic notions and notations of self-checking design which are for instance described in [13].
2. Carry-Select Adder without Error Detection A carry-select adder is block-wise organized, and in a traditional design all the adder blocks besides the least significant one are duplicated into a first adder block with carry-in signal 0 and a second adder block with carry-in signal 1. These duplicated adder blocks compute for the same group of bits of the input operands for their respective carry-in signals 0 and 1 the corresponding sum-bits and the carry-out signals. By multiplexers which are controlled by the in the preceding block selected carry-out signal the appropriate group of sum-bits and the correct carry-out signal are determined. Fig. 1 shows a traditional carry-select adder with a block size of 4. In the first adder block AB1 which is not duplicated the input bits a[0,3] = a0 , a1 , a2 , a3 and b[0,3] = b0 , b1 , b2 , b3 are added into s[0,3] = s0 , s1 , s2 , s3 . The carryout signal of this block is c3 . The second adder block, as all the other adder blocks, is duplicated into the adder blocks AB02 and AB12 . In the adder block AB02 with the carry-in sig-
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nal 0 the input bits a[4,7] = a4 , . . . , a7 and b[4,7] = b4 , . . . , b7 are added into the sum-bits s0[4,7] = s04 , s05 , s06 , s07 . The resulting carry-out signal of this block is c07 . In the adder block AB12 with the carry-in signal 1 the same input bits a[4,7] and b[4,7] are added into the sum-bits s1[4,7] = s14 , s15 , s16 , s17 , and the resulting carry-out signal of this block is c17 . Depending on the carry-out signal c3 of the preceding block the multiplexers select the sum-bits s[4,7] and the carry-out signal c7 as the outputs of these blocks. The next adder block is also duplicated. In the adder block AB03 with the carry-in signal 0 the input bits a[8,11] and b[8,11] are added into the sum-bits s0[8,11] with the carry-out signal c011 . In the duplicated adder
block AB13 for the carry-in signal 1 the same input bits a[8,11] and b[8,11] are added into the sum-bits s1[8,11] , and the resulting carry-out signal of this block is c111 . Depending on the carry-out signal c7 of the preceding block the multiplexers select the sum-bits s[8,11] and the carry-out signal c11 . The other blocks of the carry-select adder are similar. For the outputs of the duplicated adder blocks we have c17 s17 s16 s15 s14 c111 s111 s110 s19 s18
= c07 s07 s06 s05 s04 + 1, = c011 s011 s010 s09 s08 + 1, .. . .
By adding a 1 to the sum-bit and carry-out outputs of the adder blocks with a carry-in signal 0 the least significant bits of these adder blocks are inverted until the first 0 is reached. Thus we have for example 0 1 1 0 1 + 1 = 0 1 1 0 1 = 0 1 1 1 0 or 1 0 1 1 1 + 1 = 1 0 1 1 1 = 1 1 0 0 0. Based on this simple fact it was proposed in [1] to replace the second duplicated adder blocks with the carry-in signal 1 by much more simple Add1-circuits. In [1] the inputs of an Add1-circuit are not the corresponding bits of the input operands a and b but the sum-bits of the corresponding adder block and the carry-out signal of the preceding block. An efficient implementation of an (modified) Add1circuit was given in [2] and shown in Fig. 2 for a four bit adder. The transistor logic block T LB in Fig. 2 allows in a very simple way to implement these (modified) Add1circuits. In the design proposed in [2] as in [1] the adder blocks with the carry-in signals 1 are replaced by corresponding Add1-circuits. But in [2] it is assumed that the adder blocks with the carry-in signals 0 compute as well the sum-bits as the inverted sum-bits. The inputs of the Add1circuit are now the sum-bits and also the inverted sum-bits of the corresponding adder block and the carry-out signal of the preceding adder block. The Add1-circuit now only
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Figure 1. Traditional carry-select adder without error detection
component-wise selects the appropriate sum-bits from the sum-bits and the inverted sum-bits which are already generated by the corresponding adder block with the carry-in signal 0. By use of the Add1-circuits the area for 64 bit carry-select adder without error detection can be reduced by about 24%. The additional delay caused by the Add1circuits blocks is almost negligible. adder block
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Figure 2. Multiplexer-based Add1-circuit for 4 bits from [2]
3. Description of the Proposed Adder In Fig. 3 the proposed code-disjoint self-checking carryselect adder is shown. The adder consists of k adder blocks SD0 , SD1 , . . . , SDk−1 with a constant carry-in signal 0. To be concrete Fig. 3 shows a 64-bit adder consisting of 6 blocks SD0 , SD1 , . . . , SD5 of lengths 8, 8, 12, 12, 12, 12. Only the blocks SD0 , SD1 and SD5 are explicitly shown. Depending on the concrete library and the technology used other block lengths may be useful. The input operands a = a0 , . . . , a63 and b = b0 , . . . , b63 are parity encoded with the respective
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input parities pa = a0 ⊕ . . . ⊕ a63 and pb = b0 ⊕ . . . ⊕ b63. The propagate generator generates the propagate signals p0 = a0 ⊕ b0, . . . , p63 = a63 ⊕ b63 . These propagate signals are XOR-ed into p(a ⊕ b) = p0 ⊕ . . . ⊕ p63 and compared with the XOR-sum pa ⊕ pb of the input parities. Odd errors at the inputs and all single faults within the propagation generator are detected by comparing p(a ⊕ b) and p a ⊕ pb . The propagate signals p[0,7] = p0 , . . . , p7 , . . . , p[52,63] = p52 , . . . , p63 which are already checked are used as inputs for the "sum-bit duplicated" adder blocks SD0 , . . . , SD5 . The sum-bit duplicated adder block SD0 implements for the constant carry-in signal 0 the sum-bits s0[0,7] = s00 , . . . , s07 , the
inverted sum-bits s0[0,7] = s00 , . . . , s07 and also two identical
carry-out signals c07 1 and c07 2. Similarly the other adder blocks SD1 , . . . , SD5 implement also for constant carry-in signals 0 the corresponding sum-bits, the inverted sum-bits and two duplicated identical carry-out signals. The internal structure of these blocks will be described later. The sum-bits s0[0,7] and the inverted sum-bits s0[0,7] of the adder block SD0 are the least significant 8 sum-bit outputs s[0,7] and the inverted sum-bit outputs s[0,7] of the adder. The outputs of the sum-bit duplicated adder block SD1 are the inputs of the T LB1 and T LB1 circuits. The signals * of the T LB1 (T LB1 )-circuit are the control signals for the multiplexer selecting bitwise from s0[8,15] and s0[8,15] the value s1[8,15] (s1[8,15] ). Thereby the blocks T LB1 and T LB1 are identical. Finally the carry-out signal c07 1 of the block SD0 selects the resulting sum s[8,15] by a multiplexer from s0[8,15]
and s1[8,15] , and the carry-out signal c15 1 from c015 1 and c115 1. The inverted sum-bits s[8,15] and the carry-out signal c15 2 are selected by c07 2 from s0[8,15] and s1[8,15] , and from c015 2 and c115 2 respectively. In a similar way the sum-bits s[16,27] , s[16,27] , . . . , s[52,63] , s[52,63] and the corresponding duplicated carry-out
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Figure 3. Proposed code-disjoint self-checking carry-select adder
signals of the other blocks are determined. The carry-out signals of the most significant block SD5 are not implemented in Fig. 3. In Fig. 4 the sum-bit duplicated adder block SD0 is shown. The sum-bits s[0,7] , the inverted sum-bits s[0,7] and the duplicated carry-out signals c07 1 and c07 2 are realized. The corresponding propagate signals p[0,7] = p0 , . . . , p7 are only once implemented in the propagate generator, and, as already pointed out, checked by comparing p a ⊕ pb with p(a ⊕ b). The adder cells are designed as fast carry-ripple adder cells according to [14]. The internal carries ci within the block are duplicated into c1i , c2i and c3i , c4i for even and odd adder cells which are slightly different. The delay for the carry-propagation for one stage within the block is reduced to the delay of a single NAND-gate. The adder blocks SD1 , . . . , SD5 are implemented in the same way.
4. Self-Checking Property It can be shown that the proposed adder is totally selfchecking for single stuck-at faults and code-disjoint with respect to odd input faults. All single (and odd) input errors as well as single faults of the XOR-gates of the propagate generator are detected by comparing the input parity with the XOR-sum of the propagate signals. All errors due to single stuck-at faults in the duplicated parts of the adder blocks, errors in the T LB-circuits
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and stuck-at faults in the multiplexers are always detected by comparing the sum-bits and the corresponding inverted sum-bits. The correctness of the (duplicated) carry-out values is checked by the succeeding blocks. It can be also shown, that every single stuck-at fault is testable. Also all even and odd errors at the outputs s and s and all soft errors in the output registers of the adder are detected.
5. Experimental Results The experimental results are shown in Table 1. Area and delay of a traditional carry-select adder, of a code-disjoint self-checking sum-bit duplicated adder according to [11] and of the proposed code-disjoint self-checking carry-select adder are compared. The area overhead for the proposed adder is only 40% of a traditional carry-select adder without error detection compared to 71% of the adder described in [11]. The delay for the proposed code-disjoint carry-select adder compared to the traditional carry-select adder increases by 4.7%.
6. Conclusions It was shown in this paper how a code-disjoint completely self-checking carry-select adder with low area overhead can be designed by use of the T LB-blocks of the Add1-
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Figure 4. Sum-bit duplicated adder block SD0
Table 1. traditional code-disjoint self-checking carry-select adder carry-select adder without error detection according to [11] proposed adder area delay, ns
1
2
3
2083 (100%) 14.96 (100%)
3559 (171%) 14.98 (100.1%)
2925 (140%) 15.67 (104.7%)
circuits as proposed in [1, 2]. The adder blocks are implemented as fast carry-ripple adders. The propagation signals are implemented only once and checked against the input parity of the parity encoded input operands. All internal single stuck-at faults and all odd errors at the inputs are immediately detected. Also all even and odd errors at the sum-bit and inverted sum-bit outputs and all soft errors in the output registers of the adder are detected. Compared to a traditional carry-select adder without error detection the area of the proposed adder increases by only 40% with an increase of the delay of 4.7%.
References [1] T. Y. Chang and M. J. Hsiao, “Carry-select adder using single ripple-carry adder,” in IEE Electronic Letters, vol. 34, No.22, pp. 2101–2103, 1998. [2] Y. Kim and L. S. Kim, “A low power carry-select adder with reduced area,” in ISCAS, pp. 218–221, 2001.
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[3] L. Anghel, M. Nicolaidis, and I. Alzaher-Noufal, “Self-Checking Circuits versus Realistic Faults in Very Deep Submicron,” in 18th VLSI Test Symposium, pp. 55–63, 2000. [4] C. Metra, M. Favalli, and B. Ricco, “On-line Detection of Logic Errors due to Crosstalk, Delay and Transient Faults,” in Proceedings of ITC, pp. 524–533, 1998. [5] P. Liden ´ and et al., “On Latching Probability of Particle Induced Transients in Combinational Networks,” FTSC, pp. 340–349, 1994. [6] K. Mohanram and N. A. Touba, “Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits,” in Proceedings of ITC, pp. 803–901, 2003. [7] Z. Chen and I. Koren, “Techniques for Yield Enhancement of VLSI Adders,” in Proceedings of Application Specific Array Processors, pp. 222–229, 1995. [8] F.-H. W. Shih, “High performance self-checking adder having small circuit area,” in US PS 5,018,093, 1991.
[9] V. Ocheretnij, M. Gössel, E. S. Sogomonyan, and D. Marienfeld, “A modulo p checked self-checking carry-select adder,” in 9th International On-line Testing Symposium, pp. 25–29, 2003. [10] B. K. Kumar and P. K. Lala, “On-line Detection of Faults in Carry-Select Adders,” in Proceedings of International Test Conference, pp. 912–918, 2003. [11] E. S. Sogomonyan, D. Marienfeld, V. Ocheretnij, and M. Gössel, “A New Self-checking Sum-bit Duplicated Carry-select Adder,” in Design, Automation and Test in Europe Conference - DATE, pp. 1360–1361, 2004. [12] D. Marienfeld, V. Ocheretnij, M. Gössel, and E. S. Sogomonyan, “Partially duplicated code-disjoint carryskip adder,” in 7th IEEE International Symposium on DEFECT and FAULT TOLERANCE in VLSI Systems, pp. 78–86, 2002. [13] P. K. Lala, Self-Checking and Fault-Tolerant Digital Design. Morgan Kaufmann Publishers, San Francisco, CA, 2001. [14] M. Smith, Application-specific integrated circuits. Adison Wesley, Reading, MA, 1997.
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