Simulation and Modelling of Digital Delay Locked Loops

Simulation and Modelling of Digital Delay Locked Loops Rui L. Aguiar, Dinis M. Santos Dep. de Electrónica e Telecomunicações, Universidade de Aveiro, 3810 Aveiro, Portugal E-Mail: [email protected], [email protected] Abstract - This paper discusses some results for simulation and modeling of charge-pump Delay Locked Loops. A novel model based on a sampled-time approach is presented, and used for jitter analysis. The model is applied to input signal jitter, internally generated jitter and is further extended to handle jitter effects related with the control charge-pump. Behavior models for simulation purposes are derived from the theoretical model, and design considerations based on these are presented. a

I. INTRODUCTION Recently, delay locked loops (DLLs) have been increasingly used in many applications. For instance, DLL usage has been reported in clock distribution circuits [1,2], multiphase clock generation [3] and clock recovery circuits [4]. In all these applications, jitter analysis is of paramount importance for good designs, and DLLs were used as they introduce small jitter in signals and are easy to implement in digital circuits. In particular, DLL designs with charge-pump (CP) phase detectors (PD) have shown to originate systems with good characteristics. Thus charge-pumped DLLs have become increasingly used as elementary blocks in clock related circuits.

A. DLL Delay Model Our modeling is oriented towards DLLs with CP phase detectors, due to its increasing usage in clock-related applications. Fig. 1 presents a model for a DLL [7]. A phase detector (PD) using a charge-pump circuit controls a voltage controlled delay line (VCDL); this phase detector measures the phase difference between input and output signals of the VCDL. For most applications, the input signal is a clock waveform. The following relations can be derived from simple inspection of the model, when the DLL is synchronized:

Φ out ( t ) = Φ in ( t − αT ) − K VCDLV (t ) c Vc (t ) =

(1)

Φ in ( t ) − Φ out ( t ) t ∫ I c (t )dt C −∞

(2)

where α (˜1) is the total delay (in number of clock periods) of the VCDL, VC(t) is the control voltage applied to the VCDL, KVCDL is the VCDL gain (dΦout/dVC)1, and Ic(t) is the current applied to the capacitor C in the control node. The PD will create short impulses (Up or Down [8]) depending on the phase difference between Φin and Φout. As these are digital signals, their difference will be either 0, or ±1, and this will change the charge-pump state. Ideally, when the DLL is near lock, the PD impulses will

Φ in

VCDL

PD

Charge Pump

∆T

+

∆T

Vc C

-

∆T

Φ out

∆T

Current DLL models [5,6] are based on more traditional PLL analysis. They do not provide design insight for DLL design or DLL jitter mechanisms, as they are either extrapolations on PLL behavior or, at most, represent practical knowledge about DLL performance. As DLL usage increases and covers increasingly stringent conditions, these models present their limitations. CMOS applications requiring high clock frequencies led to the on-going work in DLL modeling here described. A discrete-time model for charge-pump DLLs is presented in Section II. This model is applied to jitter analysis, and overcomes the shortcomings of previous approaches, as the line delay and the phase detector are now considered. This analytic model is used to derive behavioral models for DLL simulation, presented in Section III. The paper presents simulation results supporting these proposed models, and explores these in order to achieve some DLL design guidelines. Finally, conclusions are presented in Section IV.

II. DLL MODELING

Fig. 1. Charge-Pump DLL model. a

This work has been sponsored partially by Portuguese programme Praxis XXI, through the Genclock project.

1

In our expressions we assumed that as the control voltage increases, the VCDL delay will decrease.

have a quasi-regular periodicity. A sampled time model [7,9] can approximate this behavior, where time impulses are modeled by a quantitative value per (periodic) sample. We will assume that the PD will only work on one of the clock edges, and use this period as sampling rate. As the control voltage should only change during the time when the PD input waves are out-of-phase, we can also approximate VC by its sampled value. Thus, and applying the discrete Z-transform to this discrete model, we obtain the phase transfer function (TF):

H ( z) =

Φ out ( z ) z −α − K T z −1 1 − K T z α −1 = = Φ in ( z ) 1 − K T z −1 z α − K T z α −1

(3)

where the loop gain KT is given by KVCDL * KCP, with KCP the charge-pump phase detector gain. Note that KCP is much smaller than 1 in typical integrated circuits for clock related functions. This expression readily shows the effect of total line delay: larger number of poles in origin (representing the larger delay) and zeros will appear in the phase TF. There are three main sources for output jitter in a DLL: 1) jitter in the input clock, which is becoming important for clock distribution applications, as several distribution methods are using interconnections of DLLs [1,2]. 2) jitter generated internally in the VCDL, caused by noise in each delay element, or induced in those elements by power supply noise; 3) jitter generated by noise present on the control voltage VC; this noise will change the total VCDL delay, and thus will translate as jitter at the output of the VCDL. Both phase detector induced problems (such as those caused by noise in the phase detector circuitry or the problems that may appear due to clock duty-cycle) and charge-pump inaccuracies can be modeled in our approximation as noise injected in the control voltage. Jitter behavior can be analyzed with the simplified model depicted in Fig. 2, where these jitter sources are modeled as additive stochastic processes inserted in the DLL model previously described. + ∆T

η Vc + PD -

Charge Vc Pump C

+

∆T

= +

∆T

Θ ∆T

∆T

Θ in

Different TFs can be derived for each jitter source [7], using the approximation strategy already described: Θ ( z ) z −α − K T z −1 1 − K T z α −1 , (4) J in ( z ) = out = = Θ in ( z ) 1 − K T z −1 z α − K T z α −1 for the input jitter TF; Θ ( z) KT (1 − z −α ) , (5) JVCDL ( z ) = out = ΘVCDL ( z ) (1 − z −1 )(1 − KT z −1 ) for the jitter internally generated by the delay elements; and Θ ( z) (6) JVC ( z ) = out = KVCDL , ΘVC ( z ) for the jitter generated by noise in the control voltage. Total expressions for r.m.s. output jitter can be derived from these jitter TFs, under the jitter premises above, assuming gaussian noise [7]. Thus, assuming gaussian jitter, and low values of KT, we achieve, from (4) and (5):

σin =

B. DLL Jitter Models

Φ in

In Fig. 2, Θin is the input clock jitter, Θ∆T is the jitter generated in each DLL delay element, ηVc is the control voltage noise; and Θout is the DLL output jitter.

Φ out+Θ out

Fig. 2. Charge-Pump DLL jitter model

2π σδ T (1 − KT2 )

σ VCDL =

2π T

(K

α T

σε (1 − K ) 2 T

)

(

)

− 1 + KT2 1 − KT2α ≈ 2

≈

2π σ T δ

2π 1 + KT2 σδ T 1 − KT2

(7)

(8)

where σδ is the input signal jitter, σε is the internally generated jitter, and σin and σVCDL are the output jitters originating by each case, respectively. (The output jitter for the control voltage jitter is obvious from (6).) This model is able to provide better insight into internal DLL behavior, as the equations above incorporate both control and delay effects into DLL performance, and are able to differentiate different jitter sources and effects. For instance, a traditional statement is "a DLL is inherently stable". This is the result of minimizing the importance of the control loop in DLL performance. From (3), the stability condition for charge-pump DLLs can easily be derived: KT < 1. (Note that stability does not depend on total line delay, but only on the loop characteristics.) In fact, typical DLL designs are quite far from this limit value: KT values smaller than 10-5 are common (e.g., [3,5]). Under this condition, the results achieved with this model can be shown to be similar to those previously presented in the literature [5], leading to jitter accumulation factors approximately equal to one. Both (4), (7) and (5), (8) lead to this conclusion. Note that, for instance, if (7) shows that a DLL has a jitter accumulation factor of approximately one for low values of KT, it also provides more information. This expression also shows the overall behavior of input originated jitter mechanisms in a DLL: there is a component related with the immediate effect input jitter causes in the DLL control, and another component related with the propagation of this jittered signal across the VCDL, and their respective relationships are dependent on the loop gain and total line delay.

1 In1

2 In2

AND 1

Logical Operator

OR

OR

Logical Operator1

Logical AND Operator4

1 Out1

Logical Operator2

0 .8

0 .6

0 .4

Memory

Fig. 3. Matlab model for the Müller C-element.

0 .2

0 40

60

80

100

120

Fig. 5. Output clock jitter, for normalized control voltage noise of 0.08, in an eye-diagram representation.

TABLE I Output clock jitter in functions of normalized control voltage noise.

Noise Peak-to- peak Jitter

0.02 1

0.05 2

0.08 4

0.1 5

0.2 9

most important configuration variables are the switching thresholds and the current limitations. Fig. 4. Charge-Pump DLL simulation model in Simulink. The VCDL simulated had four controlled delays. Noise sources were assumed as additive gaussian.

III. SIMULATION AND BEHAVIORAL MODELS The conceptual model presented in Fig. 1 has been used for deriving behavior models, implemented using Matlab and Simulink ®. These models are used to explore design choices of several DLL parameters, and validating theoretical conclusions extracted from the analytical models. The Simulink model was derived using a “continuous” time approach: simulators current capabilities allow for the usage of time-domain simulation to confirm our discrete time approximations. Convergence problems (and a DLL naturally presents an algebraic loop, which complicates simulation) can be mostly solved by the usage of fixed-time methods with small time steps – at the cost of simulation efficiency. Nevertheless, we have used simulation steps of 1ps with good simulation times in high-performance PCs. The blocks modeled were based on design insights from a real DLL design and assumed a phase detector with a Müller C-element [3]. Thus three custom blocks were completely designed: a line delay element, a Müller C-element, and a charge-pump. Noise sources and signal processing were implemented with exiting Matlab toolboxes. Voltage and time values were normalized (to 1V and 1ns, respectively). The delay element was modeled as a Matlab transport delay, followed by a strangled current output block. An ideal threshold comparator is included at the output, as large gain inverters are common on real delay elements outputs to increase edge slopes. These blocks are configurable, and the

The C-element was modeled as an ideal unit, resorting to a digital description of its function. This model does not have configurable parameters. Fig. 3 presents the model for the Celement, as way of illustration. The phase detector was implemented with this element and some digital logic. A custom-designed rate limiter modeled the charge-pump operation. The up and down charge currents of the CP (always assumed equal, as is usually desired in CP design) are configurable, as well as the initial output voltage, for convergence speed-up considerations. Noise sources were added to these units, assuming additive voltage noise. Following the diagram depicted in Fig. 2, these (normalized) noise sources were transformed in jitter values both for the input clock jitter and the VCDL internally generated jitter. Fig. 4 shows the total simulation circuit used, with the several jitter sources clearly identified. The input jitter generation is clearly presented in the upper side. Simulations were run on this model quite effectively, and total output jitter could be calculated for typical DLL parameters, passing the output simulation back into Matlab. The jitter introduced by these additive voltage noises in the delay line is not expected to be of major importance, as large gain inverters are used in delay elements, which filters circuit noise effects. The effect of these noise sources in the phase of the clock signal is small, and thus, from (7) and (8), output jitter is expected to be low. This has been shown in our simulations, and with reasonable values of noise, both input and internally generated jitter led to negligible output jitter. These two situations imply that the total size of the VCDL is not much relevant (in a first approximation) to jitter mechanisms in a DLL. Many delay elements can theoretically

be connected serially (and this is a trend in clock distribution circuits) without large increase in clock jitter – as long as no jitter appears in the line. If a delay element introduces jitter in the clock, then all VCDL elements will propagate this jittered signal, and all VCDL connections after this element will have large jitter values. The feedback mechanism in the DLL will not reduce this jitter. The situation is even more demanding with noise in the control voltage. Output jitter appears immediately, even with low noise values, as Fig. 5 illustrate. Simulations also showed, in accordance with (6), that output jitter increases linearly with this noise, as presented in Table I (discrepancies are due to numerical precision). Thus it is of great importance to avoid noise in the control voltage node, as it may impair overall DLL performance. It should be noted that, even in a noiseless circuit, the chargepump behavior leads to the existence of noise in this node [7], which should be minimized. Our simulation model presents its limitations at large values of noise. As noise levels increase, our model starts to output large clock signal oscillations, as no setup times are required for threshold changes in the delay elements. As noise levels increase, inexistent transitions are forced at these elements, and the model becomes unsuitable for these circumstances. A DLL, previously implemented for high-speed serialparallel conversion [3], was used to validate these results. The high-speed nature of this specific design, and its selfcontained circuitry posed some problems to jitter measurements, and especially to the identification of the several jitter sources. In this system, input jitter seemed not to have much importance, as predicted, but both control voltage jitter and internally generated jitter seemed to be of importance. As this last fact was unexpected, we made some electrical simulations of the DLL, trying to validate these results. The electrical simulations supported our model, which lead us to conclude that the internally generated jitter has a very large amplitude in this circuit - which is supported by the large power supply noise present (≈1V), and the simultaneously switching noise this reveals. Our experimental jitter analysis results were then found to be in general concordance with the models here derived, although the model does not predict its exact values due to the nature of the approximations made. This shows another limitation of the model. It does not present the relationship between a specific circuit and its jitter performance: the mechanisms how electrical noise is converted in signal jitter in the delay elements have to be known for model parameterisation (for instance, as shown in [10]) IV. CONCLUSIONS A new sampled-time model for DLL jitter analysis has been derived. This model incorporates more complex aspects than previously reported models. Jitter analysis achieved with this model show the validity of previous results, with typical design parameters. However, this model increases the

understanding of the DLL and its performance in terms of jitter, providing insight for challenging high frequency designs. This model has also been extended to a behavioral model in Matlab. Simulations were run on this model quite effectively, and total output jitter could be calculated for typical parameters. These results have been confronted with those achieved by the sampled-time model, and have been found to be in general concordance. The model shows that, for typical design parameters, input jitter and jitter internally generated by delay elements are almost unaffected by the DLL. This jitter will be kept in the line as it appears in the clock. Furthermore, our model shows that voltage control induced jitter plays an important part on the total output jitter, and any electrical noise in this node will create jitter in the clock signal. These considerations present some constraints on present trends in using DLL-based architectures for high frequency clock distribution. REFERENCES [1] R.L. Aguiar, D.M. Santos, "Multiple target clock distribution with arbitrary delay interconnects", Electronic Letters, Vol. 34, nº 22, Oct. 1998, pp. 2119-2120. [2] A. Shibayama et all: "Device deviation tolerant over1GHz clock distribution scheme with skew-immune racefree impulse latch circuits", IEEE Intl. Solid-State Conf. ISSCC’98, Feb. 98, pp. 402-403. [3] A.M. Sarsfield, E. Vasconcelos, R.L. Aguiar, D.M. Santos, "Link para fibra óptica a muito alta velocidade", I Conferência Nacional de Telecomunicações, Aveiro, Apr. 1997, pp. 443-446. [4] Thomas H. Lee, John F. Bulzacchelli, "A 155-MHz clock recovery delay- and phase-locked loop", IEEE Journal of Solid-State Circuits, Vol. 27, Dec. 1992, pp1736-1746. [5] B. Kim, T.C. Weingandt, P.R. Gray, "PLL/DLL system noise analysis for low jitter clock synthesizer design", ISCAS'94, 1994 IEEE International Symposium on Circuits and Systems, 1994, pp. 151-154. [6] B. Ravazi, "Design of monolithic phase-locked loops and clock recovery circuits - A tutorial", Monolithic PhaseLocked Loops and Clock Recovery Circuits, IEEE Press, 0-7803-1149-9, 1996. [7] R.L. Aguiar, D.M. Santos, "Modelling charge-pump delay locked loops", ICECS'99, 6th IEEE International Conference on Electronics, Circuits and Systems, Cyprus, Sep. 1999, in press. [8] F.M. Gardner, "Charge-pump phase-lock loops", IEEE Trans. On Communications, Vol. 28, n.11, Nov. 1980, pp- 1849-1858. [9] J.P. Hein, J.W. Scott, "z-Domain model for discretetime PLL’s", IEEE Trans. On Circuits and Systems, Vol. 35, Nov 1988, pp 1393-1400. [10] T.C. Weingandt, B. Kim, P.R. Gray, "Analysis of timing jitter in CMOS ring oscillators", ISCAS'94, 1994 IEEE International Symposium on Circuits and Systems, 1994, pp. 191-194.