IEEE TRANSACTIONS ON ELECTRONICS PACKAGING MANUFACTURING, VOL. 32, NO. 4, OCTOBER 2009
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Thermal-Mechanical Process Simulation of an Advanced NCF Technology Hsien-Chie Cheng, Member, IEEE, Wan-Yu Hwang, Kuo Shu Kao, Jimmy Tsang, Sterling S. Yang, Chao-Chyun An, and Simon M. Chang
Abstract—The paper introduces an advanced nonconductive film (NCF) typed FC technology employing a novel compliant composite interconnect structure. The interconnect reliability and bondability of the technology are demonstrated through experimental thermal humidity (TH) test in conjunction with a two-point daisy chain resistance measurement. The alternative goal of the study aims to look into the insight of the thermal-mechanical behaviors of the novel packaging technology during NCF bonding process and thermal testing through numerical modeling and experimental validation. For effectively simulating the bonding process, a process-dependent finite-element (FE) simulation methodology is performed. The validity of the proposed methodology is verified through several experimental methods, including a Twyman–Green (T/G) interferometry technique for warpage measurement, and a four-point probe method for contact resistance measurement. At last, a design guideline for improved process-induced thermal-mechanical behaviors is presented through parametric FE analysis. Both numerical and experimental results demonstrate the feasibility in applying the novel compliant interconnects to achieve a proper contact stress at various temperature environments so as to hold a low and stable connection resistance at elevated temperature. Most importantly, the novel interconnects survive the 85 C/85%RH TH test for 500 hours. Index Terms—Contact resistance measurement, finite-element (FE) modeling, flip chip, interconnect reliability, nonconductive film, process simulation, Twyman–Green interferometry technique.
I. INTRODUCTION CCORDING to the prediction of International Technology Roadmap for Semiconductors (ITRS) in 2007, the I/O pitch would decrease to 20 m beyond 2011. Unfortunately, the strict target might not be straightforwardly attained by the state-of-the-art I/O interconnection technologies. For example, the widely used solder/underfill-based FC technology is
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Manuscript received July 31, 2008; revised February 03, 2009 and June 04, 2009. Current version published October 07, 2009. This work was supported by the Taiwan TFL LCD Association (TTLA), and the National Science Council, Taiwan, under Grants NSC98-2221-E-035-024. This work was recommended for publication by Associate Editor S. Liu upon evaluation of the reviewers comments. H. C. Cheng is with the Department of Aerospace and Systems Engineering, Feng Chia University, Taichung 407, Taiwan (e-mail:
[email protected]). W. Y. Hwang is with the Thermal/Stress Characterization Section, Siliconware Precision Industries Co., Ltd., Taichung 427, Taiwan. K. S. Kao, J. Tsang, and S. S. Yang are with the Taiwan TFT LCD Association, Hsinchu 310, Taiwan. C. C. An and S. M. Chang are with Display Technology Center, ITRI, Hsinchu 310, Taiwan. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TEPM.2009.2030958
no longer effective as I/O pitch becomes less than 80 m mainly because of underfill-filling problems, causing low throughput. On the other hand, the adhesive-based FC technologies (e.g., [1]–[7]) can be an engaging choice for very fine-pitch interconnection. In contrast to the conventional solder/underfill-based technology, the adhesive-based FC technologies imply several favorable features, including low cost, good manufacturability, structural simplicity, reworkability, high I/O densities, and most importantly, potential of ultra-fine-pitch interconnections. Up to date, the adhesive-based FC technologies have been widely applied in some applications. For example, the chip-onglass (COG) packaging technology using an anisotropic conductive film/adhesive (ACF/A) has been in widespread use in LCD industry. ACF/A contains an adhesive polymer matrix and uniformly dispersed fine, flexible electrically conductive particles that are not present in the nonconductive film/adhesive (NCF/A). However, as a result of the tiny conductive particles, the ACF/A-based packaging technology might suffer from lateral electrical conduction when I/O pitch is decreased down to below 40 m. It is thus not ideal for ultra-fine-pitch applications. Besides, an excessive contact pressure may increase the risk of failure of these fine particles. Note that collapsed particles are difficult to maintain required contact performance, especially at elevated temperature. On the contrary, the NCF/A technologies seem more appropriate and practical for use in I/O pitch below 40 m because of the absence of these tiny electrically conductive particles. In spite of the appealing advantage, the lack of the compliant tiny conductive particles may unfortunately lessen the structural compliance of the I/O interconnects, thus being incapable of maintaining robust contact or electrical continuity at elevated temperature due to the thermal expansion of the adhesive. Consequently, the associated yield and reliability issues of the NCF/A technology remain a great concern. For easing the above technical difficulties, an advanced NCFtyped FC technology (briefly termed as the NCF technology or COG assembly) is introduced in the study. The packaging technology incorporates a novel compliant interconnect structure, comprising a patented composite micro-bump. The composite micro-bump (U.S. patent: 6,084,301) is composed of a polyimide (PI) kernel, overcoated by metal layers for facilitation of electrical connection. The most unique feature of the micro-bump structure is that on the surface of the kernel, a number of PI micro-studs are created for further enhancing the structural compliance. Because of the soft polymer-based kernel and micro-stud structures, the interconnect technology has a very compliant joining mechanism. The interconnect reliability and bondability are examined through experimental thermal humidity (TH) test in conjunction with a two-point daisy-chain resistance measurement.
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Several dominant failure mechanisms have been often observed in the NCF/A typed COG technology, including adhesive delamination, loss of electrical contact during temperature variation, and long-standing fatigue failure of the adhesive due to material degradation at high temperature and moisture absorption, etc. These failures can be largely resulted from the process- and temperature-induced thermal-mechanical behaviors. For example, the process-induced contact stress between the micro-bumps and opposing electrodes may greatly affect the electrical performance of the electronic assemblies [7], [8]. In addition, the process-induced warpage of the glass substrate in the COG technology is believed to be one of the main causes of the so-called “Mura” phenomenon in TFT-LCD panel [9], which would downgrade production yield. Besides, the process-induced peeling stress on the NCF/A might be the key factor inducing the initial delamination of the adhesive, resulting in the loss of structural integrity of I/O interconnection. Increased technical understanding and management of the process-induced thermal-mechanical characteristics during bonding process are indispensable to the realization of the technology. Thus, the alternative goal of the study is to quantitatively characterize the thermal-mechanical behaviors of the novel packaging technology during NCF bonding process and thermal testing through numerical modeling and experimental validation. Finally, to enhance the feasibility and reliability of the advanced interconnect technology, the effects of some key process and geometry parameters on the process-induced thermal-mechanical behaviors are explored using parametric finite-element (FE) analysis. II. ADVANCED COG ASSEMBLY USING AN NCF A. Configuration of the NCF Technology The LCD panel comprises two layers of glass substrates. The size of the top layer is 32.2 (length) 39.03 (width) 0.5 (thickness) (mm) and that of the bottom one is 32.2 44.85 0.5 (mm), on which a driver IC is mounted. The size of the chip is 17.2 1.43 0.4 (mm) and the I/O number is 1010. These I/Os constitute four different sizes/pitches of micro-bumps: 1) 764 I/Os with a bump size of 50 (length) 20 (width) 10 (height) ( m) and I/O stagger pitch of 21 m, 2) 236 I/Os with a bump size of 57 50 10 ( m) and I/O line pitch of 70 m, 3) 10 I/Os with a bump size of 50 39.5 10 ( m) and I/O line pitch of 70 m. The interconnects of the assembly include very compliant composite micro-bumps on the chip and opposing electrodes on the circuited substrate. The electrodes are made of Indium–tin–oxide(ITO) materials. A piece of thermoset type of NCF is used to create mechanical bonding between the chip and the substrate by way of its adhesion strength and shrinkage force during hardening and cooling under thermal-compression process. In principle, the bumps and the mating electrodes are not fully mechanically bonded. The advanced NCF technology employs a novel compliant composite micro-bump structure (Fig. 1). In specific, it is composed of a 10- m-thick polyimide kernel and a metal overcoat for facilitation of electrical connection. The structural compliance of the bumps is further enhanced by performing etching on the top surface of the polymer-based kernel using an exposing and developing
Fig. 1. Novel compliant composite interconnect structure.
process to create about 1.5- m-deep micro-studs. The metal overcoat consists of two metal layers: a 0.15- m-thick TiW and a 0.3- m-thick Au. These micro-studs are used mainly for simulating the functions of the fine electrically conductive particles in ACF/A. B. NCF Bonding Process The manufacturing process of the advanced NCF typed COG assembly is identical to that of the conventional one. First, a piece of NCF is placed on the glass substrate, and then the LCD driver IC is aligned and pushed down to the substrate under an adequate bonding force. The main purposes in applying the bonding force are principally to achieve solid contact between the micro-bumps and the electrodes prior to the curing of the NCF, to alleviate the risk of electrical disconnection due to bump height nonuniformity [7] and to crush the oxidation layer of the metals. As the bonding force is being applied on the chip, thermal loading is at the same time given for carrying out thermal curing of the NCF. The needed time for a fully cured NCF depends on the magnitude of the imposed thermal loading and the chemical properties of the adhesive. Once the NCF is fully thermoset, the imposed bonding force is released, and the assembly is cooled down to room temperature. III. PROCESS-DEPENDENT THERMAL-MECHANICAL ANALYSIS In principle, the thermal-mechanical behaviors of the COG assembly change with the NCF bonding sequences. In this paper, a process-dependent FE simulation methodology [9] is utilized for characterizing these behaviors. The methodology integrates a “death-birth” meshing scheme and 3-D FE modeling that involves both transient thermal and nonlinear thermal-mechanical analyses. In the process-dependent FE modeling, all the main NCF bonding steps are included except the solidification process of the NCF during heat cure stage. The NCF before fully cured would yield a low glass transition temperature, leading to a weak material strength and a large coefficient of thermal expansion (CTE); as a result, the curing process for the NCF can be neglected in the modeling. Note that the applied bonding force for the assembly is 10 kgW. The temperature loading given from the bonding head of the main bonder for the NCF curing is nonuniform, where a linear variation increasing from the center of the bonding head to its two sides is observed. The applied thermal load at the center of the chip is 150 C, which implies that the temperature at the edge of the chip is about 160 C, and the heat time during heat cure stage is 10 s. According to the NCF bonding process, the process-dependent simulation methodology would involve the following
CHENG et al.: THERMAL-MECHANICAL PROCESS SIMULATION OF AN ADVANCED NCF TECHNOLOGY
thermal and thermal-mechanical FE modelings: 1) transient thermal modeling of the heat cure stage of the NCF; 2) thermal-mechanical analysis of the loading process, including the imposed bonding force and the temperature loading based on the calculated thermal profile; 3) thermal-mechanical modeling of the activation of the NCF; 4) thermal-mechanical simulation of the release of the applied bonding force; and 5) thermal-mechanical analysis of the cooling process of the assembly. It should be noted that the interfaces between the handling station and the bottom glass substrate and between the micro-bumps and mating electrodes are defined with contact behaviors using ANSYS®. The transient thermal FE analysis takes into account heat transfer conduction, natural convection and radiation. In the 3-D FE modeling, all the main components of the COG assembly are considered, including the NCF fillet in the periphery of the chip. It is found that the averaged height of the NCF fillet after the thermal-compression process is about 100 m. In addition, the air between the bonding head and the glass substrate is included in the transient thermal modeling, and because of its trivial thickness (about 0.4 mm), heat transfer activity in the region is simply modeled by heat transfer conduction. Furthermore, the circuited glass substrate with a thin layer of copper runners can serve as a channel for heat dissipation. The copper runners are not only complex in trace layout but also bad in geometry aspect ratio. To deal with heat transfer analysis of the copper plane while still managing the scale and quality of FE mesh, a typical effective approach using the rule-of-mixture (ROM) technique is applied. Similar problems can be also observed in the composite micro-bumps comprising PI kernel, thin metal layers and micro-studs. They are modeled by an FEM-based effective approach [10] that integrates the 1-D Fourier’s law of heat conduction and 3-D FE modeling. The derivation first assumes that the equivalent micro-bumps would have the same heat transfer capacity along the transverse direction as the original model. Hence, they are considered as a seeming transversely isotropic material. Based on the 1-D Fourier’s law of heat conduction, the rate of heat transfer for a micro-bump is proportional to the cross-sectional area normal to the direction of heat flow, i.e., (1) which yields the effective transverse thermal conductivity ( ) (2) Likewise, the effective axial thermal conductivity can be also derived as (3) The coordinates , , and in (1)–(3) are defined in Fig. 1(b). and in (2) and (3) denote the total heat flux on the and -plane, respectively, , , and the depth, width, and the temperature difference height of the micro-bump, and between two parallel sides along either the transverse or axial direction. Once these two resultant heat fluxes under an imposed
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Fig. 2. 3-D thermal FE model of the COG assembly.
temperature difference are calculated using the heat conduction FE approximations, the effective thermal conductivities are derived from (2) and (3). To describe the heat transfer activity at the surface of the assembly, this study employs existing heat transfer (HT) coefficient correlation models for natural convection and radiation, in which they are the convective HT coefficient correlation model suggested by Ellison [11] and the typical radiative HT coef[12]. Fig. 2 shows one example of ficient correlation model 3-D thermal FE model, which is only a quadrant of the advanced COG assembly together with a part of the bonding system because of symmetry. The FE model for the thermal-mechanical analysis is similar to the transient thermal FE modeling aforementioned but with a minor modification. Particularly, the air layer applied in the thermal transient analysis is removed. The modeling difficulties can be also found in the great deal of composite microbumps consisting of thin metal layers and a number of etched micro-studs. To reduce the FE modeling effort and maintain solution accuracy at the same time, detailed modeling that includes the metal overcoat, micro-studs and polyimide kernel is performed with a fine mesh only at some critical micro-bumps on the chip, where the contact stresses are potentially critical (minimal or maximal). On the other hand, the rest of the microbumps are modeled using two stages of effective modeling. The first stage of effective modeling applies the FEM-based effective approach[10] to derive the equivalent material properties of a composite micro-bump. Subsequently, the effective material properties derived in the first stage are used in the second stage, where several micro-bumps are grouped together to form one equivalent micro-bump using the ROM technique. The underlying idea behind the FEM-based effective technique for deriving effective thermal-mechanical material properties is that the equivalent model would have the same thermalmechanical behaviors as the original one. The approach integrates 3-D elasticity theory and FE modeling. The relationship between the stress and strain for a transversely isotropic material can be expressed in the generalized Hooke’s law. In , total, there are five independent material constants ( , , , ) for the seeming transversely isotropic material. The generalized Hooke’s law yields these effective material constants if the corresponding stresses and strains can be obtained.
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TABLE I THERMAL-MECHANICAL MATERIAL PROPERTIES
TABLE II TEMPERATURE-DEPENDENT YOUNG’S MODULUS OF NCF
of the laser applied, which is 316 nm. The sensitivity of interferometers can be further improved through the integration of a phase-shifting technique. The relationship of the contact stress at the bump/electrode interface and the environmental temperature is much easier to be determined using theoretical methods than experimental approaches. However, the experimental measure of the connection resistance at various environmental temperatures allows to indirect verification of the effectiveness of the theoretical prediction of the contact stress using the proposed numerical model. Besides, the dependence of contact resistance on contact stress can be correlated by the approach. In this paper, the electrical contact resistance measurement is carried out by virtue of a four-point probe method. The contact resistance measurement is performed over a temperature range, i.e., 27 C 135 C. To minimize the measurement uncertainty, three measurements are taken and averaged for each gauge. Furthermore, the interconnect reliability of the advanced NCF technology is also examined through TH test of 85 C/85%RH. For facilitating the TH testing, the chip is daisy-chained allowing for the interconnection of the COG assembly to be experimented by a two-point electrical resistance measurement. V. RESULTS AND DISCUSSIONS A. Process-Induced Residual Thermal-Mechanical Behaviors
TABLE III CTE OF NCF
In the study, they are, respectively, calculated by an imposed loading on the -, -, and -plane, or along the -direction on the -plane of the micro-bump using FE approximations. All the materials of the COG assembly are assumed to be linearly elastic in the thermal-mechanical FE modeling, as shown in Table I. In addition, the CTE and Young’s modulus of the NCF are assumed temperature-dependent, shown in Tables II and III, respectively. The equivalent thermal-mechanical material properties of the micro-bumps are also shown in Table II. IV. EXPERIMENTS A T/G moiré interferometry technique is performed for exploring the out-of-plane deformations of the glass substrate [13]. The thermal deformations of the glass substrate are considered to be one of the major causes of the “Mura” phenomenon of the LCD panel. The moiré interferometer applies an He–Ne source laser with a wavelength of 632.8 nm. The technique can perform in situ measurement of the whole-field, out-of-plane deformations of structures subjected to the temperature loading. The primary restriction of the technique is that the measured surface of the object has to be lustrous. The resolution of the T/G moiré interferometry measurement can be up to a half of the wavelength
The curing-induced temperature of the package is first computed using the transient thermal FE analysis. The calculated temperature field at the duration of 10 s is shown in Fig. 3. As can be seen in the figure, there is a significant temperature gradient across the package. The temperature gradient would be the main cause of the residual warpage of the package after the NCF bonding process. Besides, the temperature gradient across the chip is less significant than that of the substrate because of better thermal conductance. The temperature field is further considered as an essential loading boundary condition of the subsequent thermal-mechanical FE modeling. 1) Warpage of the Glass Substrate: The process-induced warpage of the substrate along the line “a” of Fig. 4(a) (the bottom edge of the bottom glass substrate) are presented in Fig. 5(a), associated with the simulation steps. Note that the “0” on the horizontal axis of Fig. 5(a) is the central symmetry point of the lower edge of the bottom glass substrate. Clearly, owing to the compressive force during the thermal-compression bonding process, the warpages of the substrate at the first and second simulation steps are quite trivial. As the applied compressive force is discharged at the third simulation step, a considerable increase in the maximum warpage of the substrate is observed. This is due to the rebound of the package from the previous compressive restraint. The warpage is further drastically increased as the packaging is cooled down to the room temperature at the fourth simulation step. The final deformations are regarded as the residual warpage of the electronic assembly due to the bonding process. It is found from Fig. 5(a) that the maximum residual warpage at the line “a” takes place at the outermost point. In addition, the maximum warpage turns out to be also the maximum warpage of the entire substrate. Besides, the warpage of the substrate along the line “a” presents a convex shape. This can be explained by
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Fig. 3. Temperature profile at transient time 10 s.
Fig. 4. Locations of data extraction.
that there is a much higher CTE and process-induced temperature during the thermal-compression process in the driver IC than the substrate. Hence, the chip would undergo much more significant thermal contraction than that of the substrate, resulting in an upward bending in the substrate. The maximum residual warpage of the substrate at the line “a” after the NCF bonding process is about 9.48 m, and that at the line “b” is about 7.79 m. 2) Contact Stress on the Bump: There is a strong dependence between the contact stress and the contact electrical resistance [14]. In general, the larger contact stress implies the better contact electrical performance. Consequently, the epoxy-based interconnection technologies, including the current NCF technology, rely on a substantial residual contact stress after the bonding process for a robust and stable I/O connection at various temperature environments. The contact stresses at the micro-studs/electrode interface associated with these four simulation steps are shown in Fig. 5(b). Essentially, there are three rows of interconnects on the chip, as can be seen in Fig. 4(b), and the contact stresses are plotted versus the bumps in row “3”. The bump identification (ID) number in Fig. 5(b) starts from the central symmetry plane to the free edge along the longitudinal direction of the chip. In
addition, the contact stress on the contact surface is averaged in a volume-weighted manner [15]. In the first simulation step, both compressive force and temperature loading are applied to the top side of the driver IC that are placed and aligned to the circuited substrate. The resulting contact stresses as a result of the thermal loading is trivial because the NCF is thermally uncured yet. The resultant contact force on the bumps should be comparable to the applied load. As soon as the NCF is fully thermally cured at the first step, it thus becomes immediately activated in structure and also in the FE modeling. The inclusion of the NCF in the FE modeling at the step turns out to be quite insignificant on the resulting contact stresses because of the neglect of the chemical shrinkage of the NCF during heat cure stage. Besides, a very low strength of the NCF at temperature larger than its glass transition temperature is another key factor for the results. At the third simulation step, the contact stresses are reduced considerably in consequence of the discharge of the applied compressive bonding force. At the fourth simulation step, the NCF undergoes an extensive thermal contraction as the electronic assembly is cooled down to the room temperature, resulting in an extensive “bounce-back” increase in the contact stresses. The results also reveal that the bump in the row “2” closest to the free edge of the chip holds the maximum contact stress. On the other hand, the bump in the row “1” nearby the central symmetry plane of the chip would have the minimum one. This suggests that the electrical performance in the vicinity of the central zone of the chip would be poorer than that at the free edges. This poorer contact performance at the area may be the root cause of the central “light defect” failure of the LCD panel [Fig. 6(a)] occasionally observed in a high temperature test. 3) Tensile Stress on the NCF: Furthermore, the tensile stresses (normal stresses) on the adhesive at its interface with the chip are also presented in Fig. 5(c). The data is extracted along the line “c” of Fig. 4(b), which is nearby row “2” interconnects. It shows that there is no tensile stress at the first simulation step. Once the NCF is fully cured, it is subjected to small tensile stresses as a result of the thermal loading obtained from the transient thermal analysis. As the compressive
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Fig. 5. Process-induced thermal-mechanical behaviors at different simulation steps.
Fig. 6. Field failure modes.
Fig. 7. Residual warpage of the substrate along the line “b”.
bonding force is released, the bumps are immediately bounced back, creating a reaction force on the NCF. As the package
is cooled down to the room temperature, the tensile stresses become further increased due to the thermal contraction of the NCF. It is evident that the maximum residual tensile stress on the NCF takes place at the fourth simulation step, similar to the result trend of the warpage but different from that of the contact stress. Notice that an excessive residual tensile stress may be a great concern because of the potential of NCF delamination unless there is a good adhesive strength with the chip and substrate. It is also noted from the figure that the maximum tensile stress actually takes place in the neighboring area of the outermost bumps of row “1” and “2”. 4) Shear Stress on the NCF: The shear stresses on the NCF along the line “c” of Fig. 4(b) are presented in Fig. 5(d). A noticeable residual shear stress can only be detected after the bonding process. In addition, it is also found that the closer to the free edge of the chip, the larger the residual shear stress. The resultant stress of the tensile and shear on the NCF represents the peeling stress that tends to tear the NCF off from the die and substrate, resulting in the risk of the NCF delamination. In summary, the NCF at the corners or free edges of the chip is composed of both a significant residual shear stress and tensile stress, resulting in an excessive peeling stress, and thus becomes the most critical region for the risk of the NCF delamination. This has been somewhat confirmed by the field data, as shown in Fig. 6(b), where the corners of the chip tend to undergo substantial NCF delamination. 5) Experimental Validation: To validate the modeled residual warpage, the T/G moiré interferometry measurement is performed. The fringe pattern on the top surface of the entire LCD panel nearby the driver IC is captured and shown in Fig. 9(a), representing the residual warpage of the LCD panel
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Fig. 8. Thermal-mechanical behaviors of the COG assembly at temperature variation.
after the NCA bonding process. The modeled and measured residual warpages along the line “b” of Fig. 4(a), starting from the center of the substrate to its free edge, are depicted in Fig. 7. Both experimental and numerical results show that the farther the distance from the center of the glass substrate, the larger the deformations. Besides, they all deform in a convex shape (bend upward). The deformed shape is similar to that of Fig. 5(a), i.e., the deformations along the bottom edge of the bottom substrate. The measured maximum deformation at the line “a” is about 7.58 m, and that at the line “b” is about 10.43 m. In contrast to the modeled results, 7.79 m and 9.48 m, respectively, the differences are approximately 2.8% and 9.1%. The measured and modeled data agree well with one another. B. Thermal-Mechanical Behaviors During Temperature Variation The NCF technology is further cooled down to 40 C, followed by being heated up to 200 C soon after the NCF bonding process is completed. To verify the effectiveness of the numerical modeling, the modeled results in terms of the process-induced warpage of the glass substrate and electrical contact resistance are compared with the experimental data obtained from a T/G interferometer and a four-point probe method with an equivalent circuit, respectively. It is assumed an isothermal condition for the electronic assembly when subjected to the swing loading. The results, including the minimum and maximum contact stresses on the bumps, the shear and tensile stresses of the NCF at the point “P” in Fig. 4(b), and the maximum warpage of the substrate, are depicted versus temperature in Fig. 8. Fig. 8(a)
shows that the warpage of the substrate is reduced with an increase of temperature. The reason could be that the CTE of the silicon chip is larger than that of the glass substrate, and as the temperature is elevated, under the isothermal condition, the chip expand thermally more significantly than the substrate, thus leading to a downward bending and cutting back the residual warpage. A dramatic decrease of the warpage can be also observed at temperature beyond 190 C. This is because the material strength of the NCF becomes so negligible at the temperature and beyond that it can no longer serve as a mechanical connection structure of the chip and substrate. Fig. 8(b)–(d) shows the maximum and minimum contact stress, tensile stress, and shear stress, respectively, versus temperature. Noticeably, the result trend of the contact stress is consistent with that of the tensile stress. The stress evolution can be roughly categorized into three sections, and then be interpreted alone. It is evident that under the (100 C 120 C) of the NCF, both the stresses slightly decrease with temperature. This is probably due to that at elevated temperature, the NCF material becomes softer, and in addition, is closer to its stress free temperature. It should be noted that one of the key technical restrictions of the epoxy-based interconnect technology is the electrical deterioration in a high-temperature environment, and thus becomes impractical for high-temperature applications. Fortunately, for the technology, the decreasing rate of the contact stress is quite insignificant at the standard operation temperature range (0 C 100 C), thus having a little impact on the electrical performance. As the temperature approaches to around the of the NCF, a dramatic jump in the contact and tensile stresses can be detected. This is mainly because the CTE
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Fig. 9. Measured fringe patterns on the substrate under an isothermal temperature swing.
of the NCF increases dramatically at . The influence seems to be far more substantial than the elevation of temperature and the drop of the Young’s modulus of the NCF. The excessive contact stress value may be resulted from the assumption of elastic materials of the metal overcoat in the simulation. On the other hand, such phenomenon cannot be found in the shear stress. The dominated factors affecting the shear stress include the CTE difference between the chip and glass substrate, the shear modulus of the NCF, and the temperature, rather than the CTE of the NCF. Elementary mechanics of materials show that the shear modulus, elastic modulus and poison’s ratio are not independent for an isotropic material. Furthermore, over 180 C, the material strength of the NCF drops significantly, consequently resulting in trivial contact, tensile, and shear stresses. The modeled warpage at temperature elevation are compared with those obtained from the T/G moiré interferometry measurement. Fig. 9 shows the captured fringe patterns on the top surface of the LCD panel nearby the driver IC under an isothermal temperature swing from 27 C to 90 C. The difference in fringe order represents the net out-of-plane deformation due to the temperature swing. According to Fig. 9, the fringe order along the line “a” at temperature 27 C is 24 and that at temperature 90 C is 19, and that along the line “b” at temperature 27 C is 33 and that at temperature 90 C is 28. The fringe order is reduced by 5 at both locations, which is equivalent to 1.58 m. In comparison with the modeled result, 1.25 m, the difference is 0.33 m. It is only about one fringe order. The larger gap between the measured and modeled may be due to the less accurateness of the temperature-dependent material properties of the NCF and the limited accuracy resolution (i.e., 0.316 nm) or uncertainty of the T/G moiré interferometry measurement. C. Contact Electrical Resistance Measurement The measured average contact electrical resistances at the NCF joints when temperature is elevated from 27 C to 135 C are shown in Fig. 10. Similar to the contact stress, the contact electrical resistance evolution can be also classified into three sections. First of all, in the temperature range of 27 C 83 C, there is a slight increase in the contact resistance. This is caused by the minor growth of the contact stress, as can be seen in the figure. As the temperature approaches to around the of the NCF, a fair drop in the contact resistance is noticed. This could be attributed to the corresponding rise of the contact stress as a result of the substantial jump in the CTE of the NCF at . Once
Fig. 10. Contact resistance versus temperature.
Fig. 11. Connection resistance versus testing time under 85 thermal humidity condition.
C/85% RH
the temperature goes beyond the , a remarkable increase in the contact resistance can be detected. It agrees well with the contact stress, in which a dramatic drop can be observed at the temperature range. Fig. 11 shows the variation of the mean connection resistances of the COG assembly during the TH test of 85 C/85%RH. It is found that the interconnects surviveafter 500 h TH testing, and maintain their resistance, one half of the two-point daisy chain resistance, below 5 throughout the test. VI. PARAMETRIC ANALYSIS Parametric FE analysis is performed to explore the effect of design factors on the process-induced thermal-mechanical behaviors of the advanced NCF technology, including warpage, contact stress, tensile stress, and shear stress. The design factors considered only cover process and geometry parameters. The results of the parametric analysis associated with the essential design factors are presented in the following.
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Fig. 12. Effect of the chip thickness.
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Fig. 13. Effect of bonding force.
A. Effect of the Thickness of the Chip The effect of chip thickness on the process-induced thermal-mechanical behaviors of the NCF technology is shown in Fig. 12. Silicon IC chip thicknesses of 100, 200, 300, 400, and 500 ( m) are involved in the parametric analyses. Fig. 12(a) shows that the thicker the chip, the stiffer the chip, the larger the thermal contraction force acting on the substrate and eventually, the larger the maximum warpage of the glass substrate. It turns out that the degree of effect is significant. In addition, as can be seen in Fig. 12(b) and (c), the contact and tensile stresses are raised slightly by an increase of the thickness of the chip. Also due to the larger thermal contraction of the chip as a result of an increasing chip thickness, the corresponding shear stress is also enhanced considerably. B. Effect of the Process Parameters The effect of the bonding force and bonding temperature on the thermal-mechanical behaviors of the advanced NCF technology is investigated and presented in Figs. 13 and 14, respectively. Bonding forces varying from 6 to 10 (kg) and bonding temperature of 150, 170, and 190 ( C) are investigated. Results show that no noticeable influence of the bonding force on the warpage [Fig. 13(a)] and shear stress [Fig. 13(c)] can be detected. On the other hand, there is a strong dependence for the contact stress [Fig. 13(b)] and the tensile stress [Fig. 13(c)], in which an increase of the bonding force would considerably enhance the contact stress and also the tensile stress. This quite satisfies one’s expectation. Fig. 14(a) reveals that a larger bonding temperature implies a larger warpage in the glass substrate. This could be attributed to that as the bonding temperature is elevated, the corresponding temperature difference between the chip and the substrate is enlarged, thus leading to a more significant thermal contraction mismatch and causing a greater warpage. Furthermore, a higher bonding temperature suggests a larger contact stress, as shown in Fig. 14(b). A higher bonding temperature would result in a larger process-induced temperature on the NCF, and
Fig. 14. Effect of bonding temperature.
thus would create a larger thermal contraction during the temperature cooling and lead to a larger contraction force on the bumps. It turns out that both the contact and tensile stresses [see Fig. 14(c)] increase with the bonding temperature, but the effect is insignificant. On the other hand, the bonding temperature does have a larger impact on the shear stress [see Fig. 14(c)] of the NCF, as compared to the contact and tensile stresses. This is owing to that the dominant factor creating the shear stress on the NCF is the thermal mismatch between the chip and substrate, similar to the warpage. A larger bonding temperature would result in a larger temperature difference between the chip and substrate, thus leading to a more significant shear stress.
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VII. CONCLUSION This paper presents an advanced NCF-typed FC technology employing a novel compliant composite micro-bump structure. The interconnect reliability of the novel interconnect structural design is demonstrated through the TH test of 85 C/85%RH. In addition, the process-induced thermal-mechanical behaviors of the advanced NCF technology during the bonding process and temperature variation are extensively explored by virtue of the proposed process-dependent FE simulation and experimental validation. The factors most affecting the process-induced thermal-mechanical behaviors are also identified through parametric FE analysis. Results show that the modeled results are in very good agreement with the experimental data, including the process-induced warpage measurement using the T/G moiré interferometry technique and the contact electrical resistance measurement using the four-point probe technique. In addition, the novel interconnects pass 500 h of the TH test of 85 C/85%RH. Furthermore, from the process simulation, it is found that the maximum residual warpage of the bottom substrate is about 9.5 m and occurs soon after the cooling of the assembly and at the outermost points of its bottom edge. In addition, substantial residual contact and peeling stresses are generated after the bonding process. Moreover, both the modeled and field data indicate that the area neighboring the four corners of the chip would be considered the most critical region of the risk of the adhesive delamination, and in addition, the bump nearby the central symmetry plane of the chip comprises the minimum contact stress, thus resulting in an inferior electrical performance at the location. This may be the root cause of the “light defect” failure at the center of the LCD panel. Besides, the warpage of the glass substrate presents a decrease with an increase of temperature, but both the contact and tensile stresses show a slight decrease under the (100 C 120 C) of the NCF. As the temperature approaches of the NCF, a dramatic jump in the contact to around the and tensile stresses can be observed because of a considerable rise of the CTE of the NCF at . When the temperature exceeds 180 C, the NCF becomes very weak in material strength, leading to trivial contact and tensile stresses. For the shear stress, the higher temperature suggests the less shear stress. It is also found from the numerical analysis and experimental characterization that the contact resistance is indeed closely related to the evolution of contact stress. Finally, from the parametric analysis, the design parameters most affecting the thermal deformations of the glass substrate are the thickness of the chip and bonding temperature; those for the electrical performance are the bonding temperature and bonding force; those for the tensile stress of the NCF are identical to those of the contact stress; and those for the shear stress of the NCF are the thickness of the chip and the bonding temperature, similar to those of the warpage. Besides, with the novel interconnect structural design, the bump height nonuniformity stemming from manufacturing tolerances can be eased. REFERENCES [1] K. Hatada, H. Fujimoto, T. Kawakita, and T. Ochi, “A new LSI bonding technology: Micro bump bonding assembly technology,” Proc. IEEECHMT, pp. 45–49, 1988. [2] J. Liu, “An overview of advances of conductive adhesive joining technology in electronics applications,” Mater. Technol., vol. 10, pp. 247–252, 1995.
[3] R. Aschenbrenner, A. Ostmann, G. Motulla, and E. Zakel, “Flip chip attachment using ansiotropic conductive adhesives and electroless nickel bumps,” IEEE Trans. Compon., Packag., Manuf. Technol.-Part C, vol. 20, no. 2, pp. 95–100, Apr. 1997. [4] D. Lu, Q. K. Tong, and C. P. Wong, “Mechanism underlying the unstable contact resistance of conductive adhesives,” IEEE Trans. Electron. Packag. Manuf., vol. 22, no. 3, pp. 228–232, Jul. 1999. [5] K. N. Chiang, C. W. Chang, and J. D. Lin, “Process modeling and thermal/mechanical behavior of ACA/ACF type flip-chip packages,” ASME Trans. J. Electron. Packag., vol. 123, pp. 331–337, 2001. [6] M. J. Yim, J. S. Hwang, W. S. Kwon, K. W. Jang, and K. W. Paik, “Highly reliable non-conductive adhesives for flip chip CSP applications,” IEEE Trans. Electron. Packag. Manuf., vol. 26, no. 2, pp. 150–155, Apr. 2003. [7] H. C. Cheng, C. L. Ho, K. N. Chiang, and S. M. Chang, “Processdependent contact characteristics of NCA assemblies,” IEEE Trans. Compon. Packag. Technol., vol. 27, no. 2, pp. 398–410, Jun. 2004. [8] S. M. Chang, J. H. Jou, A. Hsieh, T. H. Chen, J. N. Jao, and H. S. Wu, “Internal stress and connection resistance correlation study of microbump bonding,” IEEE Trans. Compon. Packag. Technol., vol. 24, no. 3, pp. 493–499, Sep. 2001. [9] H. C. Cheng, C. L. Ho, W. C. Chen, and S. S. Yang, “A study of process-induced deformations of anisotropic conductive film (ACF) assembly,” IEEE Trans. Compon. Packag. Technol., vol. 29, no. 3, pp. 577–588, Sep. 2006. [10] H. C. Cheng, J. Lin, W. H. Chen, Y. Y. Hsu, and R. H. Uang, “Process-dependent thermal-mechanical analysis and design of a novel nanowire-based anisotropic conductive film assembly,” in Proc. IMPACT, Taipei, Taiwan, Oct. 18-20, 2006. [11] G. N. Ellison, Thermal Computations for Electronic Equipment. Malabar, FL: R. E. Krieger, 1989. [12] G. Ridsdale, B. Joiner, J. Bigler, and V. M. Torres, “Thermal performance limits of the QFP family,” IEEE Trans. Compon., Packag. Manuf. Technol.-Part A, vol. 17, no. 4, pp. 427–443, Dec. 1996. [13] D. Post, B. Han, and P. Ifju, High Sensitivity Moiré: Experimental Analysis for Mechanics and Materials. New York: Springer-Verlag, 1994. [14] R. S. Timsit, “Electrical contact resistance: Properties of stationary interfaces,” IEEE Trans. Compon. Packag. Technol., vol. 22, no. 1, pp. 85–98, Mar. 1999. [15] H. C. Cheng, K. N. Chiang, C. K. Chen, and J. C. Lin, “Solder joint reliability of thermal enhanced BGA using a finite-volume-weighted averaging technique,” J. Chinese Inst. Eng., vol. 24, no. 4, pp. 439–451, Jul. 2001. Hsien-Chie Cheng (M’07), photograph and biography not available at the time of publication.
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