BIST for Phase-Looked Loops in Digital Applications ... - CiteSeerX

BIST for Phase-Locked Loops in Digital Applications Stephen Sunter & Aubin Roy Logicvision, Inc. Ottawa, Canada Abstract Phase-locked loops (PLLs) are an essential building block of most digital and mixed-signal ICs. This paper describes a built-in self-test (BIST) circuit that tests the key analog parameters of PLLs, using only logic gates that can be synthesized from a hardware description language (HDL). The parameters tested include lock range, lock time, RMS jitter, and loop gain (from which the natural frequency is calculated). Experimental waveforms and results are shown for a 200 MHz PLL which uses a ‘phase-frequency detector. Test time is typically 10 msi much faster than for conventional testing. I

1. Introduction The PLL is possibly the most common mixed-signal building block used in digital IC design. It is typically used to accomplish one of four functions: synthesize an on-chip clock at a frequency higher than the board-level clock; generate a low jitter clock from a noisy clock; extract a data-synchronous clock from serially communicated data; generate an ‘on-chip clock with its phase advanced relative to a received clock. In some applications, designers may not think of the PLL as a “mixed-signal” function because it has a digital input and digital outputs. But because of its analog interior, PLL test results ye not deterministic and require testing like that for any other continuous variable, e.g., the tests must tolerate noise and measure values in various domains (frequency, time, voltage, etc.). However, the frequency analysis capabilities of a typical mixed-signal tester may not help. I

Testing PLLs on a synchronous digital tester or a mixedsignal tester can be complex to program, requiring high precision and on-pe-fly timing changes, and consuming 500 ms of test time even if special hardware is added specifically for PLLs [I]. As a result, PLLs are often tested by simply checking that they achieve phase lock.

This may not be sufficient to ensure adequate lock range and loop stability under all conditions.

A search of the US Patent database found only one patent addressing BIST for PLLs [2], and very few papers have been published on the topic, to our knowledge. Veillette & Roberts [3] reported a technique at ITC’97 for determining the jitter transfer function using a sigmadelta principle. Dufort & Roberts [4]reported at the same conference a jitter measurement technique which requires analog changes to the PLL. This paper will describe on-chip digital test circuitry that fully tests PLLs at-speed. First, the type of PLL addressed will be expla$ed. Then assumptions will be given that guided the BIST circuit design. Next, we describe the novel techniques used to test each of the key PLL parameters: loop gain, lock range, lock time, and jitter. The scheme requires no connections to analog nodes of the PLL, which minimizes the impact on PLL performance and PLL design time. 1.1 Types of PLLs There are primarily two types of phase detectors in common use on ICs. The most frequently used PLL type, shown in Figure 1, has a phase detector that is rising or falling edge-sensitive and is responsive to both phase and frequency, hence it is referred to as a phase-frequency detector (PFD). The PFD comprises sequential logic with Up and Down outputs controlling a 3-state charge-pump, which drives an integrator voltage up or down, or neither when the PLL is phase locked. When phase locked, the feedback signal is in phase with the input signal (i.e., 0” phase difference). The integrator output drives a voltagecontrolled oscillator (VCO). The other common type of phase detector is levelsensitive, most frequently implemented using an exclusive-or gate, and is best for very high frequencies. We have found that this type of PLL is rarely used in digital ASICs.

1 I

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ITC INTERNATIONAL TEST CONFERENCE 0-7803-5753-1 J99 $1 0.00 01999 IEEE

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3 vco KV

J

Typical Outputs:

Figure 1

2.

P i i P

fvc,JN

2fv,dN, etc.

fVC0

PLL with phase-frequency detector

Test Techniques

The key input parameter to control is phase, and the key output parameter to observe is frequency. Frequency is commonly measured using a gated binary counter and a reference frequency, as illustrated in Figure 2.

Unknown

frequency Ck

Binary counter

Divide by 2R

2R-' funknown IKnown

Figure 2

2.2 Loop Gain Measurement A key PLL design parameter is the open loop gain. The elements of this gain, referring to Figure 1, are:

K, , the gain of the phase detector

- for a phase-frequency detector which uses a charge-pump,

K,= iJ2n G(s), the frequency-dependent gain of the finite gain low pass filter (Type I loop) or integrator (Type I1 loop), where s is the Laplace variable

K,, the gain of the VCO, in radians/second/volt

2.1 Assumptions and BIST Design Constraints We set out to create a self-test technique that addresses both types of PLLs. However, their fundamental differences required significant test circuit modifications to achieve this. We will only describe BIST for the more popular type of PLLs, namely those that use edgesensitive PFDs and charge-pumps.

Digital output count =

Lastly, we assumed the BIST circuitry must be implementable in the typical digital ASIC! design flow, i.e., design capture at the register transfer level (RTL) in an HDL, followed by logic synthesis and automatic layout. This last assumption meant that we could not rely on precise delay matching or non-standard digital logic gates.

Circult for measuring frequency

To achieve minimal impact on PLL performance and design time, we assumed the PLL must be tested as a complete block, with no access to internal nodes. We assumed access is available to the PLL's one digital input and two or more digital outputs. The typical digital outputs are: the VCO output, the VCO output frequency divided by various integers, and possibly a phase lock indicator.

N , the digital divider, an integer typically 22. The open loop gain, for a second order, Type I1 PLL is:

The open loop gain is linearly dependent on every parameter affecting the PLL's transfer function at its 'operating frequency, so testing its value can achieve high analog fault coverage (however defined). But, as seen for operational amplifiers, it is very difficult to measure open loop gain without physically opening the loop. One test method, that does not physically open the loop, involves phase-modulating the input with various frequencies and measuring the amplitude of phase modulation at the output [ 5 ] . The novel approach that we chose is to open the loop by preventing feedback, i.e., making the output of the phase detector independent of the VCO frequency. It is relatively easy to generate an input to the PLL at the same frequency as the feedback signal by accessing the outputs of the divide-by-N counter, as shown in Figure 3. When the inputs to a PFD have zero phase difference, independent of the VCO output frequency, then its charge-pump output will be disabled - neither sinking nor sourcing current. The error integratodfilter output will then stay at a constant voltage equal to its output voltage when it was last driven by the charge-pump, assuming no current leakage. When in this 'opened-loop' state, a precise phase offset can be introduced and its effect on the VCO output frequency measured to determine the open loop gain.

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I

Currenl

Phase delay circuit

Figure 3

Delay next cycle

Circuit for measuring loop gain

fvcdN =

REF

2fRiT-w$

'Delay Next Cycle' 2fVCdN

Figure 4

To PLL input Circuit for delaying the phase of one cycle

The following equation relates the measured change in VCO frequency, d4c0, to the input phase shift, S,which is a unitless portion of a single cycle (negative if input lags feedback), and the charge-pump current, Icp :

Amvco

K v 8ICP

(radiansls)

fREFc

An equation for the open loop gain, which we calculated by dividing the feedback phase change by the input phase change for a single cycle off,, , is: fi:

There are two kinds of phase error that can be easily and accurately intfoduced with digital circuitry. We can cause a constant or a temporary phase shift. A 180" phase shift is easily derived from the PLL's divide-by-N outputs if N is an even integer, as shown later, and other phase shifts may be derived when N23. Applying a cdntinuous phase shift greater than 25" causes rapid change in the PLL's output frequency, too fast to be measured accurately with a simple frequency counter. Implementing smaller phase shifts requires larger values of N which limits the variety of PLLs for which it can be used - frequently N is less than eight. Applying a temporary phase shift (e.g., for only one cycle of the feedback clock, whose frequency equals f,,> causes rapid change while the phase is shifted, but when the phase shiftjreturns to zero, the output frequency stays constant at the,new value. This is the technique that we developed to 1 allow simple and accurate frequency measurement. An example circuit is shown Figure 4, and waveforms are ;shown in Figure 5. This circuit delays its 25% duty cycle output pulse by 180" during the cycle of f,,dN (which starts on a rising edge) immediately following detedtion of Delay-Next-Cycle-I. Initially, f,,dN =fREF, but quickly decreases in frequency.

1

Pw21.1

AmvcoAt I N

f ;EF NC

GOL

K v Icp

'@m -

A@w

~

(radidradian)

(4)

~ T ~ A F N C

Using this technique, the change in output frequency is proportional to the loop gain, the phase shift applied, and the number of cycles for which the phase is shifted. By subtracting the frequency change measured when no phase shift is introduced (over a similar time interval), any measurement errors due to an unknown phase offset, leakage current, or similar systematic errors, can be canceled (a first order approximation). This subtraction aspect is very important for tolerance to process variations. The loop gain in terms of the change in frequency caused by the input phase shift is calculated as follows. First we derive the change in the VCO frequency in hertz, for M cycles of input phase shift:

i

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MKV s I C P Afvco

2nfREFC

(5)

One way to drive the PLL's VCO to its lowest frequency, is to simply connect a logic 0 (or logic 1) to the PLL's input instead off,,. This is often sufficient, but several problems can arise.

Then we combine (4) and ( 5 ) to obtain:

Afvco COL

MN6

fREF

The value of Af",,,can be measured using the frequency counter, the value of S is controlled digitally using the circuit shown in Figure 4, and the value of M is controlled by a counter. The loop gain can be measured for a phase lead and then for a phase lag (e.g., S=+ O S ; -0.9, which can reveal any mismatch in the sink and source charge-pump currents. As well, the phase shift does not need to be 180" - it can be any value less than 360", as long as it is deterministic. Small values of M are best when the PLL has a high loop gain and there is a risk of driving the VCO input into saturation, and large values of M are best for lower loop gains to reduce variance in the output frequency count. Another key parameter in PLL design is the natural frequency of the loop. It is defined [5]as:

2niv c

voltage range delivered by the phase comparator and integrator. This simplifies BIST.

(7)

and is related to our measured loop gain as follows: f R E F JGOL

Knowing in advance the value off,, , test limits for Af,, can be loaded in during testing or stored on-chip, so that BIST will only pass PLLs which meet specifications for w, or G O L .

2.3 Capturehck Range Measurement The lock range and capture range are two important measures of the operating frequency range of a PLL. The capture range is the frequency range that the input signal may have, in which the PLL is able to acquire phase-lock. The lock range is the frequency range in which the PLL is able to retain phase-lock. For level-sensitive phase detectors, the lock range can be significantly larger than the capture range, as long as any frequency shifts are sufficiently slow. For edge-sensitive PFDs, which we are focusing on, the capture range and lock range are usually equal; we wish to measure the maximum and minimum frequencies of the IocWcapture range. We assumed that the primary limitation in lock range is the range of the VCO output frequency for the output

One problem is that many PLLs use a current-starved ring oscillator whose control voltage is connected directly to an n-channel transistor which controls the oscillator's current. If the input voltage decreases to less than the threshold voltage of the transistor, no current flows, and the oscillator stops oscillating. Obviously the lock range does not extend to DC, however, setting the PLL's input to logic 0 will drive the output frequency to its minimum very quickly, too quickly for the frequency counter to measure a frequency other than zero. A problem can also occur at the maximum frequency: if the output frequency of the VCO exceeds the capability of the divide-by-N counter, then the divided-down result may become a steady-state logic value. Thus, driving the PLL's output frequency too high, and too quickly, can result in the frequency counter having an output of zero. One solution to these problems is to continuously apply a frequency error to force the VCO output frequency to its maximum (or minimum) value at a controlled, relatively slow rate - it can then be measured several times during the frequency transition. We accomplish this by connecting the PLL's input to an output derived from the divide-by-N, with a frequency equal to double (or half) the internal feedback frequency. The output frequency is measured continuously, and when it stops changing significantly within a programmable time interval (i.e., it approaches its minimum or maximum value), the last recorded frequency count is saved.

2.4 Lock Time Measurement Lock time is the time for a PLL output frequency to become phase locked to an input signal within its capture range, starting from a different frequency. Lock time is typically quite sensitive to process variations, temperature, and power supply voltage. Often, lock time is not measured in production,testing; instead, a specified minimum amount of time is waited and if phase-lock is achieved, then the test continues on to the next test, else the device fails. Phase-lock is typically signaled by a circuit within the PLL, or elsewhere on the IC. A test for lock time must measure time until this circuit indicates that phase-lock has been achieved.

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An alternative approach is to measure time until frequency-lock is achieved, i.e., the PLL's output frequency equals the input frequency (or any other frequency).

a maximum value E, e.g., E=8096. Every E cycles of the PLL-input signal, the counter output is latched and then reset.

To measure lock time, the VCO output is first driven to its maximum frequency, during the last step of the lock range test. Next, the loop is 'closed' by reconnecting the normal input, and the number of reference clock cycles is counted until lock is achieved. 2.5 Jitter Measurement Jitter is a complex phenomenon whereby the phase of a signal with relatively constant frequency randomly deviates (jitters) relative to the average frequency. The root mean square (RMS) value of the jitter is often the best way to statistically summarize the random variation. The peak-to-peak value of the jitter is another common measurement. Jitter is typically measured relative to a suitably jittertfree signal from the tester or system. The BIST citcuit is constructed as follows. The PLL input signal is connected to the D input of a D-type flipflop (Figure 6), via a constant delay. The PLL output signal is divided down by a synchronous counter to the same frequency and phase as the PLL's input and connected to' the Clock input of the flip-flop, via a digitally-contrplled adjustable delay. Its maximum delay is approximately double the delay through the constant 4 delay. The variable delay, shown in simplified detail in Figure 7, comprises a chain of digital gates, such as non-inverting buffers, tapped by a multiplexer. The gates may be inverters, but p e n appropriate inversiodnon-inversion in the multiplexer is needed. The buffers used in the tapped delay chain must be fast enough to ensure that the delay step size achieves sufficient jitter measurement resolution, but slow enough to ensure that the number of inputs to the multiplexer is ' not excessive (preferably 132). Many other arrangements are possible, such as using only twoinput multiplexers, or tri-state buffers, and using binaryratioed delays., In any case, the buffers can be fast, serially-connected inverter pairs, slow 4-input NOR gates, or specially-designed logic gates. The delays of the individual gatys in the chain are assumed to be approximately equal by design, but not equal in reality. The output of b e D-type is compared to the expected value, and eachitime an error is detected, an error counter is incremented.~ If the PLL input is a 50% duty cycle clock (fREF), the expected value is always logic 1. When a pseudo-random bit stream is used, the source clock must be supplied to the BIST circuitry (instead off,,,), and an LFSR provides the expected value. The error counter has l

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i

Constant Delay

counter

I

Enable Ring Osc.

(circled characters refer to waveforms in Figure 12)

Figure 6

Circuit for measuring jitter

digital buffers (non-inverting logic gates)

tint _..".

I

Increment

Figure 7

last

output

Circuit for digitally-controlled variable delay

We shall now describe the procedure for measuring RMS jitter with the circuit of Figure 6 (with a rising-edge sensitive PLL). First, the adjustable delay is set at its minimum delay so that the error count is (presumably) continually zero for each group of E cycles. Next, a counter controlling the adjustable delay (i.e., connected to the multiplexer which taps the delay chain) is incremented after each E cycles of the PLL input signal. The delay control counter's values for which the error count is 15.9% and 84.1% of E are recorded (see Figure 8) - these correspond to the plus and minus one sigma points on the cumulative distribution function (CDF) for a Normal random variable (assuming the jitter is Normal).

To measure peak-to-peak jitter, the delay control counter values for which the error count is first non-zero and first equal to E are stored. Other ranges, e.g., 10% to 90%, or 20% to 80%, can also be measured.

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observation of analog effects via an oscilloscope without significantly affecting the PLL’s operation.

Bit Error Count vs Delay Tap Number

90% 80% 70% 60%

50% 40%

30% 20%

----------o

The phase-frequency detector of the 74HC4046 is a single pin driven by a tri-state buffer whose output is resistive (not a sink/source current). It was connected to an active RC filter, so the loop gain calculated similarly to (4) was: -

r

m

N

s

W

x

RMS value = (delay for Ta~16)- (delav for Ta08)

2 Figure8

(9)

s

Measuring the RMS Jitter on the Cumulative Distribution Function

Each of the two the adjustable delay tap values needs to be converted into absolute time measurements, because we do not know the exact delays of the delay chain. The adjustable delay, at each of the two settings (e.g., corresponding to 15.9% and 84.1%),is included in a ring oscillator, whose oscillation period is measured, and the difference between the two periods is output as a binarycoded digital value. Because it is the difference that is measured, all constant delays are irrelevant or are cancelled, including the flip flop’s set-up time. Off-chip measuring of RMS jitter via the CDF has been used for many years. Recent papers using the technique include [I] and [SI, in which ATE samples a digital output and implements the algorithm in software. Another on-chip technique has been reported [2] for measuring peak-to-peak jitter, in which a precise delay line has a latch and counter connected to every tap, and the counters containing the maximum and minimum counts indicate the time extent of the jitter.

3. Experimental Results All of the tests described above were verified on an ASIC manufactured in a 0.6 um CMOS technology (chosen because it has a PLL with sinklsource current mismatch). The PLL had a lock range extending above 200 MHz. We also verified the BIST techniques using an P G A (XC4010) to implement the logic gates, and an off-theshelf analog PLL (74HC4046) with a lock range of less than 200 kHz. Results from both verifications are presented in this paper. In both cases, the BIST circuitry was synthesized from Verilog or VHDL RTL code, and automatic layout was used, with no manual placements. For the P G A verification, the PLL’s input signal, f,, , was nominally 48 kHz. We chose a low frequency range to simplify verifying the BIST operation, and to enable

The input signal to the VCO during the loop gain test is shown in Figure 9, and was altered for two cycles of the input, as is visible in the waveforms. There is a small rise in voltage after each pulse deletion, caused by the resistor in the loop filter (see Figure 3). After the phase shifts, the voltage has been lowered to a new stable level, permitting an accurate measurement of the PLL’s output frequency. The loop gain was calculated using equation (6). 000 VDC

.. .. .. .. .. .. .. .. .. ................................................ . . . . . . . . .

Figure 9

VCO input during Loop Gain test, for FPGA

.. .. .. .. .. .. . . .... . . ... . . . ... . . .... . . .... . . ... . . . ... . . .... . . .. . . . . . . . .

. . . . . . . . ...............................................

. . . . . . . . ...............................................

Figure 10 VCO input during step change in frequency (36-58 kHz), for FPGA

We determined the loop gain using two other methods. First we measured the individual gains of the PLL’s circuit blocks, and calculated gain using (9). Next, for a step change in input frequency (Figure lo), we measured the time to the first peak in the VCO input voltage, T,,, and the per cent overshoot, d, for the closed loop response. Using the following equation for a second order loop, we calculated the open loop gain:

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The jitter was observed directly in both versions (FPGA in Figure 13, ASIC in Figure 14). The step size of the adjustable delay was approximately 2 ns for the FPGA, and 40 ps for the ASIC (20% of the ASIC’s typical inverter delay).

Loop gain results

BIST Equation (9) - direct measurement from (8) and (IO) - overshoot waveform ~

0.028 radhad 0.03 1 0.025

.a0 yD( 6.4115 02 An5

The waveforms for the ASIC PLL loop gain test are shown in .Figure 1 1 . We verified that doubling the sinkhource current bias reference had a proportional effect on the loop gain, and we measured a 50% difference in the sink and source currents, consistent with information supplied by the ASIC vendor. .03VDC

.. ..

... .

... .

... .

.. ...

.. ...

.. ...

.. .. .

. . . . ......................

EpI

1.2 2 v m 5

v

1- Rising Edge of Reference Clock to PLL 2- Rising Edge of Divider Output showing Jitter, Taw27 A- Rising Edge of Delayed Reference Clock (see labeled circuit nodes in Figure 6)

Figure 13 Waveforms during jitter test, for FPGA i’:...

2.8

v

I

Figure 11 VCO input during Loop Gain test, for ASIC

Figure 12 shows the VCO input during the lock range test for the FPG& version. It is first driven to its maximum level, and held stable while the frequency is measured, and then to its minimum level where the frequency is again measured. To measure these frequencies conventionall$, we slowly increased the input frequency until loss of phase lock was observed, and recorded the input frequency. We then repeated the experiment, but slowly decreased the frequency. 1

--lm

............... ....~..” .... .... Rising Edge of PLL Output, with display persistence, as measured by Tektronix 118018 oscilloscope, 3................A.

triggered by signal at PLL input pin of ASIC

Figure 14 Waveforms durlng jltter test, for ASIC

............................... . . . . . .

.

.

.

.

.

. 1.48

v

Flgure 12 VCO Input during Lock Range test, for FPGA (for lowest, mid-range, then highest frequency) Lock Range results Min. , Max.

Slow sweep BIST BIST

27666 67718 Hz 27374 68024 Hz (FPGA) 240 MHz(AS1C)

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Jitter results

Oscilloscope BIST

46.4 47.4

ns ns

Oscilloscope BIST

88.8 72

ps (RMS, ASIC @ 4.5 volts) ps (8K samples)

Oscilloscope BIST

26.6 39

ps (RMS, ASIC @ 5.5 volts) ps (8K samples)

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(peak-to-peak, FPGA)

4. Limitations Phase delay is introduced when testing a PLL which is distant from the BIST circuit. Five to ten nanoseconds was insignificant at the frequencies used for the P G A implementation, but for the 100 MHz ASIC, such a delay would not be tolerated by the BIST circuit. It is the subnanosecond delay access that gives BIST an advantage over external testers at high frequencies.

The accuracy of the loop gain test is limited primarily by phase error and leakage. Phase error introduced by the multiplexer in the input signal path may cause frequency drift in open loop mode (see the slight slope in Figure 11) that is too fast to measure, but the error can be reduced by identifying the critical paths to the logic synthesis and layout software. Excessive leakage, in the PLL’s integrator or charge-pump, also reduces the number of clock cycles that can be counted, however it usually indicates a faulty PLL. We did not experience any phase error problems in the ASIC implementation, mostly because typical loop filters reduce the frequency drift to levels which can be accounted for. The introduced phase error that limits accuracy becomes more significant at higher frequencies because its variation becomes too localized in the layout and hence cannot be canceled. The maximum measurable frequency is limited by circuit layout, introduced phase error, and the adjustable delay’s step size. The BIST circuitry was implemented in a fully synchronous design style (since it needs to be self-tested), so it faces the same speed limits as any synchronous digital design. While automated layout may be sufficient for several hundred megahertz, higher speeds usually require ‘assisted’ automatic layout. We expect that the upper limit will be sufficient for any PLL being tested on the same IC, especially since various, commonly known, design ‘tricks’ were used at the RTL level to limit the logic which must operate in a single clock cycle, and to exploit multi-cycle paths where possible. The maximum measurable jitter is limited by the gate delay available in the IC technology. For example, if jitter is 10 ns and gate delays are less than 20 ps, then over 500 gates would need to be connected in series to create the adjustable delay (without resorting to transistorlevel design or analog techniques). The jitter in a delay line is proportional to its delay [6],so a signal travelling through a long delay line might experience more jitter than that of the PLL being tested. In our experience, PLL jitter greater than the delay of 30 logic inverters is rare. Phase offset in the PLL is accommodated by using a longer delay line within the BIST circuitry, and more than a few nanoseconds of delay may result in excessive

measurement jitter, as just discussed. This usually limits the BIST circuitry to testing nearby PLLs, on-chip. The resolution of the jitter measurement is limited primarily by the delay of the logic inverters in the delay chain, and this delay decreases with each new technology. We used proprietary techniques to achieve delay increments equal to less than one fifth of a typical inverter’s delay in the chosen CMOS technology, while retaining suitability for logic synthesis. The resolution is also limited by jitter in the test circuitry itself, as previously discussed. For a reasonably short delay line (