Computer-Aided VLSI System Design (CVSD), Fall 2010 ... Verilog Language -.
Chapter 1-11. Verilog ... Verilog HDL: A Guide to Digital Design and Synthesis.
Computer-Aided VLSI System Design (CVSD), Fall 2010 http://cc.ee.ntu.edu.tw/~jhjiang/instruction/courses/fall10-cvsd/cvsd.html Schedule (9:10 ~12:10, Fridays) Week
Date
1
09/17
Lecture Overview
Lab
Assignment
Project
Linux; X-editor
Verilog (1): Cadence 2
09/24
Verilog Language -
Verilog Lab 1
Verilog HW 1
Verilog Lab 2
---
---
Verilog HW 2
Chapter 1-11 Verilog (2): Cadence 3
10/01
Verilog Language Chapter 11-17 Verilog (3): Behavior
4
10/08
Modeling and Debugging (Verdi) Verilog (4): Testbench
5
10/15
Writing and
Topics
---
Announced
Synthesizable Codes Synthesis (1): Design
Synthesis HW;
6
10/22
7
10/29
8
11/05
9
11/12
10
11/19
11
11/26
12
12/03
13
12/10
14
12/17
Verification
15
12/24
FPGA
16
12/31
Project Presentation
Presentation
17
01/07
Project Presentation
Presentation
18
01/14
Project Presentation
Compiler Synthesis (2): Design Compiler DFT and ATPG (Tetramax)
Synthesis Lab
Verilog HW 3
--DFT and ATPG
DFT/ATPG
Lab
HW
Midterm exam Static Timing Analysis (PrimeTime) Placement and Routing (SoC Encounter) Placement and Routing (SoC Encounter) DRC, LVS, LPE (Calibre)
Proposal Due STA Lab
Verilog HW 4
P&R Lab 1 P&R Lab 2
P&R HW
DRC/LVS Lab Verification Lab FPGA Lab
Presentation/ Report Due
*Lecture in Room 229, EE2. * Lab in PC classrooms 130, 132, EE2.
(right after lecture)
Lecture Notes: On course webpage (based on CIC training materials and others from instructors)
Reference textbooks: (not required) CIC training materials (available on CIC webpage). S. Palintkar. Verilog HDL: A Guide to Digital Design and Synthesis. Prentice Hall, 1996. M.D. Ciletti. Advanced Digital Design with the Verilog HDL. Prentice Hall, 2003. M.J.S. Smith. Application-Specific Integrated Circuits. Addison Wesley, 1997.
Teaching Assistants A 類助教
TBA TBA
張耀文教授 吳安宇教授 江介宏教授 簡韶逸教授 李建模教授 闕志達教授 黃鐘揚教授 陳良基教授
徐孟楷
[email protected]
施信瑋
[email protected]
張恩瑞
[email protected]
蘇冠羽
[email protected]
張家偉
[email protected]
林辰軒
[email protected]
黃泳霖
[email protected]
許博豪
[email protected]
陳柏瑞
[email protected]
白炳川
[email protected]
莊富凱
[email protected]
廖家群
[email protected]
吳政穎
[email protected]
葉昱甫
[email protected]
陳東杰
[email protected]
蔡一民
[email protected]
Grading Lab
10%
Homework
40%
Midterm
25%
Project
25%
Website password =
(5% presentation; 20% report)
