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Design and Measurement of a CT ADC With Switched-Capacitor Switched-Resistor Feedback Martin Anderson, Member, IEEE, and Lars Sundström, Member, IEEE
Abstract—The performance of traditional continuous-time (CT) delta-sigma (16) analog-to-digital converters (ADCs) is limited by their large sensitivity to feedback pulse-width variations caused by clock jitter in their feedback digital-to-analog converters (DACs). To mitigate that effect, we propose a modified switched-capacitor (SC) feedback DAC technique, with a variable switched series resistor (SR). The architecture has the additional benefit of reducing the typically high SC DAC output peak currents, resulting in reduced slew-rate requirements for the loop-filter integrators. A theoretical investigation is carried out which provides new insight into the synthesis of switched-capacitor with switched series resistor (SCSR) DACs with a specified reduction of the pulse-width jitter sensitivity and minimal power consumption and complexity. To demonstrate the concept and to verify the reduced pulse-width jitter sensitivity a 5 mW, 312 MHz, second order, low-pass, 1-bit, CT 16 modulator with SCSR feedback was implemented in a 1.2 V, 90 nm, RF-CMOS process. An SNR of 66.4 dB and an SNDR of 62.4 dB were measured in a 1.92 MHz bandwidth. The sensitivity to wideband clock phase noise was reduced by 30 dB compared to a traditional switched-current (SI) return-to-zero (RZ) DAC.
Fig. 1. Normalized impulse response of different feedback DACs. (a) SI nonreturn-to-zero (NRZ) [1], (b) SI dual-return-to-zero [25], (c) sine shaped feedback [26]–[29], (d) SI delayed return-to-zero (RZ) [1], (e) switched capacitor with series resistor (SCR) [10]–[13], (f) switched capacitor with variable series resistor (SCVR) [14].
Index Terms—A/D conversion, clock jitter, delta-sigma modulation.
I. INTRODUCTION ELTA-SIGMA modulators with CT loop-filters have gained popularity in battery powered applications due to speed/power advantages over their discrete-time (DT) counterparts, enabling a higher clock rate or lower power consumption [1], [2]. Also, CT modulators can provide inherent anti-alias filtering. Recent CMOS implementations show feasible input bandwidths up to a few 10 MHz [3]–[5], making CT modulators an attractive choice in for example wireless receivers. Unfortunately, CT modulators are more sensitive to non-ideal effects such as process spread, excess loop delay, and the phase noise of the clock [6]–[8]. The clock phase-noise causes different types of timing errors. The most serious is the feedback pulse-width (PW) variation [9] caused by the wideband clock phase noise. The large sensitivity to feedback PW variations is due to the high amplitude of the traditionally used SI (RZ) feedback signals (shown in Fig. 1(a), (b), (d)) at the set and reset time instants, making
D
Manuscript received February 04, 2008; revised September 17, 2008. Current version published January 27, 2009. This work was supported by the Vinnova Competence Center for Circuit Design (CCCD) and Ericsson AB. M. Anderson is with the Department for Electrical and Information Technology (EIT), Lund University, SE-22100 Lund, Sweden (e-mail:
[email protected]). L. Sundström is with Ericsson AB, Business Unit Multimedia, Unit Mobile Platforms, SE-221 83, Lund, Sweden (e-mail:
[email protected]). Digital Object Identifier 10.1109/JSSC.2008.2010978
the amount of charge fed back to the loop-filter strongly dependent on the PW. As a consequence, there has been a considerable interest in the use of decaying feedback pulse shapes like, for example, sine-shaped feedback (see Fig. 1(c)) and exponentially decaying feedback (see Fig. 1(e)). Among these, the exponentially decaying pulse shape is the one that has been most frequently implemented simply by using a switched capacitor with a series resistor (SCR) [10]–[13]. In SCR feedback, the sensitivity to PW errors is controlled by the discharge time constant, . However, as also concluded in [11], a reduction of the PW sensitivity using SCR feedback, can only be achieved by reducing the time constant, which will increase the DAC output peak currents linearly, and thereby increase the slew-rate requirements for the integrating amplifiers in the loop-filter. Recently, we introduced a technique to control the output current of a SC DAC, that results in a constant current pulse shape followed by an exponential decay of the feedback current amplitude [14], as shown in Fig. 1(f). This new pulse shape, which can be realized theoretically using a SC with variable series resistance (SCVR), and approximated in practice using a SC with switched series resistors, has two main benefits. Firstly, the PW sensitivity can be controlled by the discharge time constant. Secondly, the constant current phase will give lower DAC output peak currents, which relax the slew-rate requirements of the integrating amplifiers. The two main contributions of this paper are a theoretical analysis of SCSR feedback and a measurement verification of the reduced PW jitter sensitivity. In Section II, the clock phasenoise effects in a CT modulator are reviewed. In Sections III and
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modulators the clock phase In Nyquist rate ADCs and DT noise induced noise power is dominated by the noise from sampling errors in the upfront sampling circuit [8]. Because the sampling process ideally is a multiplication in time, the spectra of the analog input signal and the clock signal convolve. Therefore, the spectrum of the output signal of the upfront sampler will be the spectrum of the analog input signal with the (typically non-white [15]–[17]) spectral shape of the clock signal expressed on it. It can be shown that, given a single-sideband phase noise spectrum with power spectral density (PSD) for the sampling clock signal with frequency and a sinusoidal and amplitude , the corresponding input with frequency , will be (in dBc/Hz) noise PSD at the output of the sampler, [18], [19]
The clock phase-noise causes each clock edge to deviate from its nominal position, resulting in both PW and pulse-position (PP) variations, depending on the frequency of the phase noise. Phase noise close to the clock frequency (sometimes denoted close-in noise) will be strongly correlated from one clock edge to another, thereby moving the position of a number of consecutive clock edges in the same direction with respect to the ideal sampling instants. It was shown in [9] that the amplitude errors in the loop-filter caused by PP errors are at least 1st order noise shaped. It has also been found that the close-in noise causes a similar IBN as for non-uniform sampling [1], [5], [11]. Thus, close-in phase noise creates in-band noise the same way as in an ADC with upfront sampler, mainly by modulating the desired in-band signals. Wideband phase-noise will change the phase of the clock . from one clock edge to another resulting in PW variations, The change in PW changes the amount of charge integrated by the input integrator and thereby results in a voltage error at its output, which is not noise shaped when referred to the modulator input. Due to the wideband nature of the PW errors, they create IBN by modulating the high power density regions of the DAC input outside the signal bandwidth, mainly quantization noise and out-of-band ADC input signals. For a traditional 1-bit SI (RZ) DAC, the PW error can be approximately modeled as an average amplitude error over one , where is the quantization step size. clock period, Assuming that the PW errors are white with zero mean and , we can get the in-band noise power by standard deviation simply taking the mean-square of the average amplitude errors, multiplied by the transfer function squared and divided by the OSR:
(1)
(3)
centered at the signal frequency instead of the clock frequency. Narrowband (close-in) clock phase noise will fall directly in-band, whereas the wideband clock phase noise will be aliased within the Nyquist band of the upfront sampler increasing the in-band noise (IBN) uniformly. Assuming a white clock phase noise with zero mean, the total output power of a , sampler in the frequency band of interest, with a single-tone input can be found to be [8]
Equation (3) is in agreement with the earlier presented results in [7] and [11].
Fig. 2. Illustration of an annotated.
Lth order CT 16 modulator with its clock signals
IV, we define and analyze the SCVR concept and its SCSR realization, respectively. Design equations and methodology, providing insight into the most important tradeoffs involved in the design of SCSR feedback, are derived. Finally, Sections V, VI, and VII present the CT modulator implementation and the experimental results. II. CLOCK PHASE-NOISE IN CT
MODULATORS
(2) is the standard deviation of the corresponding white where sampling time jitter. In a CT modulator, as illustrated in Fig. 2, the time discretization takes place at the quantizer input, which is the point of maximum error suppression, rather than at the modulator input. Therefore, in an th order CT modulator, these sampling errors will be th order noise shaped. Instead, the clock phase noise induced noise power is dominated by the noise from the DAC clocks. The total noise contribution from the DACs is dominated , because the PSD of the noise from the by the noise from is noise shaped. Therefore, the theoretical other DACs analysis presented in this paper mainly considers the noise induced in the outermost, th, feedback branch.
III. THE SCVR FEEDBACK METHOD In this section, we first introduce the generalized SCVR feedback DAC concept. Then we use its basic parameters to derive the two most important properties of its implementations: (i) the reduced sensitivity to PW errors and (ii) the tradeoff between reduced loop-filter feedback coefficients and DAC pulse discharge time constant. The operation of an SCVR feedback DAC, illustrated in Fig. 3, can be divided into three operation phases, the reset, the constant current, and the exponential discharge phase. , a 1) In the reset phase, which takes place from 0 to switched capacitor is pre-charged to an initial DC voltage, . This results in a well-defined charge, , being stored on the capacitor. 2) During the constant current phase, with duration , the charge is discharged through a variable that changes its value over time in such a resistance way that the current through the resistance is held constant and equal to its initial value. (4)
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Fig. 4. Amplitude efficiency, , versus =T for different values of = [0 0:125 0:25 0:375 0:5 0:625 0:75] with = 0:25 and = 1. = 0 corresponds to a SCR DAC and = 0:75 corresponds to a SI (delayed RZ) DAC with 75% duty-cycle. The SCVR solutions along a dashed line, result in the same pulse-width jitter sensitivity, . Fig. 3. SCVR feedback DAC concept definitions and notations. (a) SCVR circuit concept, (b) capacitor voltage jv (t)j, (c) variable resistance R (t), (d) SCVR feedback current ji (t)j.
3) Finally, in the exponential discharge phase from , the resistance is held constant
to
(5) Therefore, the current decreases exponentially to its final value
To facilitate comparisons of different SCVR feedback pulses, we introduce a Figure-of-Merit (FoM), , called the amplitude efficiency. We define the amplitude efficiency as , where is taken to be the feedback coeffiand . Thus, a low cient for a SI (RZ) DAC with means that the DAC output current will be high. Since SI (NRZ) feedback has the lowest possible feedback coefficient, it represents the upper limit for the amplitude efficiency, and . By inserting the result from (7) the ampliequals tude efficiency for SCVR feedback equals (8)
(6) where
is the discharge time constant for
. Since the nominal SCVR feedback pulse shape is defined by and , both the DAC output peak current and the sensitivity to PW variations can be controlled through a careful choice of those parameters. Maximizing the constant current phase, , will give the lowest DAC output currents, but will on the other hand require a very low exponential discharge time , in order to guarantee a low sensitivity to PW constant, and ), jitter. This tradeoff between the timing parameters ( the DAC output peak current, the PW jitter sensitivity and the , will be further explored smallest discharge time constant below in Section III-A and B. A. SCVR Feedback Coefficient The loop-filter feedback coefficients should be made as small as possible to minimize the DAC output peak current. In the outermost feedback branch, the feedback coefficient, , depends only on the integral of (the amount of charge delivered by) a certain feedback pulse during one clock cycle [1], [11]. Therefore, is given by the DT feedback coefficient, , divided by the integral of a normalized SCVR pulse (7)
The SCVR amplitude efficiency (8) as a function of for different values of , is plotted in Fig. 4 (the solid lines). B. SCVR PW Jitter Sensitivity Due to the exponential reduction of the feedback pulse amplitude from to , the average PW error per clock period , will be exponentially reduced. for a SI (RZ) feedback, By assuming that the decaying pulse is approximately constant around the reset time instant, and following the same procedure as in Section II, the in-band noise power caused by white PW errors, can be found to equal (9) for an arbitrary SCVR feedback pulse. To further facilitate comparisons of different SCVR feedback pulses, the PW jitter suppression efficiency, , is defined. We choose the PW jitter induced in-band noise power of a tradi, as the reference. Theretional SI (RZ) DAC output pulse, is a measure of how much a white PW jitter is supfore, pressed in an SCVR DAC as compared to a traditional SI (RZ) . By combining (3), (7), and (9) we get DAC with (10)
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TABLE I SUMMARY OF SCVR PULSE CHARACTERISTICS, ILLUSTRATING THE TRADEOFF BETWEEN AMPLITUDE EFFICIENCY, , DISCHARGE TIME CONSTANT, , PW JITTER SUPPRESSION, , AND CONSTANT CURRENT PHASE DURATION,
Fig. 5. SCSR PW jitter suppression efficiency, , versus =T for different : : : : : : with : and values of .
corresponds to a SCR DAC and : corresponds to a SI (delayed RZ) DAC with 75% duty-cycle.
=0
= [0 0 125 0 25 0 375 0 5 0 625 0 75] = 0 75
= 0 25
=1
arbitrary SCSR current pulse can be expressed as the sum of exponentially decaying pulse segments staggered in time: (11)
Fig. 6. Normalized, equi-ripple, SCSR pulse with notations.
In Fig. 5, the PW jitter suppression efficiency (10) is plotted as for different values of . The dashed lines a function of in Fig. 4, pointing out the SCVR solutions with various levels of PW jitter suppression, were obtained from Fig. 5. The feedback coefficients and time constants along the constant PW suppression lines are also shown in Table I. As can be clearly seen from the comparisons, increasing the constant current phase , can reduce the feedback coefficients significantly, but the discharge time constant must be decreased in order to keep constant. In 20 dB is required, the feedback coefficient cases where becomes very large for small whereas the time constant becomes very small for large and low . As shown in Table I, 20 to 40 dB, the peak current can be reduced by for 2–4 times compared to traditional SCR feedback. IV. SCSR FEEDBACK REALIZATION In this section, the nominal properties and the synthesis of the SCSR feedback realization of the SCVR feedback concept are presented. The SCSR feedback DAC constitutes a switched capacitor with a series resistance that can change value at discrete time instants. The series resistance is realized either by bypassing resistors connected in series, or by switching in resistors connected in parallel, or by using other combinations of switched parallel and series resistors. pulse segments, is An SCSR pulse example, with shown in Fig. 6 to illustrate the notations. Mathematically, an
where segment,
is the initial current of the th pulse is the timing of switching instant is the first switching instant, is is the discharge time the last switching instant, and , and constant between switching instant is the overall resistance of the variable resistance network in the th pulse segment. The duration of pulse segment will be . denoted For all SCSR realizations of SCVR, the feedback coefficient and the PW sensitivity will be affected by the amplitude ripple during the constant current phase, caused by the discretely varying switched resistance. Using the same arguments as in Section III-A it can be shown that, for any SCSR realization, the feedback coefficient in the th feedback DAC is increased, compared to the SCVR equivalent, to (12) As a consequence, the PW induced noise power will also increase to (13) Fortunately, in theory, an SCSR realization can be designed to approximate its SCVR equivalent arbitrarily accurate, by increasing the number of pulse segments . A. Pulse Shape Alternatives To minimize the DAC complexity and power consumption while meeting the specification on jitter sensitivity, peak current
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and discharge time constant, a careful choice of each duration and time constant as well as a minimum number of pulse is necessary. segments There is an infinite number of ways to arrange the duration and time constant of each pulse segment. In order to simplify the implementation of the switch control phases, it would be preferable to make all pulse segments equally large in time (equi-duration pulse segments). (14) Unfortunately this leads to a ripple in the constant current phase is that increases for every pulse segment. The reason is that required to decrease in a linear fashion (see Fig. 3(c)) to keep the current constant. This in turn means that the discharge time constant, , is reduced and consequently the variation in current over one segment will increase along the pulse. As a consequence, a large number of pulse segments are needed to accurately approximate the SCVR equivalent. This increases the power needed to generate the switch control phases. Instead, focus has been on equi-ripple SCSR realizations since they are the theoretically optimal way to approximate the SCVR pulses, using no more pulse segments than necessary. They do however require the switching instants to be non-uniformly distributed in time. In order to determine the minimum number of pulse segments for an equi-ripple SCSR realization, a design equation relating the duration of and ripple in the constant current phase to the number of pulse segments is needed. For a normalized, equiripple SCSR feedback pulse, previously shown in Fig. 6, it holds that the constant amplitude of the ripple, , is (15) From the equi-ripple characteristics, it follows that (16) It can also be shown that the duration of one pulse segment is related to the duration of the following pulse segment as (17) and that (18) Using (15)–(18) it is possible to find the equation relating the ripple to the number of pulse segments , the duration of the constant current phase , and the smallest discharge time : constant (19) Once a target SCVR pulse ( , and ) has been selected, (19) can be used to numerically study the relation between and the increase of the feedback coefficient due to the inevitable ripple during the constant current phase. The results
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from the design examples presented in [23] suggest that as few as 3–5 pulse segments can give acceptable performance. B. Numerical DT-CT Transformation After choosing a DT modulator and a feedback pulse shape with the required performance, a DT-to-CT transformation must be performed in order to obtain the equivalent CT modulator. Using the impulse-invariant transformation [6], [11], [20], the equivalence is achieved if the inputs of the quantizers of the DT and respectively, are the same and CT modulators, . at all sampling instants (20) By making the open loop impulse responses of the DT and CT modulators identical at the sampling instants (20) is fulfilled. As a consequence, the closed-loop outputs of the DT and CT modulators will also be identical. This leads to the condition [1], [21], [22] (21) or in the time domain (22) where and are the impulse responses of the DT and CT is the impulse response deloop-filters respectively and scribing the pulse shape of the DAC output in the CT modulator , and are the Laplace and z-transform case. , and respectively. of For a specific pulse shape, (21) may be solved analytically. , we have However, to support arbitrary pulse shapes, used a numerical method to perform the convolution in (22) instead. The numerical impulse-invariant transformation, briefly outlined below, can be performed using any analog circuit simulator. 1) First, the DT loop-filter and all CT modulator feedback pulse shapes must be known. Also, an impulse response simulation of the DT reference system and the CT system needs to be arranged. 2) Start with feedback coefficient , where is initially set to . In the SCSR case, the order of the loop-filter, can be found using (12). Set for both the DT and CT to their nominal values and all the undetermined coefficients to zero. to 3) Reduce by one. Set the nominal DT coefficient its nominal value. Run repetitive impulse response simulaof the CT system is swept, in order to tions, where determine the coefficient that makes the input of the quantizers identical at the sampling instants. 4) Repeat Step 3 until all coefficients have been determined. V. CT SCSR MODULATOR IMPLEMENTATION To demonstrate the SCSR concept, and to verify the reduced sensitivity to wideband phase-noise, a fully differential, second modulator, was implemented in order low-pass, 1-bit, CT a 90 nm CMOS process with 1.2 V power supply. A simplified ADC block schematic is shown in Fig. 7.
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Fig. 7. Simplified block schematic of the implemented, fully differential, second order, 1-bit, CT
A. System Architecture In this design the W-CDMA baseband bandwidth of 1.92 MHz was targeted. Clocked at 312 MHz, the OSR 81. The DT loop-filter coefficients realizing the desired NTF were selected using the Delta-Sigma Matlab toolbox by Schreier 1 and [24], with peak NTF gain of 4, resulting in 2. This modulator configuration ideally gives an in-band quantization noise level of about 82 dBFS. B. Loop-Filter Implementation The loop-filter consists of a feedback RC integrator followed by a Gm-C integrator. The RC integrator is required to provide a high linearity summing node for the input signal and the feedback pulse whereas the Gm-C integrator exhibit very good high speed properties (low loop delay) that are essential to the operation. Also, the Gm-C integrator does not load the RC-integrator resistively and thereby does not lower the RC integrator open-loop gain. After selecting the feedback pulse shapes, and performing the DT-to-CT transformation (see Section IV-B), the dynamic range scaling was performed through CT simulations on an ideal CT loop-filter model, using Spectre. The nominal full scale ampli560 mV for the differential input signal, . tude was After DR scaling the resulting peak voltages for the differential signals at the integrator outputs, using a 6 dBFS single 320 mV and tone input, have the nominal values of 280 mV for the RC and Gm-C integrator, respectively. The RC integrator was implemented using a fully differential 40 dB and loopfolded-cascode amplifier with DC gain 850 MHz resulting in the GBW-togain bandwidth 2.7. The transconductance of the clock ratio Gm-C integrator was implemented using a source degenerated differential-pair. C. Feedback DAC Implementations The feedback DAC output current to the summing node of the RC integrator is generated by an SCSR DAC . An is used to provide the feedback signal to the SI DAC Gm-C integrator.
16 ADC with SCSR/SI feedback DACs.
The SCSR feedback pulse parameters were chosen to suppress the PW jitter noise to the same level as the noise shaped SI DAC noise from the inner feedback path. Margin was taken to account for variations in the discharge time constant, and the static timing variations of the switch control phases. With and were sea four-phase clock available and , the SCSR lected. With , and the feedback coefficient becomes, from (12), theoretical maximum suppression of the noise from the SCSR 58 dB. The nomDAC can be calculated, using (13), to inal SCSR pulse-shape and timing of the switch control signals are shown in Fig. 8. One side of the implemented, fully differential, SCSR DAC is should be chosen shown in Fig. 9. The switched capacitor and , and thereby minas small as possible to maximize imize the influence of the on-resistances of the switches, the RC integrator input impedance and finite GBW. Furthermore, minalso reduces the effect of the kT/C noise because imizing but the the PSD of the kT/C noise is proportional to . When transfer function back to the input is proportional to reducing has to be increased to keep the feedback coefficient constant. Therefore, the fundamental lower limit to the . Here, switched capacitor size is set by the upper limit for 132 fF was selected for the differential dethe nominal sign, which is larger than that lower limit, to become less sensitive to parasitic capacitive effects. Since the maximum average must equal the maximum average feedback input current during one clock period, the nominal can be current derived: (23) 15.4 k . The nominal resistances , of each with pulse segment , is derived from the nominal , and are given in Table II. A parallel switched resistor implementation, as shown in Fig. 9, was selected since it proved to be a good way to rein presence of the switch and layout alize the aggressive parasitics. The values of the parallel switched resistors of Fig. 9 was reduced to account for the finite amplifier input . impedance and on-resistance of the switches
ANDERSON AND SUNDSTRÖM: DESIGN AND MEASUREMENT OF A CT
Fig. 8. The nominal pulse-shape and switch control signals plemented SCSR and SI DAC.
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for the im-
The power consumption of the switch control phase generator and delay line dominates the power consumption of the SCSR DAC implementation. Fortunately, variations of the pulse segdo not substantially change the amount of ment durations charge delivered per clock cycle by the SCSR DAC. Since the amount of integrated charge has been shown to be the most important aspect of the feedback pulse accuracy [9], the requirements on the switch control phase random variations become controlling the switch low. Therefore, the control signals were created in a simple inverter based control signals delay line, as shown in Fig. 9. To generate the non-uniform delays the capacitive load is reduced and the driving strength increased towards the end of the delay line. was implemented using a SI (RZ) DAC with and . Using the numerical DT-CT transformation method described in Section IV-B, the feedback coefficient was found . Assuming white PW errors with zero mean, the to be is input referred PW induced noise power for
Fig. 9. Single-ended illustration of the fully differential SCSR DAC with M 8 switched resistors, the inverter-based delay line and switch control phase generator.
=
TABLE II SCSR PULSE CHARACTERISTICS t =T ; FOR THE IMPLEMENTATION, WITH C
=T
AND R
= 132 FF
(24) Thus, with suppressed by
, the PW errors from 34 dB.
will ideally be
VI. SIMULATION RESULTS The circuit noise mainly composed of quantization noise, kT/C noise and thermal noise loop-filter thermal noise, from the voltage reference circuit provides an IBN level of 76.8 dBFS assuming an ideal clock. The sensitivity to white PW errors was simulated using a behavioral model of the system with an ideal loop-filter, and the IBN was measured over a 1.92 MHz bandwidth. Thus, the IBN will be composed of both PW jitter induced noise and quantization noise. Fig. 10 shows the result from simulations 0.5%, on a traditional SI DAC and the imwith plemented SCSR DAC in , respectively. From the PSD close to DC, the expected PW jitter suppression for the SCSR 58 dB, can be seen. Fig. 11 shows the result of DAC, three different PW jitter sweeps, where the PW jitter of each of the DACs was simulated separately and together. Firstly, it
can be seen that the IBN caused by PW jitter from is in good agreement with calculations (24), and that it is domi5%. Secondly, nating the PW jitter induced noise for above that level, the SCSR DAC noise increases rapidly since (9) is based on the assumption, that the exponentially decaying pulses are approximately constant at the reset moment, which is only valid for small PW variations. Because the pulse amplitude has not reached low levels in the case of large negative PW errors the decaying waveform does not suppress the negative peak PW errors of the Gaussian amplitude distribution, , very effectively. Thirdly, the maximum simulated PW jitter suppression for the implemented SCSR/SI
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Fig. 10. Output spectra from PW jitter simulations of the implemented SCSR DAC (DAC ) and a SI DAC (DAC ) used to verify the reduced sensitivity to PW jitter, = 58 dB. White PW jitter, =T = 0.5%, was used. The input signal was a 30 dBFS single tone at 581 kHz. 32768-point FFT with Hann window.
0 0
Fig. 11. Simulated IBN due to PW jitter and quantization noise, compared to calculated PW jitter induced IBN for a 50% duty-cycle SI (RZ) DAC in DAC and the implemented 75% duty-cycle SI (RZ) DAC in DAC .
A. The Measurement Setup DAC combination, is 31 dB, and can be found approx4%. imately at To investigate the effect of the RC integrator finite GBW on the PW jitter suppression [11] of the SCSR DAC, we included a behavioral high-frequency model of the RC integrator in the system simulation. The input impedance, closed-loop transfer and loop-gain bandwidth of the model closely follow that of the implemented RC integrator at high frequencies. With 850 MHz, the GBW is times higher than the clock frequency in this implementation. From the simulation result 0.5%, the PW shown in Fig. 10, it was found that for jitter induced noise level from the SCSR DAC is increased by 6 dB when using the GBW limited RC integrator model as compared to the simulation using ideal loop-filter. Since the noise is much larger, the GBW of the implemented RC from integrator does not increase the overall sensitivity to white PW jitter. , we By sweeping the feedback pulse segment durations, made two interesting observations. First, the value of the settled impulse response of the DAC and RC integrator does not vary much with , which means that the amount of charge delivered by the SCSR DAC, in one clock cycle, is weakly dependent on the exact delay time. Therefore, the feedback coefficient is not dependent on , and the sensitivity to small random delay variations (delay line jitter) is small. Random delay variations were also simulated in [14], where it was concluded that even quite large random delay jitter variations can be allowed without decreasing the performance. Second, large static delay variations can cause two different effects. It was found that an increased will increase the sensitivity to clock PW variations by increasing . On the other the feedback current at the reset moment will increase the peak currents from the hand, reduced is reduced faster than SCSR DAC, because the resistance nominally. VII. MEASUREMENT RESULTS This section presents measurements of the reduced phasenoise sensitivity and the performance of the implemented CT modulator.
The prototype modulator was implemented in a 90 nm RF-CMOS process. The layout shown in Fig. 12 occupies 0.3 mm and consists of two modulators and a bandgap reference. The operation of the circuit was verified using a supply voltage of 1.2 V for the modulator core and 1.8 V for the bandgap and reference voltage buffers. The measurement setup is illustrated in Fig. 13. The input signal was generated using an RF signal generator and a ninth order LP filter to remove the harmonic distortion from the generator. The four-phase, 312 MHz, clock signal was generated using another RF generator and a splitter with 90 degree phase shift. The clock sine waves were amplified to square-wave signals on chip. In any application where complete chip integration is important, a four-phase clock can instead be created using a phase locked ring oscillator or by using a clock rate that is twice the sampling rate of the converter. The digital 1-bit output was collected using a logic analyzer and further analyzed in Matlab. The power spectra were calculated using FFTs with Hann windowing and averaging. To increase observability we used a single tone instead of a white phase-noise when measuring the sensitivity to wideband phase-noise. In that way, we were able to study the effect of each phase-noise frequency component separately. The clock phase-noise was created by simply using a third RF signal gen, that was erator to create another tone, added to the clock sinusoid, , using a comcreates both phase biner as shown in Fig. 13. The tone and amplitude modulation of the clock signal, but the amplitude modulation is removed by the amplitude limiting on chip. The , phase modulation of the clock causes pulse width errors, , but mainly varying with the offset frequency, the error sequence also contains some weaker harmonic tones at multiples of . In the DACs, the PW errors are multiplied (in time domain) by the input signals of the DACs, causing energy from the DAC input signal spectrum around the offset frequency to shift into the signal band of interest. These effects , were simulated by first calculating the pulse width errors, caused by this setup. Thereafter, the clock PW error sequence was multiplied by the actual output sequence of the ADC from
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Fig. 14. Measured and simulated total IBN for the implemented modulator and and the implesimulated IBN due to PW jitter from a 50% duty-cycle SI mented 75% duty-cycle SI when sweeping f . The relative amplitude A =A was 20 dBc (corresponding to =T 1.5%).
0
Fig. 12. CT modulator layout. Top: ADC-I. Bottom: ADC-Q. Middle: Bandgap reference, bias generators and clock input buffers.
Fig. 13. Measurement setup.
the measurements. The resulting DAC output error sequence was then referred to the input by using the nominal loop-filter coefficients. Finally an FFT of the error sequence was calculated and the IBN induced by the systematic phase modulation was found by integrating over the 1.92 MHz signal bandwidth. The in-band circuit noise power from the measurement was added to get the total IBN from simulation. B. Measurements The results of sweeping the frequency, , and relative am, of are shown in Figs. 14 and 15, respecplitude, tively. The sweeps were performed in simulations and measurements on the implemented modulator with SCSR feedback and compared to simulations on a modulator with SI ( and ) feedback. In all measurements and simulations, a dBFS input signal at 0.5 MHz was used. The offset frequency, , of was swept from 0 to . The
DAC
DAC
large IBN from the simulation clearly shows the high sensitivity of the SI DAC to the phase-noise at large offset frequencies from the clock frequency that modulates the quantization noise into the signal band. A significantly reduced sensitivity to this noise can be observed for the implemented SCSR DAC over a wide frequency range. At small offset frequencies the noise is dominated by quantization noise rather than by the PW modulation. The increased IBN for phase-noise tones at offset is due to modulation with strong idle frequencies close to . In the tones in the modulator output spectrum close to phase-noise amplitude sweep, the PW error for a phase-noise was swept corresponding to PW tone at offset frequency variations from 0.015% up to about 9%. At large phase-noise tone amplitudes, the integrated in-band noise for the measured SCSR DAC is 30 dB lower than for the simulated SI DAC. Furthermore it can be seen from the simulais not tion that the sensitivity of the SCSR DAC to large as dramatic when using sinusoidal PW errors, which is because . the peak PW variations are smaller, The results from an input amplitude sweep, using a 0.5 MHz single tone input signal, are shown in Fig. 16. The IBN was calculated over a 1.92 MHz bandwidth. The peak SNR is 66.4 dB at 4.7 dBFS input amplitude. The peak SNDR is 62.4 dB at 7 dBFS input amplitude. The DR is 70.0 dB. A summary of the measured performance and the simulated power consumption for the different modulator sub blocks is given in Table III. The total measured power consumption amounts to 12.5 mW and each modulator is estimated to consume 5 mW. VIII. CONCLUSIONS AND FUTURE WORK modulator A 5 mW, 312 MHz, second order, 1-bit, CT with SCSR feedback, having 70 dB dynamic range and 10 bit ENOB over a 1.92 MHz signal bandwidth, has been implemented in a 90 nm RF-CMOS process. The measurement results clearly demonstrate that the SCSR technique can be used to reduce the CT modulator sensitivity to wideband phase-noise by as much as 30 dB without a large increase in the DAC output peak currents compared to traditional SI (RZ) DACs. This leads to reduced phase-noise requirements on the clock source, better robustness against power
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TABLE III SUMMARY OF THE SIMULATED POWER CONSUMPTION AND THE MEASURED PERFORMANCE
Fig. 15. Measured and simulated total IBN for the implemented modulator and and the implesimulated IBN due to PW jitter from a 50% duty-cycle SI and SCSR when varying the relative mented 75% duty-cycle SI amplitude A =A at the fixed offset frequency f : f MHz.
DAC DAC =03
DAC
Fig. 16. Measured SNR and SNDR versus input signal level for a 0.5 MHz single tone signal. Peak SNR is 66.4 dB at 4.7 dBFS. Peak SNDR is 62.4 dB for 7 dBFS input level. The DR is 70.0 dB.
0
0
supply induced clock jitter from clock buffers as well as to reduced slew rate requirements for the integrating amplifiers, especially useful in applications demanding a high SNR. The results of the theoretical investigation can be used to make a proper tradeoff between PW jitter sensitivity, discharge time constant and DAC output peak current during design. The theoretical investigation furthermore suggests to use only half the number of pulse segments found in the implementated circuit without significantly increasing the DAC peak current. This in turn can lead to better power efficiency and lower complexity of future SCSR DAC circuits. Because of the sensitivity to static delay line variations, we recommend the use of a delay line with process insensitive delay for future implementations. For example, it would be possible to lock the delay time to the duty cycle of the reference clock using a phase detector and negative feedback.
ACKNOWLEDGMENT The authors wish to thank Dr. R. Strandberg and T. Pettersson for skillful design and layout assistance, N. Klemmer for reviewing the design, and Dr. P. Andreani and Dr. S. Andersson for their perspicacious suggestions on how to improve this paper.
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Martin Anderson (S’07–M’08) received the M.Sc. degree in electrical engineering from Linköping University, Norrköping, Sweden, and the Ph.D. degree from Lund University, Lund, Sweden, in 2002 and 2008, respectively. In 2002, he joined the Mixed-Signal IC Design Group at the Department for Electrical and Information Technology, Lund University, where he has been working with time-interleaved SA-ADCs, reconfigurable pipelined ADCs and CT 16 modulators in CMOS. During 2006, he was with Ericsson AB, Lund, working with ADC technology for cellular systems. Since 2008, he holds a research position at Lund University. His research interests include systematic analog/mixed-signal IC design and behavioral modeling.
Lars Sundström (S’91–M’95) received the M.Sc. degree in electrical engineering and the Ph.D. degree from Lund University, Lund, Sweden, in 1988 and 1995, respectively. From 1995 to 2000, he was an Associate Professor with the Competence Centre for Circuit Design, Department for Electrical and Information Technology, Lund University. Since 2000, he holds a research position at Ericsson AB, Lund, Sweden. He continues his research activities with Lund University as an Adjunct Professor. His research interests include analog/ mixed-signal design and transceiver architectures for future cellular standards.
