Design and Simulation A Low-Power SA ADC

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IJARAS

International Journal of Academic Research in Applied Science 1(3): 40-51, 2012 ijaras.isair.org

Design and Simulation A Low-Power SA ADC Asadollah Salimi Department of Electrical Engineering, Boroujen Branch, Islamic Azad University, Boroujen, Iran [email protected]

Abstract In this paper, an 8 bit 100 kS/s successive approximation analog to digital converter is designed and simulated in TSMC 0.18 µm CMOS technology. System level simulations are done using MATLAB and design parameters are extracted. Static and dynamic performances of this analog to digital converter are analyzed total power consumption of analog to digital converter is 137 µW in 100 kS/s sampling frequency. Keywords SA ADC, low power, CMOS, TSMC 0.18 µm

Int. J. Acad. Res. Appl. Sci., 1(3): 40-51, 2012

1. Introduction Energy-limited applications such as wireless sensor networks, biometrics, and portable amusement demand the energy-efficient analog-to-digital converter (ADC) to extend the duration of the system powered by the battery [1]. Power saving can be achieved in many aspects. At architecture level, different ADC architectures consume different power for the same specification. The successive approximation (SA) ADC exhibits the lowest power reported in literature due to its minimal active analog circuit requirement. If its input signal connects to all the capacitors of the digital-to-analog converter (DAC) through ten analog switches, it doesn’t suitable for low voltage application. When the input signal level is around half the supply voltage, these switches may have very poor on-resistances at a low supply voltage and thus limits the input bandwidth of the ADC [2]. The switch connecting to the common-mode reference will suffer from the same issue as well since is usually designated to be a half of the supply voltage. Our selected structure also has the special DAC that reduce the entire capacitance of DAC due to its C-2C section. The essential point of our structure is comparator. Due to input connection is must be rail2rail. For SAR (Successive Approximation Register) we use the LFSR that introduce in [3].

2. System Level Design and MATLAB simulation The first step of design is simulating the procedure of SA ADC in MATLAB simulator. In this environment in a loop with ideal comparator and other elements we can convert any input voltage in full-scale range can be converted into digital code in 8 clock pulses. In this simulator we can simulate the parasitic capacitance or offset of comparator and their effect on entire system. We can plot the Vin versus Vout for an ideal 8-bit ADC. So we can evaluate the SNQR for an ADC without any noise except quantization noise. It’s measured and compared with the formula: SQNRformula = 6.02 × N + 1.78 = 49.94 dB

(1)

SQNRevaluation = 48.6383 dB

(2)

The difference between these two values (although is negligible) is related to the Vin/Vout relation in two graph. Figure 1 shows the difference between two diagrams (for better showing we set N=3). Figure 1 is used for SQNRformula and figure 2 is the output of MATLAB simulator for calculating SQNRevaluation.

Figure 1: SQNRformula

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Figure 2: The output of MATLAB simulator for calculating SQNRevaluation

2.1. Architecture The main blocks consisting of the proposed SAR ADC are DAC, comparator, S/H, SAR and clock control block as shown in figure 3. The ADC is based on charge redistribution architecture in C-2C capacitor array. The comparator has a rail-to-rail input range and the clock control block generate a short pulse with delay comparing with digital clock for good operation of comparator. Therefore, the ADC achieves low power consumption.

2.2. Digital-to-Analog Converter The DAC is designed by using a C-2C capacitor array as shown in figure 4. S0 to SN-1 are controlled by clock control block. S0 to Sk are LSB part and Sk+1 to SN-1 are MSB part.

Figure 3: Block diagram of the proposed SAR ADC

Figure 4: schematic of the proposed DAC with C-2C capacitor

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Int. J. Acad. Res. Appl. Sci., 1(3): 40-51, 2012 The LSB part is constructed by C-2C capacitor array. The total capacitance of the LSB part is expressed as (3k-1)C . The reduction of the total capacitance leads to low power consumption and fast settling time. Moreover, the capacitor array is composed of unit capacitor C and 2C. It generates more accurate reference voltage than the attenuate capacitor array. Rise time of DAC in worst case is measured and it’s 16.11 ns. However, the C-2C capacitor array has large output impedance. It makes an error equivalent to the input impedance of capacitor. To reduce the error, the binary weighted capacitor array is used in the MSB part. Finally, by changing the ratio of C-2C and binary array, power consumption, accurate, total capacitor and etc., were compared in different states.

2.3. Track-and-Hold Circuit The block diagram of sampler is shown in figure 5 [4]. In this structure; a capacitor was added to end of Abo switch that can take very accurate sample. This structure doesn't need any kind of amplifiers dissipating large amount of power. This switch despite of variable input has a constant Gait-Source voltage, equal VDD. For do that, it uses bootstrapping method. Main circuit of this switch or sampler is shown in figure 5.

Figure 5: Bootstrap circuit and switching device plus output capacitor as a track and hold

2.4. Comparator with a Rail-to-Rail Input Range The comparator is one of the main analog blocks, which decided the resolution in SAR ADC. To achieve high resolution, large gain structure is necessary. However, the low supply voltage limits the dynamic range of analog circuits and results in a reduction of SNR. To get the maximized SNR at low supply voltage, rail-to-rail signal swing is required. The block diagram of the proposed rail-to-rail comparator is shown in figure 3. Better comparator than main paper comparator was used for better power consumption that it doesn't multiplexer and clock control block for enable switches. The voltage boosting comparator is used to achieve a rail-to-rail common mode for comparator. This comparator is chosen from [5]. The proposed comparator schematic is shown in figure 6. The voltage booster can be easily implemented and will not consume much power as its output is a pulse wave not a regulated DC voltage and also the comparator’s dynamic current is relatively small. Nevertheless this clock booster can be shared for all comparators driven by similar clock pulses in the same stage or even in the entire converter. In this case special care should be taken in the design of the booster to be

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Figure 6: The proposed dynamic comparator

able to deliver the total required current in the corresponding phase as well as the total capacitive load. For power issue, the proposed comparator is operated only for the moments when it compares the values. Comparator is necessary at every clock cycle, but there is no need to compare the voltage for the whole convention time. In fact it compare just at the small time of cycle when digital part needs that (figure 7).

Figure 7: The proposed comparator clock

2.5. Successive Approximation Register Figure 8 shows the successive approximation register that designed to has minimum transition for minimizing the power consumption [2]. It consists of 18 D-Flip-flop. For proper output the D-FFs of above row must have synchronous set/reset pin although, the below row must have asynchronous set/reset. The Rst signal, that is in figure 8 is produced from a 4-bit counter that counts from 0 to 9 (10 clock pulse). In first clock all capacitors of DAC is reset and T/H samples the input. In 8 clocks, 8 bits is determined and in final clock the output code is registered in a specific register. This SAR is designed so that minimum transitions are

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Int. J. Acad. Res. Appl. Sci., 1(3): 40-51, 2012 happened and minimum power is dissipated. Each bit (D7 to D0) is high for one pulse and then depend on comparator output, its reset to zero or stay one. Figure 9 shows the internal circuit of D-FF. Internal circuit of inverter and transmission gate can be seen in [6]. All transistors in SAR have minimum scale for minimizing power consumption and have less area. For designing D-FF with asynch/synch set/reset pin we used a truth table and with general gate we design all of it.

Figure 8: The successive approximation register

Figure 9: The internal circuit of D-FF

3. Simulation Results 3.1. Static Performance The measured differential nonlinearity (DNL) and integral nonlinearity (INL) of the SA ADC are shown in figure 11. The INL is in the range of -0.14/-0.28 LSB whereas the DNL is within -0.15/+0.15 LSB. With attention to VFS=1.8 and 8-bit resolution LSB is 7.03125mV, so for measurement INL and DNL we simulated the program to sweep input voltage from 0V to 1.8V with 1mV resolution. Figure 10 shows the INL and DNL without shift and gain correction.

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INL without correction -0.1

INL(LSB)

-0.15 -0.2 -0.25 -0.3

0

50

100

150 200 Code DNL without correction

0

50

100

250

300

250

300

0.2

DNL(LSB)

0.1 0 -0.1 -0.2

150 Code

200

Figure 10: The INL and DNL without shift and gain correction

3.2. Dynamic Performance Figure 11 plots the measured signal-to-noise-and-distortion ratio (SNDR) and spurious free dynamic range (SFDR) of the SA ADC with respect to the stimulus amplitude. The results prove that the ADC indeed has a rail-to-rail input range. Besides, the ADC achieves a peak SNDR and a peak SFDR of 48.6699 and 57.7271 dB, respectively. It corresponds to an effective number of bits (ENOB) of 7.79 bits. Figure12 shows the measured output spectrum of the ADC where the ADC achieves its peak SNDR 64 samples was used to derive the spectrum. The main spurious tone is the second harmonic of the stimulus, showing that the ADC is somewhat asymmetric at the test setup. Nevertheless, the fourth harmonic is only 58.9 dBFS and thus has no significant impact on the SNDR performance of the ADC. The harmonic distortions of the ADC as functions of the input frequency are shown in Fig. 13. Figures 11-12 illustrates the measurement results of the ADC’s SNDR and SFDR versus different stimulus frequencies and amplitudes. The SNDR does not degrade even with the stimulus frequency close to 100 kHz. In other words, this ADC achieves An ERBW no less than its Nyquist bandwidth and the ERBW is independent of the stimulus amplitude. 60 SFDR SNDR ENOB

SFDR(dB) SNDR(dBc)

50

40

30

20

10

0

0

0.1

0.2

0.3

0.4 0.5 0.6 Vin Amplitude (mV)

0.7

0.8

0.9

Figure 11: SNDR, SFDR and ENOB versus different stimulus amplitudes

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SFDR

Power Spectial Dencity(dBFS/bin)

10

10

10

10

10

10

10

0

-1

-2

-3

-4

-5

-6 4

10 Frequency (Hz)

Figure 12: Power Spectral Density of a sample input

60 SFDR SNDR ENOB

SFDR(dB)\SNDR(dBc)\ENOB

50

40

30

20

10

0 100

150

200 250 300 Sampling Frequency(KS/s)

350

400

Figure 13: SNDR, SFDR and ENOB versus different stimulus frequencies

Figure 9 depicts the measured SNDR versus the system clock frequency with the 1 kHz sinusoidal stimulus to test the maximum operation speed of the ADC. The ADC is shown to be able to operate at a clock frequency as high as 2 MHz without notable SNDR degradation. Further increasing the clock rate will degrade the performance of the ADC. Since the bandwidths of the T/H and the DAC are all much higher than 2 MHz, it is the comparator that limits the bandwidth of the ADC design. All SFDR and THD (and estimation of SNDR) are done with 64-point FFT.

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Figure 14: Equivalent circuit for DAC when MSB is one

3.3. Input Capacitance of Comparator With attention to Fig. 14 we can measure input capacitance of comparator (Cp). We remove the SAR form the ADC and manually feed the DAC with 1000000 input. So the output of DAC that is connected to input of comparator, in this case the output is 0.89998Volt although it’s must be 0.9Volt. So the parasitic capacitance can be evaluated. =

=

×

(3)

−

=

. .

−

≈

(4)

3.4. Power Consumption The total power dissipation of the SA ADC is 13.74 µW at 1.8 V and a 100 kS/s output rate. The averaged powers consumption can be reduced to 11µW with changing the structure of DAC. The power consumption gets smaller with .25 ratios if the voltage source gets behalf. Table 1 shows this fact. Table 1: POWER DISSIPATION IN DIFFERENT VOLTAGE SUPPLY

Supply

Digital

Analog

Total

Voltage(V)

Power(µW)

Power(µW)

Power(µW)

1.8

6.51

7.23

13.74

0.9

1.46

1.83

3.29

Table 2 shows the effect of main frequency clock on power dissipation. It shows that with twice the frequency clock, the power dissipation will be twice. 48


Also in the table 3, power consumption and total capacitor are compared in the different ratio of C-2C to binary of DAC.

Table 2: Effect of main frequency clock on power dissipation

Sampling

Digital

Analog

Rate(KS/s) Power(µW) Power(µW)

Total Power(µW)

20

0.60602

0.63855

1.2445

50

3.1425

3.3491

6.49

100

6.51

200

13.483

400

7.23 16.215

27.14

32.253

13.7 29.7 59.4

Table 3: power consumption and total capacitor in the different ratio of C-2C to binary

Ratio (C-2C)/(Binary)

Analog Power Total Capacitor (µW)

(µW)

3/5

10.94

41Cu

4/4

7.66

28Cu

5/3

6.14

23Cu

6/2

5.5

22Cu

8/0

5.3

23Cu

3.5. Monte-Carlo Simulation We simulated the DAC and Comparator with Monte-Carlo simulation dependently. In DAC we model the biggest cap with a random variable with 8pF mean value and 1.5% variance. In one hundred run 54 percent of runs have DNL in allowed region and 100 percent of runs have INL in allowed region (Fig. 15).In our Monte-Carlo simulation we give the DAC digital codes 01111111 and 10000000 to measure the INL and DNL in worst case. For yield of DNL is 54% and INL is 100%. For comparator we run Monte-Carlo simulation for width one of the input transistors, with mean value 0.25µm and 3.6e-3 relative variance. In this simulation in 73-run of 100-run the comparator do its task correctly. So the yield is 73%. 49


Monte-Carlo Analysis: Scatter Plot 2

1.5

DNL(LSB)

1

0.5

0

-0.5

-1

-1.5 0

10

20

30

40 50 60 Sample Number

70

80

90

100

Monte-Carlo Analysis: Histrogram Plot 12

10

8

6

4

2

0 -2.5

-2

-1.5

-1

-0.5

0 0.5 DNL(LSB)

1

1.5

2

2.5

Fig. 18: Scatter and Histogram of DNL for Monte-Carlo simulation

4. Conclusion An energy-effective 8-bit SA ADC is presented. At 1.8 V and an output rate of 100 kS/s, the SA ADC achieves an ERBW up to the triple bandwidth, a peak SNDR of 49.37 dB, a peak SFDR of 57.72 dB, and a rail-to-rail input range. From the energy perspective, the proposed ADC achieves an FOM of 286 fJ/conversion-step. Table 4 shows the summary of specification of our ADC. Table 4: summary of SA ADC

Process

0.18 µm CMOS TSMC

Supply Voltage(V)

1.8

Full-Scale Voltage(V)

1.8

50


Bit Resolution

8

LSB(mV)

7.03125

Clock Frequency(MHz)

1

Output Rate(KHz)

100

SFDR(dB)@fin=(31/64)Fs

57.72

ENOB@fin=(31/64)Fs

7.79

SNDR(dB)@fin=(31/64)Fs

48.66

THD(dB)@ fin=(31/64)Fs

-48.66

ERBW (KHz)

333

Total Power Dissipation(µW) 13.7 FOM(fJ/conversion-step)

286

DAC Settling Time(ns)

16.11

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[2]

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[3]

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[4]

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[5]

R. Lotfi, M. Taherzadeh-Sani, M. Y. Azizi, and O. Shoaei, "A 1-V MOSFET-only fully-differential dynamic comparator for use in low-voltage pipelined A/D converters," in Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on, 2003, pp. 377-380.

[6]

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