Digital System Simulation with VHDL in a High-level Synthesis System Zebo Peng E-mail:
[email protected]
Abstract This paper presents the use of VHDL to simulate the intermediate design representation in a high-level synthesis system. The design representation is captured by an extended time Petri net notation and is used throughout the synthesis process. We have developed an algorithm to convert the design representation into a VHDL description. As a result, digital system designs can be simulated together with the behavioral models of the primitive register-transfer level components which are also described in VHDL. The main feature of our approach is that the intermediate results (as well as the final results) of the high-level synthesis process can be simulated at any time and the simulation results can be used to guide the synthesis process. This work has been supported by the Swedish National Board for Industrial and Technical Development (NUTEK). Published in Microprocessing and Microprogramming, the EUROMICRO Journal, Vol 35, 1992
IDA Technical Report 1994 LiTH-IDA-R-94-02 ISSN-0281-4250
Department of Computer and Information Science, Linköping University, S-581 83 Linköping, Sweden
Digital System Simulation with VHDL in a High-level Synthesis System Zebo Peng Dept. of Computer and Information Science Linköping University S-581 83 Linköping, Sweden E-mail:
[email protected] This paper presents the use of VHDL to simulate the intermediate design representation in a high-level synthesis system. The design representation is captured by an extended time Petri net notation and is used throughout the synthesis process. We have developed an algorithm to convert the design representation into a VHDL description. As a result, digital system designs can be simulated together with the behavioral models of the primitive register-transfer level components which are also described in VHDL. The main feature of our approach is that the intermediate results (as well as the final results) of the high-level synthesis process can be simulated at any time and the simulation results can be used to guide the synthesis process.
1. Introduction A high-level synthesis system takes an abstract behavioral specification as input and generates an implementation structure at register-transfer level as output. The VHDL language [VHDL 87], with its rich functionality and multi-level description capability, has been used for many different purposes in high-level synthesis. It has been used, for example, to capture the input specification [Cam 91] and [Pos 91], to model the designs at varying levels [Lis 89], and to perform design simulation [Ber 91]. In this work, we have addressed the problem of how to use VHDL to simulate the intermediate design representations of the high-level synthesis process. This work has been carried out with the continuous development of the CAMAD synthesis system [Pen 89]. The current version of the CAMAD system takes a high-level algorithmic specification and generates a net-list description of the data path as well as a microprogram for the controller. The net-list description specifies the primitive components of a design as well as their connections. The components are defined by a component (module) library which consists of all available components (modules) and their parameters, such as estimated layout area and typical timing information. Most of other high-level synthesis systems use a flat list of informal descriptions of components. In our approach, VHDL is used to specify both the functionality and the implementation attributes of the components. As a result, a hierarchical organization of the components is obtained, components with many different levels of granularity can exist simultaneously in the library, and automatic selection of components during the synthesis process is made possible. One of the main objectives of the current work is to make it possible to simulate intermediate as well as final designs of the high-level synthesis process so that the behavior of a design can be verified at an early design
This research has been supported by the Swedish National Board for Industrial and Technical Development (NUTEK).
phase and at the same time the simulation results can be used to guide the synthesis process. To achieve this, the intermediate design representation of CAMAD is automatically converted into an equivalent VHDL description, which is then simulated with behavioral models of the primitive components and the user-specified input stimuli using existing VHDL simulation tools. Since the design representation of CAMAD is used throughout the whole synthesis process, both intermediate and final results of CAMAD can be simulated using the same mechanism/tool and multi-level simulation is achieved. Related work in this area, on the other hand, usually uses different models/methods to simulate the different levels/domains of designs and therefore the simulation results are sometimes difficult to be interpreted and compared. With our approach, it is very straightforward to interpret and use the simulation results since they are all referred to the same design representation model. The rest of this paper is organized as follows. Section 2 presents an overview of the CAMAD high level synthesis system together with a discussion of how the VHDL simulator interacts with the other tools. We describe then the use of VHDL to capture the semantics of the basic register-transfer level components in section 3. The algorithm used to convert the design representation of CAMAD into a VHDL description is presented in section 4, where the use of a VHDL simulator to simulate the design representation is also described. We finish the paper with a final discussion and a short summary of the results in section 5.
2. The CAMAD High-Level Synthesis System The CAMAD system is built on top of a unified design representation model used to capture the design (or partial design) during the high-level synthesis process. This design representation is based on an extended timed Petri net description (the ETPN model) which consists of separate but related models of control and data path [Pen 88]. The data path of ETPN is represented as a directed graph with nodes and arcs. The nodes are used to capture data storage and manipulation units and the arcs represent the connections of the nodes. The control part of ETPN, on the other hand, is captured as a timed Petri net with restricted transition firing rules. A very simple example of ETPN is illustrated in Fig. 1. Fig. 1(b) shows the data path where each data path node is depicted as a rectangle with a label indicating the basic operation of the node. The arcs of the data path represent the data flow between the nodes. Flow of data from one node to another is controlled by the control signals coming from the control part. The control relation is indicated by using control place names to guard the arcs. Fig. 1(a) depicts the Petri net which represents the control flow of the example. A control state is represented as a marking of the Petri net, i.e., the possession of tokens in a subset of the places of the Petri net which are depicted as circles. The transitions of control states are represented as firings of one or several transitions of the Petri net which are depicted as bars. This ETPN example is generated by CAMAD as the compilation output of the input ADDL specification given in Fig 1(c). The main feature of the ETPN design representation is its ability to capture the intermediate result of a design explicitly so as to allow the design algorithm to make accurate design decisions. For example, if several operations are not data-dependent and can thus be executed concurrently, the situation can be captured precisely by giving their associated control places in the Petri net a potential to hold tokens simultaneously. That is, the set of Petri net places corresponding to the operations will not have any partial ordering relation between them. For example, in Fig. 1, P2 and P7 control the loading of initial data to register X and Y respectively, which are independent operations. Therefore, P2 and P7 can hold token simultaneously. When it is, however, discovered later that the potential parallelism will not be able to be implemented, some partial ordering relations can be introduced into the set of Petri net places by performing a place-stretch transformation [Pen 89]. As in the above example, if both register X and Y are loaded via I/O pins and it is too expensive to implement two set of I/O pins, P2 and P7 can be stretched so that either P2 will follow P7 or vice versa and thus only one set of I/O pins will be needed.
P0
“1”
PI
P2
P7
P4
Y
P7
P2
“0”
P5
P5 P6
P3 C1
P5
P3
+
C1
P6
P4
P1
P5
“0”
X
P3
> P3 C1
PO (b) Data path
BEGIN COBEGIN X := 1; Y := 0; COEND; WHILE X > 0 DO (a) Control Petri net BEGIN Read(X); Y := Y + X; END; (c) ADDL description Write(Y) END.
/P0/ /P7/ /P2/ /P3/ /P4/ /P5/ /P6/ /P1/
Fig. 1 An example of the ETPN representations and its corresponding ADDL description In general, given an intermediate synthesis result represented in the ETPN form, an algorithm can be used to calculate, for example, its implementation cost, check whether the cost satisfies the design constraints, and automatically choose a transformation to apply to the design to produce another intermediate result with improved outcome. CAMAD utilizes such an iterative transformation approach to carry out the synthesis tasks. That is, it first generates a preliminary (default) design from the input specification which is written in the ADDL language (Algorithmic Design Description Language, a subset of PASCAL with several extensions to capture parallelism and hardware specific operations). It then applies design transformations one by one to the preliminary design so as to obtain better results. These transformations deal with design decisions concerning operation scheduling, data path/control allocation, or optimization of the current design. This iterative process is finished when a satisfactory result has been reached. The data path is then transformed into a net-list and the control part into a microprogram. The netlist and the microprogram together form the RT-level implementation of the input specification. This process is illustrated in Fig. 2. With the development of the VHDL simulator described in this paper, it is possible to simulate the intermediate as well as the final results of CAMAD, as indicated in Fig. 2. The simulation of a design is achieved by converting the ETPN description into a VHDL program and linking it with the basic component descriptions which are also specified by VHDL. After the design is simulated with some user-specified input stimuli (which usually corresponds to the typical input data of the designed system), the simulation results can then be interpreted by the designers and used to interactively guide the design transformations using the interactive mode of the CAMAD system [Pen 89]. For
ADDL Input Specification ADDL Compiler
Scheduling Allocation Optimization
ETPN Controller
Controller Implementation
ETPN Data Path
Netlist Generation
VHDL Input Stimuli
VHDL Generator
VHDL Simulator
VHDL Component Descriptions
RT-level Design Fig. 2 The high-level Synthesis Process of CAMAD example, if the performance of a given critical path of the current ETPN design cannot satisfied the given design constraint, the designers can instruct CAMAD to select performance improvement transformations to apply to the related data part of the design. This can be easily done by indicating to CAMAD the related critical path and letting CAMAD to use performance as the first criterion for selecting transformations [Pen 89].
3. Component Descriptions with VHDL In order for CAMAD to make accurate simulation of an ETPN design so as to estimate, for example, its performance in respect to two given states, the component library which consists of all the available basic components must provide information about different parameters (attributes) of the components. More importantly, the component library must contain semantics information of the components so that the synthesis algorithms know precisely what the functions of the different components are and how to simulate them. Previous work has used either a procedural representation of the component library where the component specification is embedded in the algorithms, or a very simple declarative structure of components of a single technology. The current work enhances declarative representation of multiple-technology component library and its integration into the synthesis process. It improves also the flexibility of the CAMAD system as the VHDL component specifications are independent of any specific technology or vendor. Each component of the CAMAD component library is described by a VHDL entity. The entity declaration specifies the name and the input/output port structure of the component together with possible parameterized information. An architecture body is used to specify the semantics of the component. The following example illustrates the specification of the basic semantics of a combinational component. entity Add16 is port(Ip1, Ip2 : in Unsigned16; --inputs Op1 : out Unsigned16); -output end Add16;
architecture behavior of Add16 is begin Op1
