“resist core” spacer patterning process for the

The “resist core” spacer patterning process for the fabrication of 2xnm-node semiconductor devices *Koutarou Sho, Tomoya Oori, Kazunori Iida, Katsutoshi Kobayashi, Keisuke Kikutani, Katsumi Yamamoto, Fumiki Aiso, Kentaro Matsunaga, Eishi Shiobara, Koji Hashimoto

TOSHIBA Corporation

Outline
Introduction
Issues on Resist Core Spacer Process


Results and Discussions
Hard Mask Stack Optimization
Resist Profile Improvement
Profile After Lithography
Profile After Resist Slimming
Profile After ULT Spacer Deposition


Conclusion 2

k1 Trends and Lithography Technologies

k1=HP(NA/λ)

0.5 0.4

EUVL

CMOS Metal 45nm node 32nm node

0.3

NAND

22nm node 56nm HP

43nm HP

0.2

3x nm HP 2x nm HP

0.1

1.0NA < 0

2x nm HP

2004

2005

2006

2007

1.3NA < 2008

2009

Year

1x nm HP

DPT 2010

2011

2012

* DPT: Double Patterning Technology

Double-patterning technology (DPT) becomes a candidate for patterning with low-k1 lithography. 3

2013

Double-Patterning Technology (i)

(1) Spacer Process Spacer

Hard Mask Core Spacer Resist

Hard Mask

BARC

Substrate

Hard Mask

(2) LELE (Litho Etch Litho Etch)

Substrate

(ii)

Resist

BARC Core Spacer

BARC

Resist

Substrate

BARC

(3) LLE (Litho Litho Etch)

Substrate

(iii) Resist Core Spacer Resist Substrate

Substrate

Spacer process is one of the strongest candidates for DPT, and resist core spacer is most simple and is lowest in cost among the above spacer processes. 4

Advantage of Resist Core Spacer Process Hard Mask Core Spacer After Litho

BARC Etch

Template Etch

Template Slimming

Spacer Deposition

Etch Back

Core Strip

Double Patterning

Resist BARC Hard mask Substrate

Ultra Low Temperature (ULT) Oxide Spacer

Resist Core Spacer Mask- a-Si

ULT oxide enables direct formation of spacer over the resist core and simplifies the spacer process. In this study, the feasibility of the resist core spacer process to 2x nm-node devices was evaluated. 5

Issues on Resist Core Spacer Process Line & Space Pattern After Litho

Profile After Lithography Anti-reflective Stacks

BARC HM

Profile After Slimming

Resist Slimming

Profile After ULT Spacer Deposition

Spacer Deposition

Etch Back & Core Strip

Hard Mask Stacks Etching Conditions

Double Patterning

Key issues : 1) hard mask stacks (anti-reflective stacks) 2) resist profile 6

Hard Mask Stack Optimization Hard Mask Stack 1

Hard Mask Stack 2

(Organic BARC/CVD-Carbon HM)

(Dual CVD-C HM)

Organic BARC_70 nm

CVD-C HM1_30 nm

CVD-C HM_200 nm

CVD-C HM2_170 nm

SiO2_200 nm

SiO2_200 nm

Hard mask stacks 1 and 2 were studied for anti-reflective performance and for hard mask etching performance. The Dual CVDC HM stack controls reflectivity by stacking two CVD-C HM of different optical property. 7

reflectivity

Anti-reflective Performance 0.1 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0

Hard Mask Stack 1 (BARC/CVD-C) Hard Mask Stack 2 (Dual CVD-C)

0

10 20 30 40 50 60 70 80 90 100 110

BARC Thickness (nm)

Both stacks are applicable from a reflectivity standpoint, showing reflectivity below 1%. 8

Hard Mask Etching Performance After Litho (48nm L/S)

ULT Spacer Deposition

Etch Back & Core Strip

BARC Etch

Carbon Etch

Hard mask stack 1 (Dual CVD-C HM)

Hard mask stack 2 (Organic BARC / CVD-C HM)

Side etch profile was observed in organic BARC because of its high etch rate. Therefore, dual CVD-C stack was selected as the hard mask stack. 9

Profile After Lithography Illumination Condition

Resist

Condition A

Condition B

X-pole

Dipole

Resist A

Resist B

Resist Profile

These two lithographic conditions having different resist profile were compared in order to study their effect on pattern transfer performance. 10

Resist Profile vs. Etched Profile After Litho

ULT Spacer Deposition

Carbon Etch

Condition A (X-pole)

Condition B (Dipole)

The initial resist profile, especially at the bottom, is very important for etching CVD carbon successfully. 11

Profile After Resist Slimming Initial (After Litho)

Wet Slimming

Dry Slimming

93.8

82.7

84.9

-

11

9

Top CD [nm]

46.8

29.2

30.5

Bottom CD [nm]

43.2

32.4

29.7

Bottom CD – Top CD [nm]

-3.6

3.2

-0.8

Resist Profile Top Bottom

70 nm 5 nm

Height [nm] Thickness Loss [nm]

Wet and dry slimming methods were compared in terms of resist profile. Dry slimming showed less resist thickness loss and more rectangular resist profile. Therefore, dry slimming was applied. 12

Profile After ULT Spacer Deposition X-SEM

After Litho

After Dry Slim.

After ULT Spacer

93

81.8

87.4

Top [nm]

38.3

25

18.2

Middle [nm]

42.4

28.1

27.4

Bottom [nm]

44.6

27.9

32.3

Tilt

Side Top

70 nm

Middle

40 nm

Bottom

5 nm

Height [nm]

Effect of ULT spacer deposition on the resist profile was studied. 13

CD Variation Before and After ULT Deposition 50 45

Top

70 nm

Middle

40 nm

Bottom

5 nm

CD (nm)

40 35

Top Middle Bottom

30 25 20 15 10 After Litho

After Dry slim.

After ULT depo.

Rectangular resist profile was obtained after development and after dry slimming. However, after ULT deposition, resist profile becomes more tapered, possibly due to stress induced by the ULT spacer. 14

Optimization of CVD-C Etch and SiO2 Etch After CVD-Carbon Etch

After SiO2 Etch

LWR： ： 5.3 nm

LWR： ： 4.8 nm

Trace ULT Roughness Top ULT Spacer Tilting Inward

Optimization of CVD-C Etch and SiO2 Etch Conditions.

LWR: 2.4 nm

By optimizing the etching conditions, profile after SiO2 etch was improved. 15

Summary of Process Optimization After Litho

After Slim.

After ULT Spacer

・Dual CVD-C HM ・Dry Slimming ・Condition B

After Carbon Etch

After SiO2 Etch

・Etching Condition Tuning

LWR： ： 5.3 nm

LWR: 2.4 nm

CDU (3σ σ): 1.2nm

By the optimization of the resist core spacer process, pattern transfer to 200 nm SiO2 was successfully demonstrated. 16

Conclusion •The feasibility of resist core spacer process to 2x nmnode devices was evaluated. •The following key technologies were investigated and optimized. • Dual CVD-C hard mask stack was selected. • Rectangular resist profile after development was found to be very important. • Dry slimming method was selected for the resist slimming. • Influence of ULT spacer deposition on resist profile was studied. • Conditions for CVD-C etch and of SiO2 etch were tuned.

•Pattern transfer for 2x nm-node device was achieved. • Good LWR after SiO2 etch (3σ σ:2.4 nm) was obtained.

17

Acknowledgements Motoyuki Shima, Norihiko Sugie JSR Corporation

DPT development group TEL Corporation

18

19