CMOS SOI Distributed Amplifiers for New

´ CATHOLIQUE DE LOUVAIN UNIVERSITE ´ LABORATOIRE D’HYPERFREQUENCES Louvain-la-Neuve

CMOS SOI Distributed Amplifiers for New Communication Systems

Jury

Mehdi SI MOUSSA

Prof. L. Vandendorpe (Président) Prof. D. Vanhoenacker-Janvier (promoteur) Prof. J.-P. Raskin Prof. D. Macq Prof. F. Danneville Prof. J.-L. Gautier

Thèse présentée en vue de l’obtention du grade de docteur en Sciences Appliquées

September, 2006

Remerciements Je souhaiterais tout d’abord remercier et exprimer toute ma gratitude ` a mon promoteur, le Professeur Danielle Vanhoenacker-Janvier pour m’avoir accueilli au sein du Laboratoire d’Hyperfréquences (EMIC) et pour la confiance qu’elle m’a accordé tout au long de cette thèse de doctorat. Je voudrais remercier également le Professeur Jean-Pierre Raskin du laboratoire EMIC pour sa disponiblité et ses conseils toujours avisés qui m’ont permis d’aller de l’avant, ainsi que le Professeur Fran¸cois Danneville du laboratoire IEMN pour son apport scientifique et technique qui m’a beaucoup aidé. Je remercie de même, les autres membres de mon jury de thèse: le Professeur Damien Macq d’AMIS, le Professeur Jean-Luc Gautier, Professeur ` a l’ENSEA de Cergy-Pontoise, ainsi que le président Professeur Luc Vandendorpe qui ont pris la peine de lire ce travail avec attention. Leurs commentaires et suggestions éclairés m’ont permis d’en améliorer le contenu. Je tiens ` a exprimer toute mon amitié aux docteurs: Christophe Pavageau ` a qui j’adresse une vive reconnaissance pour notre collaboration particulièrement enrichissante, A¨ımad Saib pour son aide précieuse en LATEX et Morin Dehan pour ses remarques toujours constructives ainsi qu’` a Pierre Delatte de CISSOID. Mes remerciements s’adressent ensuite ` a mes collègues du laboratoire EMIC: Annette, Christel, pour leur gentillesse, Pascal pour sa compétence et son assistance qui m’ont été d’un grand secours, ainsi que tous les doctorants qui m’ont accompagné durant ma thèse. Merci ` a Brigitte Dupont du laboratoire DICE et ` a Fran¸coise Vancaster de la bibliothèque des sciences exactes. Je tiens également ` a exprimer mes remerciements ` a l’équipe de l’IEMN, et tout particulièrement aux Docteurs Alexandre Siligaris et Guillaume Pailloncy, ainsi qu’` a Sylvie Lepilliet et au Professeur Gilles Dambrine pour leur aide prcieuse et leur disponiblilité. Enfin, j’adresse des remerciments chaleureux aux Professeurs Rabia Aksas et Mohamed Trabelsi de l’Ecole Nationale Polytechnique ` a Alger, ainsi que le Docteur Mourad Khanfouci qui m’ont initié au domaine des micro-ondes et plus spécialement celui des amplificateurs distribués. Pour conclure, j’aimerais dédier cette thèse ` a mes proches qui m’ont apporté encouragements et soutien continu: particulièrement ` a mes parents, ` a mon frère Seddik, ` a ma femme Samira, ` a mes ami(e)s qui se reconnaitront, puis ` a tous ceux qui partagent avec moi l’amour de la science.

TABLE OF CONTENTS Scientific publications

iv

Glossary

viii

List of Abbreviations

ix

List of Figures

x

List of Tables

xvii

Introduction

xix

1 Bulk CMOS vs. SOI

1

1.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1

1.2

SOI: Silicon On Insulator . . . . . . . . . . . . . . . . . . . . . . . . .

1

1.3

SOI advantages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3

1.4

SOI disadvantages . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5

1.5

Conclusion

5

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Concept of distributed amplifiers

11

2.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2

Concept of distributed amplification . . . . . . . . . . . . . . . . . . .

13

2.2.1

Advantages of DAs . . . . . . . . . . . . . . . . . . . . . . . . .

14

2.2.2

Disadvantages of DAs . . . . . . . . . . . . . . . . . . . . . . .

15

Other applications of DAs . . . . . . . . . . . . . . . . . . . . . . . . .

15

2.3.1

Power Combiner and Splitter . . . . . . . . . . . . . . . . . . .

15

2.3.2

Circulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15

2.3.3

Active Frequency Multiplier . . . . . . . . . . . . . . . . . . . .

16

2.3.4

Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

17

2.3.5

Active Impedance Transformer . . . . . . . . . . . . . . . . . .

17

2.3.6

Multidecade Oscillator . . . . . . . . . . . . . . . . . . . . . . .

18

2.3.7

2.3

2.4

2.5

11

Power-Distributed amplifier . . . . . . . . . . . . . . . . . . . .

18

Circuit principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

20

2.4.1

Image Parameter Method . . . . . . . . . . . . . . . . . . . . .

21

2.4.2

Comparison between cascaded and distributed amplifiers

. . .

23

Theoretical analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . .

26

2.5.1

Using two-port theory (Beyer model) . . . . . . . . . . . . . . .

26

2.5.2

Using the admittance matrix (Niclas model) . . . . . . . . . . .

29

i

2.6

2.5.3

Using the wave theory (McKay model) . . . . . . . . . . . . . .

31

2.5.4

Gain degradation . . . . . . . . . . . . . . . . . . . . . . . . . .

34

2.5.4.1

Passives losses . . . . . . . . . . . . . . . . . . . . . .

34

2.5.4.2

Transistor’s losses . . . . . . . . . . . . . . . . . . . .

38

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

41

Conclusion

3 Design of distributed amplifiers on SOI technology

45

3.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

45

3.2

Design methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . .

46

3.2.1

Choice of the transistor . . . . . . . . . . . . . . . . . . . . . .

49

3.2.2 3.3

Choice of the technology . . . . . . . . . . . . . . . . . . . . . .

50

Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

53

3.3.1

Step1: Specifications . . . . . . . . . . . . . . . . . . . . . . . .

53

3.3.2

Step2: Topology

54

3.3.3

Step3: Choice of the active device

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

54

3.3.4

Step4: Power and noise figure matching conditions

. . . . . .

59

3.3.5

Step5: Choice of a bias circuit . . . . . . . . . . . . . . . . . .

59

3.3.6

Step6: Basic circuit simulation and optimization . . . . . . . .

60

3.4

Common source distributed amplifier . . . . . . . . . . . . . . . . . . .

62

3.5

Measures and discussion . . . . . . . . . . . . . . . . . . . . . . . . . .

62

3.6

Cascode distributed amplifier . . . . . . . . . . . . . . . . . . . . . . .

64

3.7

Measures and discussion . . . . . . . . . . . . . . . . . . . . . . . . . .

69

3.8

Conclusion

3.7.1

Group delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Performances vs. Temperature

73 74 79

4.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

79

4.2

SOI at high temperature . . . . . . . . . . . . . . . . . . . . . . . . . .

80

4.3

Active devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

81

4.3.1

DC Measures . . . . . . . . . . . . . . . . . . . . . . . . . . . .

82

4.3.2

RF Measures . . . . . . . . . . . . . . . . . . . . . . . . . . . .

88

4.3.3

Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

92

Passive devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

93

4.4.1

Microstrip Lines . . . . . . . . . . . . . . . . . . . . . . . . . .

93

4.4.2

Coplanar Waveguide . . . . . . . . . . . . . . . . . . . . . . . .

96

4.4.3

Temperature behavior . . . . . . . . . . . . . . . . . . . . . . . 100

4.4.4

Resistivity Behavior . . . . . . . . . . . . . . . . . . . . . . . . 102

4.4.5

Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

4.4.6

Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

4.4

ii

4.5

4.6

Analysis of the designed DAs at high temperature . . . . . . . . . . . 107 4.5.1

Behavior of the CSDA at high temperature . . . . . . . . . . . 107

4.5.2

Behavior of the FBCDA at high temperature . . . . . . . . . . 109

4.5.3

Analysis and discussion . . . . . . . . . . . . . . . . . . . . . . 109

Conclusion

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

5 Optimized distributed amplifiers and oscillators

115

5.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

5.2

Distributed Amplifiers using DTMOS . . . . . . . . . . . . . . . . . . 115

5.3

5.4

5.2.1

DTMOS transistor . . . . . . . . . . . . . . . . . . . . . . . . . 116

5.2.2

Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

5.2.3

Measures and discussion . . . . . . . . . . . . . . . . . . . . . . 118

Distributed Amplifiers using CPW . . . . . . . . . . . . . . . . . . . . 120 5.3.1

Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

5.3.2

Measures and discussion . . . . . . . . . . . . . . . . . . . . . . 122

Distributed Oscillation . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 5.4.1

5.5

Distributed Oscillators . . . . . . . . . . . . . . . . . . . . . . . 126 5.4.1.1

Basic Phase Noise Theory . . . . . . . . . . . . . . . . 127

5.4.1.2

Topology . . . . . . . . . . . . . . . . . . . . . . . . . 129

5.4.1.3

Design and measurements . . . . . . . . . . . . . . . . 131

5.4.1.4

High temperature behavior . . . . . . . . . . . . . . . 135

Conclusion

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

6 Conclusion

141

A Gain formula of a distributed amplifier

I

A.1 What are the differences between power gain, transducer gain, available gain, and insertion gain? . . . . . . . . . . . . . . . . . . . .

I

A.2 Constant-k and m-derived filter . . . . . . . . . . . . . . . . . . . . . .

II

A.3 Gain of Distributed Amplifier . . . . . . . . . . . . . . . . . . . . . . .

II

B Transistor’s linear and non-linear models

VII

B.1 The AC model for SOI MOSFET . . . . . . . . . . . . . . . . . . . . . VII B.2 The non-linear model . . . . . . . . . . . . . . . . . . . . . . . . . . . . VII C Phase Noise Measurements with a Spectrum Analyzer

XI

C.1 Measurement procedure . . . . . . . . . . . . . . . . . . . . . . . . . . XII

iii

Scientific Publications

Articles in periodicals [1] C. Pavageau, M. Si Moussa, J.-P. Raskin, D. Vanhoenacker-Janvier, J. Russat, N. Fel, L. Picheta and F. Danneville “Design of cascode distributed amplifiers on 130 nm SOI CMOS technology,” IEEE Transactions on Solid-State Circuits (Submitted). [2] M. Si Moussa, C. Pavageau, D. Lederer, L. Picheta, F. Danneville, J. Russat, N. Fel, J.-P. Raskin and D. Vanhoenacker-Janvier, “Behavior of TFMS and CPW Lines on SOI Substrate versus High Temperature for RF Applications,” SolidState Electronics (Submitted). [3] M. Si Moussa, C. Pavageau, P. Simon, F. Danneville, J. Russat, N. Fel, J.P. Raskin and D. Vanhoenacker-Janvier, “Behavior of a common source traveling wave amplifier versus temperature in SOI technology, ” IEEE Transactions on Microwave Theory and Techniques, Vol. 54, N o 6. June 2006. pp. 2675- 2683. [4] M. Si Moussa, C. Pavageau, F. Danneville, J. Russat, N. Fel, J.-P. Raskin and D. Vanhoenacker-Janvier, “Behavior of a Traveling Wave Amplifier versus Temperature in SOI Technology,” Proceedings of the European Microwave Association Vol. 1; December 2005; pp. 288-292.

Conference Proceedings [1] M. El Kaamouchi, M. Si Moussa, J.-P. Raskin and D. Vanhoenacker-Janvier, “DTMOS Low Noise Amplifier Design in Partially Depleted SOI CMOS Technology”, in IEEE International SOI Conference, Niagara Falls, USA, October 2-5, 2006. (Accepted) [2] M. Si Moussa, C. Pavageau, F. Danneville, J. Russat, N. Fel, J.-P. Raskin and D. Vanhoenacker-Janvier, “Design of a Distributed Oscillator in 130 nm SOI MOS Technology, ”, 36th European Microwave Conference, (Manchester, UK), September 2006. (Accepted). [3] M. Si Moussa, M. EL Kaamouchi and D. Vanhoenacker-Janvier, “Design of RF amplifiers in 130 nm SOI Technology,” in Microwave Technology and Techniques Workshop, ESA, (Netherlands), May 2006. [4] M. Si Moussa, C. Pavageau, F. Danneville, J. Russat, N. Fel, J.-P. Raskin and D. Vanhoenacker-Janvier,“Design of Distributed Amplifiers and Oscillators iv

in 130 nm SOI MOS Technology, ” in IEEE MTT Wireless, Silicon Monolithic Integrated Circuits in RF Systems, (San Diego, USA), pp. 190–193, January 15-20 2006. [5] M. Si Moussa, C. Pavageau, P. Simon, F. Danneville, J. Russat, N. Fel, J.P. Raskin and D. Vanhoenacker-Janvier,“Behavior of a Common Source Traveling Wave Amplifier versus Temperature in SOI Technology, ” in Proccedings of the 35th European Microwave Conference, (Paris, France), pp. 1075–1078, 3-7 October 2005. [6] M. Si Moussa, C. Pavageau, D. Lederer, L. Picheta, F. Danneville, J. Russat, N. Fel, J.-P. Raskin and D. Vanhoenacker-Janvier,“An investigation of Temperature Effects on CPW and MSL on SOI Substrate for RF Applications, ” in IEEE International SOI Conference, (Hawaii, USA), pp. 70–71, 3-6 October 2005. [7] M. Si Moussa, C. Pavageau, F. Danneville, J. Russat, N. Fel, J.-P. Raskin and D. Vanhoenacker-Janvier,“Temperature Effect on the Performance of a Traveling Wave Amplifier in 130 nm SOI Technology, ” in IEEE Radio Frequency Integrated Circuits Symposium, (Long Beach, USA), pp. 495–498, 11-17 June 2005. [8] C. Pavageau, M. Si Moussa, A. Siligaris, L. Picheta, F. Danneville, J.P. Raskin, D. Vanhoenacker-Janvier, J. Russat and N. Fel, “Low Power 23-GHz and 27-GHz Distributed Cascode Amplifiers in a Standard 130 nm SOI CMOS Process, ” in IEEE MTT - S International Microwave Symposium, (Long Beach, USA), pp. 2243–2246, 11-17 June 2005. [9] C. Pavageau, M. Si Moussa, A. Siligaris, L. Picheta, F. Danneville, J.P. Raskin, D. Vanhoenacker-Janvier,J. Russat and N. Fel, “Amplificateur distribué en bande K avec la technologie CMOS SOI 130 nm,” in Proceedings of the XIVmes Journes Nationales Microondes (JNM), (Nantes, France), May 2005. [10] M. Si Moussa, C. Pavageau, F. Danneville, J. Russat, N. Fel, J.-P. Raskin and D. Vanhoenacker-Janvier,“Design of a travelling wave amplifier in 0.13 um partially depleted SOI, ”in First Workshop of the Thematic Network on SOI Technology, Devices and Circuits, (Granada, Spain), pp. 143–144, 19-21 January 2005. [11] F. Iker, M. Si Moussa, J.-P. Raskin and D. Vanhoenacker-janvier, “ RF Circuits and MEMS Devices in Thin Film SOI Technology,” in Proceedings of Union Radio-Scientifique Internationale (URSI), (Brussels, Belgium), p. 66 December 10, 2004. [12] M. Si Moussa and D. Vanhoenacker-janvier, “ A 1 - 27 GHz distributed amplifier in 130 nm SOI technology,” in Proceedings of Union Radio-Scientifique Internationale (URSI), (Brussels, Belgium), p. 51 December 10, 2004. v

[13] F. Iker, M. Si Moussa, N. André, T. Pardoen and J.-P. Raskin, “ CMOS compatible 3-D self assembled microstructures using thin film SOI technology,” in Proceedings of IEEE Sensors, (Vienna, Austria), p. 1113–1116 October 24-27, 2004. [14] M. Si Moussa and D. Vanhoenacker-janvier, “Design of a fully integrated distributed amplifier in SOI technology,” in Proceedings of Union Radio-Scientifique Internationale (URSI), (Brussels, Belgium), p. 39 December 18, 2003. [15] M. Si Moussa and D. Vanhoenacker-janvier, “Design of a distributed amplifier in SOI technology,” in Proceedings of Union Radio-Scientifique Internationale (URSI), (Royal Military Academy, Brussels, Belgium), December 13 2002.

Seminars and Short-Courses [1] C. Pavageau, M. Si Moussa, P. Simon, F. Danneville, J. Russat and N. Fel, “130 nm SOI CMOS Distributed Amplifier,” in M+ T206 SOI project 2004 workshop, (Crolles, France), April 4 2006. [2] M. Si Moussa, C. Pavageau, F. Danneville, J.-P. Raskin and D. VanhoenackerJanvier, “Design of a Traveling-Wave Amplifier in 130 nm SOI technology,” in WS Labo-Commun EMIC-IEMN, (Louvain la Neuve, Belgium), May 2 2005. [3] C. Pavageau, M. Si Moussa, A. Siligaris, L. Picheta, F. Danneville, J.-P. Raskin, D. Vanhoenacker-Janvier,J. Russat and N. Fel, “Conception d´’amplificateurs distribués en bande K avec la technologie SOI-PD 130 nm” in WS Labo-Commun IEMN-ST-Microelectronics, (Crolles, France), March 22 2005. [4] D. Lederer, P. Delatte, M. Si Moussa, D. Vanhoenacker-Janvier and J.P. Raskin, “Crosstalk, lines and RF MOSFETs,” in M+ T206 SOI project 2004 workshop, (Crolles, France), November 25,26 2004. [5] C. Pavageau, M. Si Moussa, A. Siligaris, L. Picheta, F. Danneville, J.-P. Raskin, D. Vanhoenacker-Janvier,J. Russat and N. Fel, “Design of K-band Distributed Amplifiers using FB and BC MOS,” in MEDEA+ T206 SOI Workshop, STMicroelectronics, (Crolles, France), November 25,26 2004. [6] M. Si Moussa,C. Pavageau, F. Danneville, J.-P. Raskin and D. VanhoenackerJanvier, “Design of 1 - 27 GHz distributed amplifier in 130 nm SOI technology,” in Medea+ 4G-Radio Workshop on SOI Technology for RF Applications, (Louvain la Neuve, Belgium), October 25 2004. [7] F. Iker, M. Si Moussa, J.-P. Raskin and D. Vanhoenacker-janvier, “ RF Circuits and MEMS Devices in Thin Film SOI Technology,” in MIGAS’2004, (Grenoble, France), June 27-July 02 2004.

vi

Glossary

LIST OF ABBREVIATIONS BC

Body-Contacted

BCDA

Body-Contacted Cascode distributed Amplifier

CDA

Cascode distributed Amplifier

CDO

Cascode Distributed Oscillator

CMOS

Complementary Metal-Oxide Semiconductor

CPW

CoPlanar Waveguide

CSDA

Common Source Distributed Amplifier

DA

Distributed Amplifier

DC

Direct Current

DO

Distributed Oscillator

DTMOS

dynamic Threshold MOSFET

FB

Floating-Body

FBDA, FBCDA

Floating-Body Cascode distributed Amplifier

FET

Field-Effect Transistor

GBW

Gain-BandWidth

HR

High Resistivity

IC

Integrated Circuits

MESFET

MEtal-Semiconductor Field Effect Transistor

MOSFET

Metal-Oxide-Semiconductor Field-Effect Transistor

PD

Partially Depleted

RF

Radio Frequency

SOI

Silicon-on-Insulator

STD

Standard Resistivity

TFMS

Thin Film MicroStrip

ix

LIST OF FIGURES 1

Worldwide Market for Silicon-on-Insulator Technology, 2002-2008 (In2 and $ Millions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxii

2

Application Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiii

3

Block diagram of a 40 Gbps fiber-optic transmission system. . . . . . . xxv

1.1

Five layer metal CMOS SOI device . . . . . . . . . . . . . . . . . . . .

2

1.2

Cross section of a bulk (a) and a SOI (b) MOSFET. . . . . . . . . . .

3

1.3

Cross section of (a) MESFET and (b) MOSFET. . . . . . . . . . . . .

7

2.1

Reactively matched amplifier. . . . . . . . . . . . . . . . . . . . . . . .

11

2.2

Lossy matched amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . .

12

2.3

Feedback amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12

2.4

Distributed amplifier.

. . . . . . . . . . . . . . . . . . . . . . . . . . .

13

2.5

Basic scheme of active combiner and splitter circuits. . . . . . . . . . .

16

2.6

Basic scheme of an active circulator. . . . . . . . . . . . . . . . . . . .

17

2.7

Basic scheme of an active frequency multiplier. . . . . . . . . . . . . .

17

2.8

Basic scheme of an active mixer. . . . . . . . . . . . . . . . . . . . . .

18

2.9

Basic scheme of an active impedance transformer. . . . . . . . . . . . .

19

2.10 Basic scheme of a distributed oscillator. . . . . . . . . . . . . . . . . .

19

2.11 The distributed amplification. . . . . . . . . . . . . . . . . . . . . . . .

20

2.12 Lossless elementary section of the:(a) gate line (b) drain line. . . . . .

21

2.13 Two port network. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

21

2.14 A two-port network terminated by its image impedance. . . . . . . . .

22

2.15 Artificial transmission line. . . . . . . . . . . . . . . . . . . . . . . . .

23

2.16 Bisected-π m-derived matching network. . . . . . . . . . . . . . . . . .

23

2.17 Multiamplifier structure: (a) cascade; (b) distributed. . . . . . . . . .

24

2.18 Cascaded FET amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . .

25

2.19 Cascaded (line) and distributed amplifier (dots) gain with four MOSFETs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

26

2.20 The simplified equivalent circuit of the transistor. . . . . . . . . . . . .

27

2.21 (a) Gate transmission line. (b) Drain transmission line.

28

. . . . . . . .

2.22 Equivalent four-port representation of the elementary circuit of a DA in its general form. . . . . . . . . . . . . . . . . . . . . . . . . . . .

30

2.23 Elementary section of a bilateral distributed amplifier. The variables bn and an represent the scattering waves. . . . . . . . . . . . . .

32

2.24 T section network. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

35

2.25 Elementary section of the:(a) gate line (b) drain line. . . . . . . . . . .

36

xi

2.26 Attenuation on gate line versus normalized frequency . . . . . . . . . .

36

2.27 Attenuation on drain line versus normalized frequency . . . . . . . . .

37

2.28 A short length of microstrip line and its equivalent circuit. . . . . . . .

37

2.29 High Frequency Small-Signal Model for a common-source SOI MOSFET. 39 2.30 Frequency response of a 4 section DA using 30 × 2 × 0.13 µm SOI

FB transistor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

39

2.31 Impact of the line losses on the gain of the DA. . . . . . . . . . . . . .

40

3.1

Design methodology for the conception of a distributed amplifier. . . .

47

3.2

Small signal MOSFET SOI transistor including intrinsic and ex. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

47

3.3

Common configuration of a DA. . . . . . . . . . . . . . . . . . . . . . .

47

3.4

Single section of the DA. . . . . . . . . . . . . . . . . . . . . . . . . . .

48

3.5

Cross section of a MOSFET transistor in SOI technology. . . . . . . .

50

3.6

Cross section of a MOSFET transistor in STM SOI technology. . . . .

51

3.7

SEM photograph of a PD SOI MOSFET transistor in 130 nm technology. 52

3.8

Cut-off frequencies of PD SOI MOSFET transistor in 130 nm technology. 52

3.9

Influence of the number of stages on the gain of a distributed amplifier. 53

trinsic elements.

3.10 MOSFET on 130 nm SOI CMOS Technology. . . . . . . . . . . . . . .

54

3.11 DA section illustrated with transmission line components replaced with Π model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

55

3.12 TFMS on 130 nm SOI CMOS Technology. . . . . . . . . . . . . . . . .

56

3.13 Measured and HF SS

r

simulated attenuation for a 2 µm wide

TFMS line. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

57

3.14 Comparison of measured lines losses for a 50 Ω TFMS using or not Alucap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

58

3.15 Impact of the line losses on the gain of the DA. . . . . . . . . . . . . .

58

3.16 Equivalent circuit of MOSFET including two uncorrelated noise sources. 60 3.17 Basic distributed amplifier. . . . . . . . . . . . . . . . . . . . . . . . .

61

3.18 Common source distributed amplifier. . . . . . . . . . . . . . . . . . .

61

3.19 Chip microphotograph of the designed CSDA. . . . . . . . . . . . . . .

62

3.20 Simulated and measured data for (top) power gain and input reflection coefficient, (bottom) noise figure and output return loss for the CSDA at room temperature. . . . . . . . . . . . . . . . . . . .

63

3.21 Cascode distributed amplifier. . . . . . . . . . . . . . . . . . . . . . . .

65

3.22 Loss compensation circuit. . . . . . . . . . . . . . . . . . . . . . . . . .

66

3.23 Chip microphotograph of the designed CDA. . . . . . . . . . . . . . .

67

3.24 Floating Body and the Body Contacted SOI transistors. . . . . . . . .

68

xii

3.25 Comparison between the Floating Body and the Body Contacted architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

68

3.26 Reduction of the ripple using the cascode topology. . . . . . . . . . . .

69

3.27 Measured values of Cgs and Cgd for BC and FB SOI transistors. . . .

70

3.28 Measured gain and input return loss (top), noise figure and output return loss (bottom) for the BCDA and FBDA at Vdd = 1.4 V . . . . . 3.29 1 dB compression point @ 5 (top) and 10 (bottom) GHz.

. . . . . . .

71 72

3.30 Simulated power gain and output power at 1 dB compression as a function of power consumption at 15 GHz, for the BCDA. . . . . . . 3.31 Measured group delay for the FB and BC CDA.

72

. . . . . . . . . . . .

73

Partially depleted SOI MOSFET transistor. . . . . . . . . . . . . . . .

82

4.2

Ids vs. Vgs @ saturation Vds = 1.2 V . . . . . . . . . . . . . . . . . . . .

83

4.3

Measured threshold voltage versus temperature. . . . . . . . . . . . . .

84

4.4

Output conductance gd for Vgs=0.3, 0.6 and 0.9 V. . . . . . . . . . . .

84

4.5

Output conductance gd dependence on temperature. . . . . . . . . . .

85

4.6

Gate transoncductance gm @ saturation for different temperatures. . .

86

4.7

Ids vs. Vds for Vgs=0.3, 0.6 and 0.9 V. . . . . . . . . . . . . . . . . .

86

4.8

Temperature increase effect on a PD SOI. . . . . . . . . . . . . . . . .

87

4.9

Ft and Fmax versus T. . . . . . . . . . . . . . . . . . . . . . . . . . . .

89

4.10 Measured input capacitance Cgs versus temperature. . . . . . . . . . .

90

4.11 Measured Miller capacitance Cgd versus temperature.

. . . . . . . . .

90

4.12 Measured output capacitance Cds versus temperature. . . . . . . . . .

91

4.13 Top view (a) and cross section (b) of TFMS. . . . . . . . . . . . . . .

94

4.1

4.14 Chip microphotograph of the designed TFMS calibration kit. . . . . .

95

4.15 Geometry of TFMS. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

95

4.16 Measured losses for various TFMS line geometries. . . . . . . . . . . .

96

4.17 Effect of the Alucap layer on the losses. . . . . . . . . . . . . . . . . .

97

4.18 Top view (a) and cross section (b) of CPW. . . . . . . . . . . . . . . .

97

4.19 Chip microphotograph of the designed CPW calibration kit. . . . . . .

98

4.20 Geometry of the designed CPW. . . . . . . . . . . . . . . . . . . . . .

98

4.21 Measured lineic losses of CPW on STD, HR substrate at room temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

99

4.22 Measured lineic losses of CPW on STD, HR @ room temperature. . .

99

4.23 Measured lineic losses vs. frequency and temperature (W = 7 µm). . . 100 4.24 Measured lineic losses vs. frequency of CPW on STD and HR Si Substrate (W = 40 µm, S = 24 µm). . . . . . . . . . . . . . . . . . . . 101 xiii

4.25 Comparison of measured lineic losses vs. temperature of CPW and TFMS @ 10 GHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 4.26 Losses versus frequency for TFMS lying on low (LR, 20 Ω.cm) and high (HR, > 1000 Ω.cm) SOI substrates. . . . . . . . . . . . . . . . . . 102 4.27 Measured lineic losses vs. frequency of CPW on STD and HR Si Substrate at room temperature (W = 40 µm, S = 24 µm). . . . . . . . 103 4.28 3D view of the measured transmission coplanar waveguide on standard substrate and transferred substrate on fused silica. . . . . . . . . 103 4.29 Extracted lineic losses on standard substrate, and transferred substrate on fused silica for the measured coplanar transmission line. . . . 104 4.30 Measured CSDA gain versus frequency at various temperatures (25, 50, 100, 150, 200, 250 and 300o C). . . . . . . . . . . . . . . . . . . 107 4.31 Contribution of the passive and active devices to the degradation of CSDA performance at 250o C. . . . . . . . . . . . . . . . . . . . . . 108 4.32 Measured FBCDA gain versus frequency for various temperatures. . . 109 4.33 Contribution of the passive and active devices to the degradation of CDA performance at 250o C. . . . . . . . . . . . . . . . . . . . . . . 110 5.1

Schematic (a) top view and (b) cross section of the body contact for a DT nMOSFET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

5.2

gm and gd versus drain current for a 30x2x0.13 FB et DT MOS SOI transistors (@ saturation: Vds = 1.2 V ). . . . . . . . . . . . . . . . 117

5.3

Layout of the designed CDA using DTMOS transistors. . . . . . . . . 118

5.4

Simulated and measured gains of the Common Source and Cascode CDA with FB and DTMOS transistors. . . . . . . . . . . . . . . . . . 119

5.5

Measured gains of the Cascode CDA with FB and DTMOS transistors. 119

5.6

CPW with its electromagnetic field. . . . . . . . . . . . . . . . . . . . 120

5.7

Measured and simulated power gain and noise figure of FB-DA with different transmission lines layout. . . . . . . . . . . . . . . . . . 121

5.8

(a) Layout and (b) Chip microphotograph of the CDA with CPW transmission lines (675 µm × 2180 µm). . . . . . . . . . . . . . . . . . 123

5.9

Simulated and measured S parameters of the designed FB CDA using CPW transmission lines. . . . . . . . . . . . . . . . . . . . . . . 124

5.10 SSB oscillator phase noise output spectrum. . . . . . . . . . . . . . . . 128 5.11 Definition of Phase Noise. . . . . . . . . . . . . . . . . . . . . . . . . . 128 5.12 Distributed amplifier and oscillator schematic. . . . . . . . . . . . . . . 129 xiv

5.13 Chip microphotograph of the designed CDA. T1 : common source transistor, T2 : common gate transistor, Cdec : decoupling capacitor.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

5.14 S21 module and phase of the designed CDA at room temperature. . . 130 5.15 Layout of the designed CDO. . . . . . . . . . . . . . . . . . . . . . . . 131 5.16 S parameters simulations of the CDO. . . . . . . . . . . . . . . . . . . 131 5.17 Power Spectrum of the designed CDO: first harmonic at 10 GHz. . . . 132 5.18 Detailed Power Spectrum of the designed CDO. . . . . . . . . . . . . . 133 5.19 Phase Noise of the designed CDO measured with the HP E4440A spectrum: (a) Phase Noise curve, (b) the Marker Noise. . . . . . . . . 134 6.1

State-of-the art of cascode distributed amplifiers in CMOS process. . . 143

6.2

Comparison of measured data and other published results with cascode architecture in SOI CMOS process. . . . . . . . . . . . . . . . 144

A.1 Elementary gate line section. . . . . . . . . . . . . . . . . . . . . . . .

II

A.2 Elementary drain line section. . . . . . . . . . . . . . . . . . . . . . . .

III

B.1 The RF model of the SOI MOSFET. . . . . . . . . . . . . . . . . . . . VII B.2 Schematic of the non linear model of the SOI MOSFET. . . . . . . . . VIII C.1 Block diagram of a spectrum analyzer. . . . . . . . . . . . . . . . . . . XII C.2 Setup for phase noise measurements. . . . . . . . . . . . . . . . . . . . XII C.3 Phase Noise of the designed CDO measured with the HP 8562 A spectrum. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XIV C.4 Power spectrum and Phase Noise of the designed CDO measured with the HP 8562 A spectrum, using the Lab-VIEW application. . . . XIV

xv

xvi

LIST OF TABLES 1.1

Comparison of fundamental material proprieties of Si and GaAs semiconductor technology . . . . . . . . . . . . . . . . . . . . . . . . .

6

3.1

Technology comparison. . . . . . . . . . . . . . . . . . . . . . . . . . .

46

3.2

Width dependence of different parameters of the small signal equivalent scheme of the MOSFET SOI transistor. . . . . . . . . . . . . . .

49

3.3

DC bias voltage distribution along the drain line. . . . . . . . . . . . .

60

3.4

CSDA design parameters on 130 nm SOI technology. . . . . . . . . . .

62

3.5

CDA design parameters on 130 nm SOI technology. . . . . . . . . . .

66

3.6

Comparison of the measured characteristics of the used FB and BC MOSFET transistors in 130 nm SOI technology. . . . . . . . . . .

69

3.7

Measured data of the designed 4-stage common source cascode DAs. .

74

3.8

Gain, Matching, Bandwidth, Area, Noise Figure, DC Power for state-of-the art DA’s. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1

75

Temperature requirements for electronics components used in several consumer or industrial applications . . . . . . . . . . . . . . . . .

80

4.2

Mitigation strategies for issues in harsh environment SOI (Honeywell)

81

4.3

Degradation of some measured parameters for the studied transistor from 25 to 250o C. . . . . . . . . . . . . . . . . . . . . . . . . . . .

91

4.4

TFMS calibration kit. . . . . . . . . . . . . . . . . . . . . . . . . . . .

94

4.5

Gain and bandwidth of the CSDA vs. temperature. . . . . . . . . . . . 108

4.6

Gain and bandwidth of the FBCDA vs. temperature.

5.1

Comparison of the measured characteristics of the used FB and

5.2

Measured and simulated data of 4-stage cascode DAs using differ-

. . . . . . . . . 109

DT MOSFET transistors in 130 nm SOI technology. . . . . . . . . . . 118 ent transmission lines layout. . . . . . . . . . . . . . . . . . . . . . . . 122 5.3

Measured data of 4-stage cascode DAs using TFMS and CPW different transmission lines. . . . . . . . . . . . . . . . . . . . . . . . . 125

5.4

Tuning of the SOI CDO. . . . . . . . . . . . . . . . . . . . . . . . . . . 133

5.5

State-of-the art DO’s. . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

5.6

CDO characteristics’ vs. temperature. . . . . . . . . . . . . . . . . . . 135

C.1 Correction factor in function of the IF filter accuracy. . . . . . . . . . XIII

xvii

Introduction

In recent years, the interest in wireless communication links and in the devices which can support those links has exploded. New standards are being designed in order to tap into the exploding market. In addition, the desire for Internet connectivity using cellular phones or Personal Digital Assistants (PDAs), i.e. Palm or handheld devices, has dramatically increased the demand for universal wireless connectivity. In order for these standards and the companies that support them to stay competitive, low-cost, small form-factor portable wireless communications devices are critical components. Cost is a very important concern to attract a large group of users. As such, the desire for a low-cost wireless device with reasonable performances has exploded as well. The current implementations, while they are becoming denser, are still extremely complex and do not conduct to significant reductions in cost and size without a radical change in thinking with regards to the implementation of the transceiver. To that end, the amount of investigation into the feasibility of using CMOS processes for the implementation of the circuitry used in these devices has dramatically increased as well. CMOS does provide an extremely low-cost technology to implement circuit blocks, along with the added benefit of potential large-scale integration. Because the baseband analog and digital chips are generally CMOS chips, building the high-frequency, high-performance chips in CMOS would allow those functions to be included in comprehensive, single-chip solutions. Currently, most commercially-available wireless solutions are multi-chip implementations, in which several different technologies, including silicon CMOS (Si-CMOS), silicon bipolar, Gallium Arsenide (GaAs), and/or Silicon Germanium (SiGe) are used. A CMOS implementation of the high-frequency analog section would facilitate the integration of all the radio functions (including high-frequency analog, baseband analog, A/D conversion, and DSP) onto a singlechip. Cost reductions coming with the integration of more functions onto one piece of silicon has been translated into the simplistic rule that every electronic system will eventually be resident on a single silicon chip. CMOS technology’s simplicity and attractive scaling characteristics were a fundamental driving force for Moore’s Law. Technologies such as bipolar and gallium arsenide (GaAs) maintained advantages xix

only for high-performance analogue RF microwave and millimeter-wave applications. With the evolution of analogue CMOS techniques and the displacement from analogue to digital signal processing (DSP), CMOS appeared destined to take all of the electronics pie. CMOS is capturing a significant portion of wireless RF applications with the promise of lower costs and higher levels of integration. Proponents of RF-CMOS believe the technology is overcoming its comparative performance limitations and is destined to supplant other technologies as the RF transceiver semiconductor technology of choice. The challenges facing designers and manufacturers of RF-CMOS wireless products are, however, quite substantial. Serious limitations to this technology remain and whether they can be resolved is hotly disputed. Issues such as noise, voltage swing, power consumption, process characterization, device modeling and substrate EM coupling, as well as system-on-chip (SoC) integration, all present significant barriers to broader RF-CMOS market penetration. On-chip precision passives and circuit design techniques, together with new design automation tools and approaches, show promises in reducing these barriers. In the meantime, silicon bipolar and GaAs technologies are not standing still. Silicon germanium (SiGe) has brought substantial improvements in bipolar performance, eclipsing CMOS. SiGe BiCMOS is giving product designers the performance of GaAs with integration levels and cost-effectiveness close to that of CMOS. GaAs, indium phosphide (InP) and other Group III-V semiconductor technologies are becoming more manufacturable, and are still superior to both SiGe and CMOS for power amplifiers, optical laser drivers, and other high voltage, very high-frequency applications. A major advantage of multi-chip over SoC approaches is the flexibility of being able to mix different technologies and components or intellectual property (IP). Designers can take advantage of the best semiconductor and passive technology for the job. This also means more flexible and cost-effective product changes.

SOI materiel Silicon on insulator (SOI) is a semiconductor wafer technology that produces higher performing, lower power (dynamic) devices than traditional bulk silicon techniques. SOI is obtained by placing a thin, insulating layer, such as silicon oxide or glass, between a thin layer of silicon and the silicon substrate. This process helps reducing the amount of electrical charge (limited to the channel) that the transistor has to move during a switching operation, thus making it faster and allowing it to switch using less energy. SOI chips can be as much as 15% faster and use 20% less power than toxx

day’s bulk complementary metal-oxide semiconductor (CMOS)-based chips [1]. SOI chips tend to cost more than their standard silicon counterparts, so SOI has been primarily used for high-end applications that can justify the incremental costs for the performance gain, such as portable computing devices. The higher speed and lower power offered by SOI chips have already proven the technology’s benefits in high-performance markets. Technology attributes that are important for this market segment are high speed at low total power and voltage, and reasonably low static power at elevated temperature. Since speed and switching power are an intrinsic advantage of SOI transistors due to their lower capacitance, this is a good match. In the area of RF and mixed signal applications, SOI offers the opportunity to enjoy the benefit of low noise and high-quality passives. These additional benefits will be leveraged in the future to truly expand SOI into a domain of SoC (system-on-a-chip) applications. To date, SOI has not proliferated broadly in the low-power market space, except in some applications such as portable computers and some other very specialized instances. The main reason is that low-power products are usually extremely cost sensitive, and SOI remains too expensive to justify the performance trade off. In the future, SOI has the potential to provide significant opportunities in low power.

Radical change is needed in the material structure, processing method, or device design to enhance integrated circuit (IC) performance. With the push for increasingly smaller devices, semiconductor manufacturers have faced three major challenges: reducing power consumption and heat dissipation and boosting device performance, all while accommodating scaling demands. With these growing needs, the industry is looking at innovative technologies, such as silicon-on-insulator (SOI), as a possible solution. By offering an opportunity to deliver higher speed, while also lowering power consumption, SOI was created to combat these bottlenecks. A 1945 patent on MOS transistor structure noted the advantages of having an oxide layer beneath the structure, but it was not until the 1990s that the manufacturing capabilities to create high-quality SOI wafers were in place. Now, SOI is seen as critical to extending the life of silicon technology. According to a report from Business Communications Company [2], despite the technology economy meltdown in the last few years, wafer demand has been on the strong side from an overall recovery perspective. The ramp up of 300-mm wafer demand has driven steady growth, resulting in a 34.2% surge in 2003 over 2002. This steeptrending growth is likely to be repeated, as the market grows at an average annual growth rate (AAGR) of 36.2%, increasing from $ 212 million in 2003 to $ 992 million xxi

by 2008. On an MSI (millions of square inch) basis, the SOI merchant wafer market is expected to expand at an AAGR of 34.5% from 40.6 in 2003 to 178.9 in 2008 (Fig. 1) [2].

Figure 1: Worldwide Market for Silicon-on-Insulator Technology, 2002-2008 (In2 and $ Millions) [2]. As the industry moves towards the era of the 300-mm wafer generation, cost reduction per chip will progress significantly to allow SOI device applications to expand from the midrange to the low-end segment. In particular, as the needs of the full depletion layer SOI device arise and vendors intensify development and production activities, 300-mm ultra thin film wafer demand will gain an impetus. While 300-mm SOI wafer prices remain lofty, the anticipated improvement of production techniques will likely lower the material cost per unit area below that for 200-mm wafers in the long term [2].

RF circuits The optimum technology choice for an RF application is complicated by issues of performance, wafer cost, integration and time-to market. GaAs has been used extensively for RF applications, but whenever cost and integration are important technology criteria, CMOS is an excellent choice. Low power consumption is particularly important in mobile communications due to limited battery life. One approach to meeting this challenge is to cerate a reduced power RF system-on-chip that contains digital, analog xxii

and RF portions of the design on the same die. Fig. 2 schematically presents the interplay among commercial wireless communication applications, available spectrum, and the kinds of elemental and compound semiconductors likely to be used [3].

Figure 2: Application Spectrum [3]. The boundary between the group IV semiconductors Si and SiGe and the III-V semiconductor GaAs has been moving to higher frequencies with time and for other applications the boundary between GaAs and InP is tending to shift to lower frequencies. And eventually, metamorphic high electron mobility transistors (MHEMTs) may displace both GaAs pseudomorphic high electron mobility transistors (PHEMTs) and InP high electron mobility transistors (HEMTs) for certain applications. As an example, SiGe HBT technology is already today very promising for 77 GHz automotive radar applications. The wide bandgap semiconductors such as SiC and GaN will be used for infrastructure such as base stations at frequencies typically above about 2 GHz. Increased interests for the 94 GHz band arises from its applications for all weather landing and other security needs [3]. However, the ever-increasing demand for more connectivity inevitably increases the complexity of such systems. Integrated systems and circuits continue to play a central role in the evolution of component design. One of the more common methods of increasing the bandwidth, and hence the bit rate, of any given system is to migrate to higher operating frequencies. The maximum speed of operation in electrical systems is determined by the performance of both active and passive devices. While xxiii

in modern integrated-circuit technologies the single-transistor maximum frequency of operation can be quite high, actual circuits rarely operate anywhere near these frequencies. This provides further motivation to pursue alternative approaches to alleviate bandwidth limitations, particularly in silicon-based systems which, despite their reliability, suffer from low transistor speed, poor passive performance, and high noise compared with other technologies. Distributed circuit and system design is a multi-level approach allowing more integral co-design of the building blocks at the circuit and device levels. This approach can be used to greatly alleviate the frequency, noise, and energy efficiency limitations of conventional circuits. Unlike conventional circuits, which often consist of a single signal path, distributed integrated systems and circuits rely on multiple parallel paths operating in harmony to achieve an objective. This concept can be best seen through the distributed amplifier (originally suggested by Percival and first implemented by Ginzton). Alternatively, one can think of this approach as a method of absorbing the parasitic capacitances of the transistors into the transmission lines and making them a part of the passive network [4]. This concept gives birth to a broadband amplification i.e. flat gain over several GHz.

This work In recent years, the rapid development of multimedia communications has generated a strong demand for high speed and high capacity transmission systems. High speed integrated circuit technologies with data rates of 40 Gbps are required for these systems. Fig. 3 shows a 40 Gbps fiber-optic transmission system. Although the input 40 Gbps data has various frequency components, a bandwidth greater than 40 GHz and a flat gain are required [5]. For such high bit rates, the distributed amplifier (DA) is an attractive option when operation at bit rates approaching the cut-off frequencies of the active devices is required. Therefore, a distributed amplifier is chosen for the modulator drive circuit. While a distributed amplifier is promising for use in this application, its electrical parameters must be finely optimized to meet the stringent requirements including high output power, high gain, flat gain and broad bandwidth. Through the years, the distributed amplifier has contributed to video amplification, pulse instrumentation, xxiv

Receiver

Transmitter LED

Modulator Modulator driver

Preamplifier

Gain 40 GHz

PIN photo diode

Frequency

Figure 3: Block diagram of a 40 Gbps fiber-optic transmission system. oscillography, radars systems, particle detection, broadband communication systems and various applications requiring wide-band amplification with good phase linearity [6]. This thesis, will address issues of design and modeling of distributed amplifiers on a commercially SOI CMOS technology. Studies of gain, bandwidth and high temperature behavior will be carried out. After showing the distributed amplifier’s architecture interest, and the design methodology, a characterization of the designed circuits is done versus frequency at room and high temperature, including a behavior study of the active and passive devices used in the design. Based on the “distributed architecture”, other designs are tested, like distributed oscillators to see the benefit of this design technique on the performances of the oscillator. The choice of SOI CMOS technology is related to the fact that it meets the modern RF communication systems requirements in term of low power consumption which is particularly important in mobile communications due to limited battery life, as shown in chapter 2. Chapter 3 explains the distributed amplifier’s architecture interest, showing the gain-bandwidth product interest comparing to other “traditional architecture”, especially for wideband applications. The different analysis methods exposed here have revealed that the transmission-line attenuation caused by the device parasitic resistances is the critical factor in the design of the amplifier. The next step was the conception of the DA on 130 nm CMOS SOI technology, xxv

following a design methodology based on the choice of the transistor. After a characterization of the designed circuits, the performances achieved by the cascode DA demonstrate the ability of standard SOI CMOS process for the jointed integration of microwave circuits together with high-speed DSP functions. Another issue is the high temperature applications. Indeed, SOI technology is emerging as the most mature solution for high temperature applications. The excellent behavior of SOI CMOS circuits at high temperature suggests the use of this technology for different applications. For this reason, the behavior of the DAs is investigated with respect to temperature. In the end, based on the “distributed architecture”, other designs were tested, like distributed oscillators to see the benefit of this design technique on the performances of the oscillator. A 10 GHz CMOS SOI cascode distributed oscillator (DO) is designed, based on the designed cascode DA, with 130 nm partially depleted SOI technology using microstrip lines, where the frequency of the DO is controlled by the time delay of its transmission lines. This work has been conducted in strong collaboration with Dr. C. Pavageau from IEMN, France. IEMN was in charge of modeling of the MOSFET transistors and the passives used in the design. The design methodology was developed in EMIC. the designs were done in IEMN for the body-contacted ones, and in EMIC for the floating-body. The results related to the work carried out in IEMN is cited in Dr. Pavageau’s thesis [7]. Acknowledgment

This work is funded by the “Région Wallonne”, Belgium

through the project “4G-Radio”. The research has been done in strong collaboration with the “Institut d’Electronique, de Microélectronique et de Nanotechnologie”, and “Commissariat a ` l’Energie Atomique”, France. The chips were manufactured by STMicroelectronics, Crolles, France.

xxvi

References [1] J. Yue and J. Kriz, “SOI CMOS Technology for RF system-on-chip applications,” http://www.mysoiservices.com/appnotes/SOITechNote.pdf, October 2001. [2] “www.bccresearch.com,” . [3] http://www.itrs.net/Links/2005ITRS/Wireless2005.pdf, “Radio frequency and analog/mixed-signal technologies for wireless communications,” 2005. [4] A. Hajimiri, “Distributed Integrated Circuits: Wideband Communications for the 21st Century,” http://www.eas.caltech.edu/engenious/win03/hajimiri.pdf, 2003. [5] H. Shigematsu, M. Sato, T. Hirose, and Y Watanabe, “A distributed amplifier for 40 gbps fiber-optic communications systems,” Microwave Journal, vol. 45, no. 4, pp. 78 – 90, April 2002. [6] T. T. Y. Wong, Fundamentals of Distributed Amplification, Artech House, 1993. [7] C .Pavageau, Utilisation des technologies MOS avances pour des applications en gamme millimtriques, Ph.D. thesis, IEMN - Lille - FRANCE, Decemeber 2005.

xxvii

CHAPTER 1 BULK CMOS VS. SOI 1.1

Introduction

The last decade has witnessed the relentless increase in digital and analog integration of Si VLSI technology, with Silicon-on-insulator (SOI) CMOS as the candidate of choice for high performance digital applications. Opportunities for the nanometer SOI CMOS technology are the high gain and cut-off frequency, as well as the low RF noise and the low voltage and power consumption. SOI technology has long been used in many special applications, such as radiation-hardened or high-voltage integrated circuits. It is only in recent years that SOI has emerged as a serious contender for lowpower high-performance applications. The primary reason is the power consumption of scaled bulk complementary metal-oxide-semiconductor (CMOS) technology [1]. The optimum technology choice for an RF application is complicated by issues of performance, wafer cost, level of integration, and time-to market. Submicron CMOS technology appears to be a feasible and cost-effective integration solution for mobile communication systems. Effectively, the maturity of silicon-based CMOS technology for small device feature size and low voltage digital circuits and also the recent progresses of MOSFETs microwave performances explain the silicon success compared to III-V technologies.

1.2

SOI: Silicon On Insulator

Silicon on insulator (SOI) is a layered structure consisting of a thin layer of silicon, from 50 nm to 100 µm, which is created on an insulating substrate, which is usually sapphire or silicon with an insulating layer of 80 nm silicon dioxide thick on its surface. SOI chips cost more to produce and are generally used for high-end applications. A popular SOI technology is Silicon-on-Sapphire (SOS), used in special rad-hard applications in military and aerospace. SOI differs from generic CMOS in that its silicon junction is above an electrical insulator. The advantage is that this insulator reduces the capacitance, meaning the transistor has less to charge-up before completing a switch, which results in reduced switching time. SOI devices are usually inherently latchup resistant. Also, there is a reduction in transistor leakage current thereby making this fabrication technology an attractive choice for low power circuit design. 1

CHAPTER 1.

BULK CMOS VS. SOI

Metal 5 Metal 4 Metal 3 Metal 2

Transistors Figure 1.1: Five layer metal CMOS SOI device [2].

It is only in recent years that SOI has emerged as a serious contender for low-power high-performance applications. The primary reason is the power consumption of scaled bulk complementary metal-oxide-semiconductor (CMOS) technology. Due to the dielectric isolation of the circuit elements, SOI technology significantly reduces junction capacitances and allows the circuits to operate at high speed or substantially lower power at the same speed. The device structure also eliminates latchup in bulk CMOS, improves the short channel effect and soft error immunity [1].

SOI substrates can be fabricated by either oxygen implant/anneal (SIMOX) or bond/etch back (BESOI) techniques. Both methods have gained acceptance in the marketplace. Anticipated wafer volumes are in the range of 500.000 per year ramping to 10 million per year by 2005. This milestone signifies the general acceptance of CMOS SOI as the next generation technology choice because large volume production is the best way to ensure continuous price reductions and quality improvement. Honeywell, IBM, AMD, Motorola, Samsung and many other companies are actively working to further develop and implement this technology, thereby giving CMOS SOI a significant advantage over other insulated materials, such as SOS (Silicon-onSapphire) [2].

Figure 1.1 shows a rendered cross-section of a multi-layer metal CMOS SOI device. Complete oxide isolation can be easily accomplished by shallow trenching the top silicon layer, which is in the range of 50 nm to 200 nm [2]. Buried oxide layers offer the advantage of integrating a high resistivity substrate to reduce substrate related RF losses.

2

1.3

SOI ADVANTAGES

The submicron CMOS technologies appears to be the best for a feasible and cost-effective integration of the mobile communication systems. Silicon offers many advantages as a microwave material [3]: • Silicon is a mature technology. • It is a good thermal conductor. • Multi interconnect metal layers are easily achieved. • An ample set of analog and digital devices can be realized. Bulk MOSFET’s are made in silicon wafers having a thickness of approximately 500 µm, but only the first micrometer at the top of the wafer is used for transistor fabrication. Most parasitical effects in bulk MOS devices find theirs origin in the interactions between the devices and the substrate. The full dielectric isolation of the device in SOI technology prevents the occurrence of most of the parasitic effects. The basic differences between bulk and SOI transistors are the following: • Bulk MOSFETs are built atop the surface of a monocristalline silicon wafer (Figure 1.2.a).

• In SOI, the top active silicon region is separated from the under-laying mechanical substrate by a thick insulator layer (Figure 1.2.b).

Figure 1.2: Cross section of a bulk (a) and a SOI (b) MOSFET.

1.3

SOI advantages

In the following some general differences between SOI and bulk MOSFETs are presented [3, 4]: 3

CHAPTER 1.

BULK CMOS VS. SOI

• Reduction of substrate parasitic capacitances:

Capacitances are a key factor for the high frequency performances of devices. Any reduction of the total capacitance of a MOSFET will increase the cut-off frequency of the transistor, allowing using circuits at higher frequency. In bulk devices, the parasitic source and drain to substrate capacitances increase with the doping level, becoming larger for modern devices where the doping level is higher than in previous technologies. In SOI, the maximum capacitance between junctions and the substrate is the capacitance of the buried oxide. This capacitance is fixed by the thickness of the buried oxide. Thanks to the lower value of its permittivity, compared to silicon, these capacitances are smaller than what we can expect for bulk MOSFET .

• Small devices without latchup:

A parasitic effect of CMOS technologies is called latchup. This effect consists in the triggering of an unwanted PNPN thyristor which is present in the bulk structure. In SOI, there is no path for any current between devices, there cannot be any latchup.

• Reduction of short channel effects (SCE):

The reduction of the SCE is necessary to increase the operating frequency of circuits. This effect is related to the loss of control of the channel by the gate. In the case of SOI MOSFET, and more precisely Fully Depleted (FD) SOI MOSFET, the space charge in the thin film of silicon is well controlled by the gate. As a consequence, the SCE are reduced when compared to classical bulk MOSFET.

• Better inverse subthreshold slope:

The inverse subthreshold slope is defined as the inverse of the slope of the Id vs Vd characteristic curve in the subthreshold regime. It has been proved and demonstrated [1] that the Fully Depleted SOI MOSFET has a lower inverse subthreshold slope than a bulk MOSFET, allowing better performances, in particular at low power supply.

• Substrate Cross Talk Reduction:

To integrate an RF system-on chip, it is important to have proper device isolation in the gigahertz frequency range. SOI technology provides the adequate device isolation because the complete oxide isolation between devices essentially cuts off all direct paths of substrate injection noise and a near intrinsic substrate further reduces the capacitive coupling through the substrate. Complete oxide isolation is impossible to form with bulk CMOS or bipolar technology. To overcome this problem, multiple substrate contacts with large guard band and/or deep trench

4

1.4

SOI DISADVANTAGES

isolation to reduce the substrate injection current can be used. Either approach suffers a negative impact on density (large guard band) or on fabrication cost (complex processing of deep trench isolation structures). As pointed out earlier, the buried oxide layer offers a complete isolation between the active device region and the bulk substrate. This provides an additional degree of freedom in selecting the high resistivity substrate. Using a near intrinsic substrate to reduce the capacitive coupling is impossible for bulk technology due to latchup concerns.

1.4

SOI disadvantages

In SOI MOS transistors, the active region of the device is surrounded from three sides by insulating layers: (1) the gate insulator, (2) the protecting insulating layer at the sidewall of the silicon island, and (3) underlying buried insulating layer. Thus, it is natural to expect that some problems are associated with full dielectric isolation of SOI devices [5] [1]. • Self-heating effects:

SOI transistors are thermally insulated from the substrate by the buried insulator. As a result, removal of access heat generated by the Joule effect within the device, is less efficient than in bulk, which yields to substantial elevation of device temperature. It has recently been proposed to replace the standard silicon dioxide with buried alumina or other dielectric, able to offer excellent thermal conductivity [6].

• Reduced drain breakdown voltage:

One major concern with SOI devices is their low drain breakdown voltage, caused by the presence of a parasitic lateral bipolar structure with floating base in the SOI MOSFET. Possible solutions include the use of lightly doped sources and drains (LDS and LDD), growth of silicides on source and drain, and the use of body contacts.

1.5

Conclusion

Until recently, GaAs technology was expected to dominate the RF integrated circuit arena because of its intrinsically higher speed due to its improved electron mobility and saturated drift velocity. Table 1.1 summarizes the relative differences in the intrinsic materials properties of silicon and GaAs, with particular attention to key differences for radio-frequency applications. Based on the material properties alone 5

CHAPTER 1.

BULK CMOS VS. SOI

(low-field electron mobility and energy band-gap in particular), GaAs is clearly superior for high-frequency device applications.

Propreties

Silicon

GaAs

≈ 3 × 105

≈ 4 × 105

Electron Mobility (cm2 /V − sec)

≈ 1500

≈ 8500

Thermal conductivity at 300o K(watt/cm −o C)

≈ 1.45

≈ 0.45

Saturated Electron Drift Velocity (at 105 V /cm)

≈ 107

≈ 107

10 − 103 103 − 105

104 − 106 106 − 108

Breakdown Field (V /cm)

1/f Noise Corner Frequency (Hz) BJT/HBT MOSFET/MESFET Substrate Resistivity (typical) (Ω − cm)

Low resistivity Si 10 − 50 High resistivity Si ≈ 103

≈ 108

Table 1.1: Comparison of fundamental material proprieties of Si and GaAs semiconductor technology [7]. The structure of a typical GaAs MESFET and silicon MOSFET are compared in Fig. 1.3. The main differences between the devices are in the channel formation and the coupling of the gate-control electrode to the channel. The GaAs MESFET uses a thin doped channel whose thickness is controlled through depletion by metal/semiconductor junction, the metal gate directly contacts the channel. The MOSFET, on the other hand, forms a channel when the silicon surface is inverted (p-type silicon now contains a high density of electrons due to band-bending). The gate electrode is separated from the channel by a thin oxide dielectric layer [8]. The main advantage of GaAs over Si is ,as already said, the electron velocity. The high electron velocity at low field of GaAs is what is desired for high speed FETs or bipolars that also need to operate with small operating voltages to conserve power.

6

1.5

CONCLUSION

Contact Source

Metal gate Gate

Drain

n – GaAs n+ – GaAs Semi-insulating GaAs (a)

Polysilicon gate Contact

Gate oxide

n – Silicon

p – Silicon (b) Figure 1.3: Cross section of (a) MESFET and (b) MOSFET.

7

CHAPTER 1.

BULK CMOS VS. SOI

However, the transistor unity current-gain frequency ft of silicon technology has recently reached the level where it is comparable with GaAs [9]. Also, the higher levels of integration possible with silicon technology may reduce the need for routing high-frequency signals on- and off-chip, compared with GaAs technology, reducing overall system power dissipation. Parasitic coupling between adjacent sections of a high frequency RF integrated circuit is a problem especially in monolithic silicon technology, because of the relatively low substrate resistivity. By comparison, GaAs technology exhibits a greater degree of circuit to circuit isolation at high frequencies, due to the semi-insulating nature of the substrate [10, 11, 3]. SOI technology offers many advantages for tomorrows performance driven products. Fine-tuning the semiconductors parameters allows chips that work in extreme environments, including extremely low power consumption and very low noise. When compared with bulk CMOS technology, reductions in cross talk, simplified manufacturing processes, integrated design capabilities, increased performance, decreases in power consumption and higher yields are all attributes of CMOS SOI technology. These attributes can provide revenue and performance advantages in many RF applications [2]. Low power consumption is particularly important in mobile communications due to limited battery life. One approach to meet this challenge is to create a reduced power RF system-on-chip that contains digital, analog and RF portions of the design on the same die. SOI CMOS meets these requirements due to its reduced parasitic capacitance.

8

References [1] J.-P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI, Kluwer Academic Publishers, 2 edition, 1997. [2] J. Yue and J. Kriz, “SOI CMOS Technology for RF system-on-chip applications,” http://www.mysoiservices.com/appnotes/SOITechNote.pdf, October 2001. [3] J. P. Raskin, Modeling, Characterization and Optimization of MOSFET’s and Passive Elements for the synthesis of SOI MMIC’s, Ph.D. thesis, UCL, December 1997. [4] M. Dehan, Characterization and Modeling of SOI RF integrated components, Ph.D. thesis, UCL, November 2003. [5] J. P. Colinge, V. S. Lysenko, and A. N. Nazarov, Physical and Technical Problmes of SOI Stuctures and Devices, vol. 4 of 3 : high Technology, Kluwer Academic Publishers, 1995. [6] K. Oshima, S. Cristoloveanu, B. Guillaumot, H. Iwai, and S. Deleonibus, “Advanced SOI MOSFETs with buried alumina and ground plane: self-heating and short-channel effects ,” Solid-State Electronics, vol. 48, no. 6, pp. 907–917, June 2004. [7] http://www.siliconfareast.com/sigegaas.htm, “Properties of si, ge, and gaas at 300k,” . [8] S. I. Long and S. E. Burtner, Gallium Arsenide Digital Integrated Circuit Design, Mc Graw Hill, 1990. [9] J. O. Plouchart, N. Zamdamer, J. Kim, M. Sherony, Y. Tan, A. Ray, M. Talbi, L.F. Wagner, K. Wu, S. Narasimha, P. O’Neil, N. Phan, M. Rohan, J. Storm, D. M. Friend, S. V. Kosonocky, D. R. Knebel, S. kim, K. A. Jenkins, and M. M. Rivier, “Application of an SOI 0.12 um CMOS technology to SoCs with lowpower and high-frequency circuits,” IBM J. RES. DEV., vol. 47, no. 5/6, pp. 611 – 629, september/november 2003. [10] K. Joardar, “A simple approach to modeling cross-talk in integrated circuits,” IEEE Journal of Solid-State Circuits, vol. 29, no. 10, pp. 1212 – 1219, October 1995. [11] L. E. Larson, “Integrated Circuit Technology Options for RFIC’s - Present Status and Future Directions ,” IEEE Journal of Solid State Circuits, vol. 33, no. 3, pp. 387 – 399, March 1998.

CHAPTER 1.

10

BULK CMOS VS. SOI

CHAPTER 2 CONCEPT OF DISTRIBUTED AMPLIFIERS 2.1

Introduction

As far as new circuit design techniques are concerned, the 1980s must surely represent the heyday for the MMIC (Monolithic Microwave Integrated Circuits) designer. In the 1990s there has been very rapid development of new devices, and an increasing emphasis on the civil applications of MMIC technology in communications. Advancement in the field of electronics can often be observed from the improvement in performance of active circuits and systems. The amplifier, because it is a highly versatile functional circuit, has always been one of the first to benefit from new developments in device technology. Of the many characteristics of an amplifier, perhaps the most notable are the gain and the frequency response. The most popular and well-established circuit techniques employed in the design of broadband amplifiers that are realized in hybrid and monolithic technologies are [1][2][3]:

• Reactively matched circuits:

The reactively matched amplifier (Fig. 2.1) uses lossless matching networks, with either lumped or distributed elements. Since the matching networks are lossless the reactively matched amplifier can be designed for optimum gain, noise figure, and output power. The disadvantage of this type of amplifier is its relatively poor impedance match, because although the lossless matching circuits provides the desired match over a narrow band of frequencies, the matching at other frequencies is degraded. More suitable techniques for broadband matching in MMIC circuits are lossy matching, negative feedback, and the distributed amplifier.

RF input

Output matching network

Input matching network

RF output

Figure 2.1: Reactively matched amplifier.

11

CHAPTER 2. CONCEPT OF DISTRIBUTED AMPLIFIERS

• Lossy matched circuits:

The lossy match amplifier uses resistors within its matching network to enable flat gain to be achieved over a broad bandwidth (Fig. 2.2). This is achieved by introducing high attenuation at low frequencies and low attenuation at high frequencies, while maintaining a good input and output match over the desired bandwidth. The disadvantages of this approach, compared to the previous one, are that it has a lower gain, lower output power, and higher noise figure.

RF output

RF input R2 R1

Figure 2.2: Lossy matched amplifier.

• Feedback circuits:

The feedback amplifier is a technique that gives very flat gain with good input and output matches (Fig. 2.3). The main disadvantage is the erosion of its output power and noise figure over the lower end of the frequency band due to losses associated with the feedback resistor. Lfb

Rfb

RF output

RF input

Figure 2.3: Feedback amplifier.

• Traveling wave distributed circuits:

The traveling wave amplifier has been well established, hence it is immensely

popular in the design of amplifiers operating across multioctave bandwidths. 12

2.2

CONCEPT OF DISTRIBUTED AMPLIFICATION

The concept of traveling wave or distributed amplification has been around for over half a century. The term “distributed amplifier” originated in a paper by Ginzton et al. in 1948 [4]; however, the underlying concepts can be traced back to a patent by Percival in 1937 [5]. Distributed amplifiers employ a topology in which the gain stages are connected such that their capacitances are separated, yet the output currents still combine in an additive fashion. Series-inductive elements are used to separate capacitances at the input and output of adjacent gain stages. The resulting topology, given by the interlying series inductors and shunt capacitances, forms what is essentially a lumped-parameter artificial transmission line. The additive nature of the gain dictates a relatively low gain; however, the distributed nature of the capacitance allows the amplifier to achieve very wide bandwidths (Fig. 2.4).

Ld

Ld/2 Termination

Ld

Ld

Ld/2

Drain line

Z0 Vout

Vin

Lg/2

Lg

Gate line

Lg/2

Lg

Termination

Z0

Figure 2.4: Distributed amplifier.

2.2

Concept of distributed amplification

With the product of the gain and the bandwidth of an amplifier stage limited by parameters intrinsic to the active device employed, expanding the bandwidth will give rise to a reduction in the gain. As the gain is made close to unity, it becomes inefficient to cascade amplifier stages. On the other hand, combining the outputs from a number of active devices in parallel will increase the output power but will produce no improvement in the gain bandwidth product. The solution is to find an arrangement in such a way that the output currents from a number of devices are superimposed constructively while effects of the shunt capacitances are not accumulated: this is the base of distributed amplification [6]. 13


This method absorbs the FET’s input/output capacitance as part of the lumped elements of an ”artificial transmission line”, formed with the series inductance that connects adjacent drains and gates. A schematic of a distributed amplifier (DA) [7, 8] is shown in Fig. 2.4. Power is coupled from the ”gate line” to the ”drain line” through transistors. The transmission lines can be of either the artificial type, i.e. made up of lumpedelements inductors, or the real type, i.e. consisting of sections of transmissions lines (microstrip or coplanar). The DA concept has been successfully applied to monolithic GaAs MESFET amplifiers at microwave frequencies in the 80’s for larger gain - bandwidth products. Ayasli et al., have published design formulas for the gain of Traveling Wave Amplifier based on an approach that approximates gate and drain lines as continuous structures [8]. Similarly, Beyer et al. developed a closed form expression for the gain that depends on the circuits propagation constants and the gate circuit cut-off frequency [7]. Niclas et al. has also developed a method based on the use of the admittance matrix employing the Y parameters of the transistor model in an amplifier with either artificial or real transmission lines. This method allows the use of much more sophisticated model for the transistor developed from its measured S parameters [9]. McKay et al. [10] proposed also a formulation based on a normalized transmission using matrix formulation. This technique yields insight into amplifier operation because it displays the traveling-wave nature of the distributed amplifier.

2.2.1

Advantages of DAs

The advantages of DAs include [11]: 1. Providing a good input match, so gain modules can readily be cascaded. 2. Providing a good isolation from output to input resulting in a stable amplifier configuration with no oscillatory tendency. 3. Providing more options for the design of the input and the output matching networks than the single-stage amplifier. 4. Providing a higher power level than single stage amplifiers, as the current generated by each active device is vectorially combined at the output drain line. 5. Being versatile, as its configuration allows the implementation of other functions, such as the power combiner, power splitter, circulator, multiplier, mixer, impedance transformer, and oscillator. 14

2.3

OTHER APPLICATIONS OF DAS

6. A reduction of its noise figure by choosing the optimal number of active devices [12, 9].

2.2.2

Disadvantages of DAs

The DAs present various disadvantages [11]: 1. Phase velocity equalization is necessary because the total output current is dependent on the phase coherence of the individual current generators. 2. As the input signal propagates down the gate line, each active device receives a reduced amount of the input voltage with respect to the previous one due to the gate line losses. 3. The amplifier’s gain is limited by the gate en drain line attenuations, which will eventually exceed the added gain obtained by increasing the number of active devices.

2.3

Other applications of DAs

The versatility of the DAs configurations makes this type of amplifiers useful for performing several other circuit functions.

2.3.1

Power Combiner and Splitter

Levy et al. [13] proposed and practically demonstrated an active power combiner using a DA concept. The circuit was made of two gate lines and a common drain line actively coupled by FETs, as illustrated in Fig. 2.5.a. It is similarly possible to create a distributed power splitter , which consists of two independent DAs that have a common input (Fig. 2.5.b). Th active combiner and splitter provide an attractive alternative to the conventional Wilkinson or other planar power dividers in terms of gain, isolation, and size.

2.3.2

Circulator

Leisten et al. [14] first showed the feasibility of using a DA in duplexer/circulator. In a well-designed DA, the reverse gain is much less than unity over almost all of the bandwidth, and the DA can be considered as a four-port active directional coupler property with the usual directional coupler property of fourth-port isolation. Thus, this device can be used as an active circulator, as illustrated in Fig. 2.6.

15


Gate line Termination

RF input Drain line Termination

RF input

RF output

Gate line

Termination

(a) Drain line Termination

RF output Gate line Termination

RF input

Termination

Drain line

RF output

(b) Figure 2.5: Basic scheme of active combiner and splitter circuits.

The operation of the active circulator is quite simple : as signal power is fed into port 1 emerges from port 3 after forward amplification and isolation is provided between port 1 and port 2. Power fed into port 3 is fed directly to port 2.

2.3.3

Active Frequency Multiplier

Pavio et al. [15], have demonstrated the concept of a frequency multiplier using a DA. The multiplier, illustrated in Fig. 2.7 is realized with one pair of FETs connected in a common gate configuration while the other pair is connected in a common source configuration. The common input transmission line of impedance Zo is connected to source and gate of each pair of devices. The two output drain lines of impedance 2Zo are summed at a common node to cancel the fundamental signal and maximize the second harmonic. 16

2.3

Port 2


Drain line

Port 3 RF output Reverse gain ≠ 0

Reverse gain ≈ 0

Port 1 RF input

Gate line

Termination

Figure 2.6: Basic scheme of an active circulator.

Drain line Termination

Termination

RF input

Termination

RF output

Gate line

Figure 2.7: Basic scheme of an active frequency multiplier.

2.3.4

Mixer

The principle of using a DA as a distributed mixer was first suggested by Tang [16]. As illustrated in Fig. 2.8, the technique used is to employ an active distributed signal combiner at the input of a single-gate FET mixer. The active combiner consists of two DAs sharing a common drain line. In this configuration, the RF and LO current generators pass independent currents into the drain line, and in small-signal conditions the signals add by superposition.

2.3.5

Active Impedance Transformer

Cioffi [17] showed that the DA can be used as an impedance transformer. As shown on Fig. 2.9, to achieve impedance reduction from 50 Ω downwards can be obtained by using one 50 Ω gate line that feeds n 50 Ω drain lines via the FETs. Conversely, to transform from n 50 Ω to 50 Ω, the n 50 Ω gate lines in parallel feed the one 50 Ω drain line via the FETs. 17


IF output

Gate line

RF input Drain line Termination

LO input

Termination

Gate line

Combiner

Mixer

Figure 2.8: Basic scheme of an active mixer.

2.3.6

Multidecade Oscillator

Skvor et al. [18], first proposed a way to modify the DA into a tunable oscillator. This was achieved by omitting the idle drain load and connecting the drain line directly to the amplifier’s input, as illustrated in Fig. 5.12. This approach makes use of the DA’s reverse gain to form an oscillation loop.

2.3.7

Power-Distributed amplifier

A power-DA is simply a DA in which Power FETs are used instead of the small-signal FET devices [19]. The power DA also needs to have high power-added efficiency, given by the following equation: η=

(1 − 1/G)Pout Pin

(2.1)

where Pout is output power dissipated in the load, Pin is the amplifier’s DC power consumption, and G is th amplifier’s gain. From its equation, it is clear that a low-gain amplifier will have reduced power-added efficiency.

18

2.3


Drain line RF output

Termination

Z=Zo Termination RF input Z=Zo/n

n Gate-line

Termination

(a)

n Drain-line RF output Termination Z=Zo/n Termination

Termination

Gate line

RF input Z=Zo

(b)

Figure 2.9: Basic scheme of an active impedance transformer.

Drain line RF output

Feedback path of 180°at fo

Gate line

Termination

Figure 2.10: Basic scheme of a distributed oscillator.

19


2.4

Circuit principle

The Operation of the DA is easy to explain if we look at Fig.2.11: a RF signal applied to the input port of the gate line travels down the line to the termination where it is absorbed. The traveling signal is picked up by the gates of the individual transistor and transferred to the drain line via their transconductances. If the phase velocities on the gate and the drain lines are identical, the signals on the drain line add in the forward direction. Any signal which travels backward and is not entirely canceled by the out of phase additions will be absorbed by the drain line termination.

Vdrain

(3)

Drain Line

(4)

Zd

Output

Zg

Input

(1)

Gate Line

Vgate

(2)

Figure 2.11: The distributed amplification.

The concept of distributed amplification is based on combining the input and output capacitances of the actives devices with inductors in such a way that two artificial transmission lines are obtained. The input and output capacitance of each device become the capacitance per unit section for these lines (Fig.2.12) and the lines are coupled by the transconductance of the active device. As a result, it is possible to obtain amplification over a much wider bandwidth than with conventional amplifiers [20]. Designers have concentrated mainly on increasing the gain-bandwidth product and the gain flatness, as well as on output power capabilities.

In DA, the transmission structures employed are often analyzed as a cascade of two ports, as we will see in the following section.

20

Lg/2

2.4

CIRCUIT PRINCIPLE

Lg/2

Ld/2

Ld/2

Cgs Rds

Cds

Rgs

(b)

(a)

Figure 2.12: Lossless elementary section of the:(a) gate line (b) drain line.

2.4.1

Image Parameter Method

The image parameter method may be applied to the distributed amplifier since it consists of a cascade of identical two-port networks forming an artificial transmission line. The analysis can be conveniently accomplished using the ABCD parameters, because the overall ABCD matrix is the product of those of the cascaded two-ports (Fig. 2.13).

I1

V1

I2

Q

V2

Figure 2.13: Two port network.

When considering signal transmission and impedance matching in cascaded twoports, each two-port should operate with the appropriate impedance terminations so that the maximum power transfer takes place over the prescribed bandwidth. Such condition can be met by terminating the two-port with a pair of impedances known as image impedances so that the impedance appears the same when one looks into either direction of each port as shown in Fig.2.14. We can express those impedances as Zi1 and Zi2 . 21


The image impedances may also be expressed as: r

q

Zsc1 Zoc1 =

Zi1 =

r

q

Zi2 =

Zsc2 Zoc2 =

Q

B D B C

r

r

A C

(2.2)

D A

(2.3)

Z i2

Z i1 (a)

Z i1

Q Z i2 (b)

Figure 2.14: A two-port network terminated by its image impedance. where Zsc1 and Zoc1 are the impedances appearing at port 1, with port 2 short circuited and open circuited, respectively, and likewise for Zi2 . If the network is symmetrical, Zi1 and Zi2 become identical, known as characteristic impedance and is denoted Z0 . Fig. 2.15 shows the case of an infinite number of identical networks connected so that at each junction either “end 1s” are connected together or “end 2s” are connected together. Because of the way the infinite chain of networks in Fig.2.15 is connected, the impedances seen looking left and right at each junction are always equal, hence there is never any reflection of a wave passing through a junction. Thus, from the wave point of view, the networks of the figure are perfectly matched [21]. The image impedance Zi for a reciprocal symmetric two-port is defined as the impedance looking into port 1 or 2 of the two-port when the other terminal is also terminated in Zi [21]. To achieve an impedance match over a broad range, the load and source impedance must be transformed into the image impedance. Otherwise, the gain response will 22

2.4

Zi1

I1

CIRCUIT PRINCIPLE

I2 1 Q1 2

Vin

Zi1

IN 2

Q2 1

Zi1

Zi2

Zi2

1 QN 2

Zi2

Figure 2.15: Artificial transmission line. not be flat as a function of frequency. The bisected-π m-derived section shown in Fig.2.16, serves this purpose well [21, 22]. The impedance looking into the gate and drain line when transformed by the m-derived section is approximately constant over a broad range of frequencies. The m-derived impedance matching network provides a big improvement of the variations over the broadband frequency. It can also be used to match directly to Zo = 50 Ω. Constant-k and m-derived filters are classic examples of filters designed from the image point of view [21, 6].

m L/2

1− m2 L 2m

m c 2 Zi

Z0

Figure 2.16: Bisected-π m-derived matching network.

2.4.2

Comparison between cascaded and distributed amplifiers

Most amplifiers are cascaded (i.e. connected to second amplifier). The two techniques commonly used are shown in Fig.2.17:

• When we consider cascaded amplifiers (CA), the overall gain function is given by 23


Vin

Amplifier

Interstage network

Amplifier

Interstage network

Vout

(a) R0

Output line

Amplifier

Amplifier

RL

Input line

R0

Transmission line section of characteristic impedance R0

(b) Figure 2.17: Multiamplifier structure: (a) cascade; (b) distributed.

the product of the gain functions of the individual stages. Thus, in CA, if the gain per stage is greater than unity, we obtain product amplification. Basically, a cascade connection is a series connection with the output of one stage applied as input to the second stage and so on. Fig.2.18 shows a cascade connection of two FET amplifier stages. The gain of the overall cascade amplifier is the product of stage gains Av1 and Av2 :

Av = Av1 Av2 = (−gm1 RD1 )(−gm2 RD2 )

(2.4)

where RD1 and RD2 are the output impedances of the two FETs.

Assuming n identical stages, the overall gain is given by: Av = An vi 24

(2.5)

2.4

CIRCUIT PRINCIPLE

Vdd

RF output

V2

RF input

V1

RD1

RD2

Figure 2.18: Cascaded FET amplifier. and the cut off frequency is [23]: p

fcn = (

21/n − 1)fci

(2.6)

where fci is the cut-off frequency of the single stage.

• In a distributed amplifier (DA), the response is one-half the sum of the individual responses since each stage’s output is propagated in both direction.

The voltage gain and the cut-off frequency are given by the following equations [24]:

1 ngm R02 2 1 fc = πR0 Cgg

Av =

(2.7) (2.8)

where Cgg is the input capacitance of the transistor. In a cascaded configuration, the total gain of a conventional lumped amplifier is one if the gain of the individual transistors are close to one as the frequency increases. The total gain of a distributed amplifier is given by the sum of each stage, not their product. Therefore, the distributed amplifier is chosen for the wide band applications.

25


Fig.2.19 gives the frequency response of a 4 sections cascaded and distributed amplifier using ideal passives. As we can see, even if the cascaded structure gives a higher gain, it does not provide flatness anymore over the desired bandwidth. Indeed, the cut-off frequency is referred to as the −3 dB point. For some specific applications

where the flatness of the gain is an important parameter, we define a −1 dB cut-off frequency.

Gain (dB)

Cascaded amplifier

Distributed amplifier

Frequency (GHz) Figure 2.19: Cascaded (line) and distributed amplifier (dots) gain with four MOSFETs.

2.5

Theoretical analysis

Analysis of distributed amplifiers is facilitated by the assumption of lossless transmission networks which are realized from ladder networks based on constant k low-pass filters, and unilateral active devices. A simplified equivalent circuit of the transistor is shown in Fig.2.20. Rgs , Cgs , Rds , and Cds are the gate to source and drain to source resistance and capacitance, respectively, gm the transconductance.

2.5.1

Using two-port theory (Beyer model)

In this analysis [7], the device is considered unilateral i.e. Cgd (the gate to drain capacitance) is neglected. The equivalent gate and drain transmission lines are shown in Fig.2.21.a and Fig.2.21.b. The lines are assumed to be terminated by their image 26

2.5

THEORETICAL ANALYSIS

Figure 2.20: The simplified equivalent circuit of the transistor. impedances at both ends. With the unilateral device model employed, the two transmission lines are nonreciprocally coupled through the action of the transconductance. From Fig.2.21.b, the current delivered to the load is given by: "

n X 1 Vk e−(n−k)γd I0 = gm e−γd /2 2

#

(2.9)

k=1

where Vk is the voltage across Cgs of the kth transistor and γd = αd + jβd is the propagation factor of the drain line, αd and βd are the attenuation and phase shift per section on the drain line, n is the number of transistors in the amplifier. Vk can be expressed in terms of the voltage at the gate terminal of the kth FET as: −1

Vi e−(2k−1)γg /2−jtan (ω/ωg ) Vk = 2 1/2 2 1 + ωωg 1 − ωωc

(2.10)

where Vi is the voltage at the input terminal of the amplifier and γg = αg + jβg is the propagation factor of the gate line. αg and βg are the attenuation and phase shift per section on the gate line, ωg = 1/ (Rgs Cgs ) is the gate circuit cut-off pulsation, and ωc = 2πfc is the cut-off pulsation of the lines (fc =

1 ). πLg Cgs

For constant-k type

transmission lines, the phase velocity is a well-known function of the cut-off frequency fc of the line. By requiring gate and drain lines to have the same cutoff frequency, the phase velocities are constrained to be equal. Therefore, we have βg = βd = β. I0 can be expressed as:

I0 =

gm Vi sinh

2 1+

n 2

−1

(αd − αg ) e−n(αd −αg )/2 e−jnβ−j tan

ω ωg

2 1/2

1−

ω ωg

2

sinh

1 2

(ω/ωg )

(2.11)

(αd − αg )

27


Lg/2

Lg

Cgs

V1Cgs

Rgs

Rgs

Lg/2

Lg/2

Lg/2

V2

Cgs

Vn Termination

Vin

Rgs

(a) Ld/2

Ld

Ld/2

Ld/2

Ld/2

gmV2 gmV1

Rds Cds

gmVn

Rds Cds

ZLd

Vout

Rds Cds

Termination

Load

(b)

Figure 2.21: (a) Gate transmission line. (b) Drain transmission line.

The power delivered to the load and input power to the amplifier are given, respectively, by: 1 |I0 |2 ℜ [ZID ] 2

(2.12)

|Vi |2 ℜ [ZIG ] 2 |ZIG |2

(2.13)

P0 = and Pi =

where ZID and ZIG are the image impedances of the drain and gate lines. Therefore, the power gain of the amplifier is: 2 gm Z0g Z0d sinh2 [0.5n(αd − αg )] e−0.5n(αg +αd ) Gp = 2 2 4 1 + ωωg 1 − ωωg sinh2 12 (αd − αg )

where Z0g (= 28

p

Lg /Cg ) and Z0d (=

p

(2.14)

Ld /Cd ) are the characteristic resistances of the

2.5


gate and drain lines, respectively. The most commonly used definition of power transducer gain is the so-called transducer gain GT defined as: GT =

Pload Pavail

(2.15)

where Pload is the power delivered to the load by the amplifier, and Pavail is the power available from the source. The latter is the same as the power delivered to the amplifier input by the source under the condition that the amplifier input impedance is conjugately matched to the source impedance (see Annex A for different gain definitions).

2.5.2

Using the admittance matrix (Niclas model)

The elementary circuit of a lumped element distributed amplifier can be represented by a four-port as shown in [9]. Replacing the transistor by its two-port representation with the current source ik leads to the equivalent circuit shown in Fig.2.22. The matrix equation which relates the voltage and current in Fig.2.22 takes the following form: 2

VDk−1

3

2

VDk

6 6 IDk−1 6 6 4 VGk−1

7 6 7 6 −IDk 7 = Ak 6 7 6 5 4 VGk

IGk−1

−IGk

3 7 7 7 7 5

(2.16)

where Ak = A1k AF k A2k [A1k ] is the matrix of the input link and [A2k ] is that of the output link as shown in Fig.2.23, while [Af k ] constitutes the MOSFET admittance matrix. Cascading n elementary circuits and terminating the idle ports with RG and RD (the gate and drain loads respectively) yields the matrix equation: 2

VD0

6 −1 6 −RD VD0 6 6 VG0 4

IG0

3

2

7 6 7 6 7 = D6 7 6 5 4

VDn −IDn VGn

3 7 7 7 7 5

(2.17)

−1 −RG VGn

29


Output Drain Link

Input Drain Link

VD(K-1) ID (K-1)

VDK

IDK

(Y22+Y12)

-Y12

(Y11+Y12)

IG (K-1)

IGK Input Gate Link

VG(K-1)

VGKM

Output Gate Link

VDK

Figure 2.22: Equivalent four-port representation of the elementary circuit of a DA in its general form.

where D=

k=0 Y

Ak

n

The insertion gain is expressed as the ratio of the signal power delivered to the load by the circuit to the signal power delivered directly to that load. The insertion gain can be now determined after some algebraic steps as following:

Gain = 2Y0

C2 C

(2.18)

with

30

Y0

=

1/Z0

C1

=

−1 −1 D(3, 4) D(4, 3) + RG D(4, 4) + Y0 D(3, 3) + RD

C2

=

−1 −1 D(2, 3) + RG D(2, 4) + Y0 D(1, 3) + RD D(1, 4)

2.5

C


=

−1 C1 D(2, 1) + Y0−1 D(2, 2) + Y0 D(1, 1) + RD D(1, 2)

−

−1 C2 D(4, 1) + Y0−1 D(4, 2) + Y0 D(3, 1) + RD D(3, 2)

This equation represents the exact solution for the gain of a DA in its most general form. In the case of the distributed amplifier structure, where the load and the input impedance are the same (50 Ω); the insertion gain and the transducer gain define the same quantity (see Annex for different gain definitions).

2.5.3

Using the wave theory (McKay model)

The normalized transmission matrix approach was presented by McKay et al. [10]. This theory applies to a general class of distributed amplifier with discrete sampling points on the gate line which couple to discrete excitation points on the drain line. Si Moussa et al. [25] extends this concept by considering the bilateral case obtained by including the gate-drain capacitance Cgd of the transistor. As we will see in the next chapter, because SOI MOSFETs deeply suffer from Miller effect, we must take into account this gate-drain capacitance Cgd in order to have accurate modeling. Using the scattering formalism, the wave quantities as shown in Fig.2.23 are given by:

p Vb b± n = p n ± ibn Z0d Z 0d

(2.19)

q Va a± n = p n ± ian Z0g Z 0g

(2.20)

− + a′− n = an + an+1 −

− a+ n + an 2

(2.21)

where Van , ian , Vbn and ibn are the total voltages and currents at section n the ’a’ and ’b’ denote the waves on the gate and the drain line, respectively. Z0g and Z0d are the characteristic impedances of the gate and drain line, respectively. It is the last equation that allows to make the analysis of the bilateral case [25]. Since Van+1 = Van q Van a′− − Z0g ian+1 − ian n = p Z 0g

(2.22)

31


Drain line

b+n+1

b+n i bn

b-n Zod

Zod

Vbn

b

i bn+1

b-n+1 Zod

Vbn+1

Zod

Cgd a+n a-n G

Zog

Generator

i’ a

i an

a’-n

a+n+1

i an+1

a-n+1

Van+1 a

Van

Zog

Zog

Voltage sampler

Gate line

Figure 2.23: Elementary section of a bilateral distributed amplifier. The variables bn and an represent the scattering waves.

The transfer matrix [M ] defined as [M ] = [G−1/2 ][T ]N [G1/2 ] is given by :

Wout = G−1/2

h

TN

i

G1/2 Win

(2.23)

where + − − T Wi = [ a+ i b i ai b i ]

where

T

(2.24)

denotes the operator transpose, (in ) and (out ) are the input and the output

vector, respectively.

G1/2 = diag {exp (−θg /2) , exp (−θd /2) , exp (θg /2) , exp (θd /2)} = G−1/2

−1

(2.25)

Note that the propagation constants θg and θd of, respectively, the gate and the drain line, are complex. [T ] = [G] [H]

(2.26)

[G] = diag {exp (−θg ) , exp (−θd ) , exp (θg ) , exp (θd )}

(2.27)

where

32

2.5

2 6 6 [H] = 6 6 4


1 + jZ0g Cgd ω H + 21 jCgd ω

p

Z 0g Z 0d

− 21 jCgd ω

p

1 jCgd ω Z0g Z0d 2 1 jZ0d Cgd ω 2

p

Z 0g Z 0d

−H

1 jZ0g Cgd ω 2 p 1 − 2 jCgd ω Z0g Z0d

− 21 jCgd ω

1 − jZ0g Cgd ω

−H − 12 jCgd ω where

Z 0g Z 0d

1 − 12 jZ0d Cgd ω

− 12 jZ0g Cgd ω

−H − 12 jCgd ω

p

p

Z 0g Z 0d

q 1 H = − gm D(ω) Z0g Z0d 2

ω is the pulsation and D(ω) =

1 1 + jRgs Cgs ω

p

Z 0g Z 0d

− 12 jZ0d Cgd ω p

1 jCgd ω Z0g Z0d 2 1 + 12 jZ0d Cgd ω

3 7 7 7 7 5

(2.28)

(2.29)

(2.30)

Under the assumption of perfect matching at the input and output lines, the transmission coefficient S21 which relates the incident gate at the input to the incident drain signal at the output, has the following form: S21 =

b+ out ain

(2.31)

Where b+ out is the output wave of the last section on the drain line and ain is the input wave of the first section of the gate line.

• Design Tradeoffs The expression of the gain (equation(2.14)) is a function of the drain/gate transmission line parameters, assuming fixed FET parameters. But typically for highest frequency response performance the minimum allowed length is used. The width can be selected according to power handling capability. The physical layout of the device should minimize the input gate resistance. The parameters under direct control of the designer are thus the number of stages, n, and the gate and drain inductance; Lg and Ld . Hence for a given number of stages, there are only two parameters to vary. To achieve a good match to 50 Ω, one generally chooses Lg and Ld to set the gate and drain impedances as close to 50 as possible, limiting the range of values for these components tremendously. There seems to be only a single parameter n in the design of a distributed amplifier. In practice one can trade gain for bandwidth by increasing the gate and drain cut-off frequencies through adding a series capacitor to the gate of the input stages. The design tradeoff must be evaluated carefully, though, since a lower gain with more 33


bandwidth can also be achieved by simply reducing n. As discussed before, the attenuation factors in fact set the optimum number of stages for gain. Naively, the gain should increase as we add stages, as shown by the approximate expression of [7] where n2 dependence is shown. But eventually the attenuation on the gate line will drive the input voltage to negligibly small values and adding further stages will simply increase the length and hence attenuation on the drain line without contributing to the output current. The optimum number of stages may be calculated from evaluating the derivative of equation (2.14) with respect to n. α

nopt =

2.5.4

ln αdg

(2.32)

αd − αg

Gain degradation

The attenuation on gate and drain lines is the critical factor controlling the frequency response of the amplifier, as will be shown. The expressions for gate- and drain-line attenuations can be derived from the propagation function for the constant-k line. The origin of losses in a DA is mainly due to the gate and drain resistances in the MOSFET, but there is also a contribution of the passives used in the design by their substrate and metal losses.

2.5.4.1

Passives losses

The design of a DA involves also the design of lumped inductors [7]. A T model can be chosen for the transmission lines: two inductors, each of one half value, and a capacitor (Cgs and Cds : gate and drain transistor’s capacitance in this case). For a constant-k (Fig.2.24), the propagation exponent is given by [21, 26]: cosh(γ) = 1 +

Z1 2Z2

(2.33)

γ = α + jβ is the propagation function, α and β are the attenuation and phase shift per section of the line, Z1 and Z2 are the impedances in the series and shunt arms of a section constant-k line. The real part of Z2 represents the losses contribution of the transistor (gate and drain losses), and the real part of Z1 are the losses introduced by the passives (metallic and dielectric losses). Equation 2.33 can be expressed as:

cosh α cos β

34

=

ℜ 1+

Z1 2Z2

(2.34)

2.5


Z1/2

Z1/2

Z2

Figure 2.24: T section network.

sinh α sin β

=

ℑ 1+

Z1 2Z2

(2.35)

By eliminating β from the equations we obtain the following equation for α:

sinh2 α = tanh2 α ℜ 1 +

Z1 2Z2

2

+ ℑ 1+

Z1 2Z2

2

(2.36)

When α ≤ 0.4, we have sinh2 α ≈ tanh2 α ≈ α [7]. Under this condition, α can

be written as follows:

h

i

ℑ 1+

α≈ h 1− ℜ 1+

Z1 ) 2Z2 Z1 2Z2

(2.37)

i2 1/2

This equation is the general form of the attenuation per section of a constant-k line. When evaluated for the specific networks shown in Fig.2.25 we obtain the following closed form expressions for attenuation on gate and drain lines [7]:

αg

=

s

(ωc /ωg )

1− 1− αd where ωg =

1 , Rgs Cgs

ωd =

=

ωc ωg

2

(2.38) Xc2

(ωd /ωc ) √ 1 − Xc2

1 , Rgds Cds

ωc = √

(2.39) 2 Lg Cgs

= √

2 , Ld Cds

Xc =

ω ωc

The attenuation on gate and drain lines versus frequency are shown on Fig.2.26 and Fig.2.27 respectively, for the following values of resistances and capacitances corresponding to the 30 × 2 × 0.13 µm SOI FB transistor: Rgs = 8.5 Ω, Rds = 157 Ω,

Cgs = 5.32 10−14 F and Cds = 2.57 10−14 F (We assume that the inductances are 35


Lg/2

Lg/2

Ld/2

Ld/2

Cgs Rds

Cds

Rgs

(b)

(a)

Figure 2.25: Elementary section of the:(a) gate line (b) drain line. lossless).

−3

7

x 10

6

Gate losses (dB)

5

4

3

2

1

0 0

0.02

0.04

0.06

0.08 X

0.1

0.12

0.14

0.16

c

Figure 2.26: Attenuation on gate line versus normalized frequency It is evident from the figures that the gate line attenuation is more sensitive to frequency than the drain line. Further, unlike attenuation in the gate line, the drain line attenuation does not vanish at the low frequency limit. Therefore the frequency response of the amplifier can be expected to be predominantly controlled by the attenuation on the gate line and the DC gain by the attenuation on the drain line. The inductors Lg and Ld , shown in Fig.2.25 can be realized by short lengths of high 36

2.5


0.03

0.025

Drain losses (dB)

0.02

0.015

0.01

0.005

0 0

0.02

0.04

0.06

0.08 X

0.1

0.12

0.14

0.16

c

Figure 2.27: Attenuation on drain line versus normalized frequency impedance microstrip line (Fig.2.28). Preliminary design uses the simple definition for the characteristic impedance of a transmission line, combining the input and output capacitance Cgs and Cds with the inductance of the short length microstrip line to achieve the desired 50 Ω impedances. L

R

Zo

C

G

G

C

length: l

Figure 2.28: A short length of microstrip line and its equivalent circuit. If the transmission line is electrically short (i.e. βl 1 kΩ.cm) at the back under the buried oxide. This process

features 2 nm gate oxide, Cobalt silicide on junctions and polysilicon gates and lines, with 6 copper metal level layers and an additional top metal layer in Aluminium (Alucap) (Fig. 3.6).

50

3.2

DESIGN METHODOLOGY

Metal 7 (Al) (h=880 nm) Metal 6 (Cu) Dielectric (SiO 2 et Si3N4)

h=5,7 µm

(h=900 nm)

Metal 2 to 5 (Cu) (h=350 nm)

Metal 1 (Cu) (h=260 nm) STI + PMD (h=770 nm) BOX (h=400 nm) Silicon substrate

Figure 3.6: Cross section of a MOSFET transistor in STM SOI technology. Two types of transistors will be used in our design: the first one makes use of conventional Floating Body (FB) devices while the other one uses Body-Contacted (BC) SOI MOS devices [16]. The body-contact prevents the device from floatingbody effects (such as kink effect) by controlling the potential of the body through a direct contact to the transistor source region (Fig. 3.7). In order to achieve a high cut-off frequency, we used optimized multi-fingered transistors composed of 30 gate fingers connected in parallel and having a width of 2 µm each for both devices. Corresponding maximum oscillation frequency (fmax ) is 76 GHz and 125 GHz were measured for the BC and the FB transistors, respectively, as show in Fig. 3.8.

51

CHAPTER 3. DESIGN OF DISTRIBUTED AMPLIFIERS ON SOI TECHNOLOGY

Gate Drain

Source

Body Si Bulk

Substrate Figure 3.7: SEM photograph of a PD SOI MOSFET transistor in 130 nm technology.

160 MOSFET conventionnel Floating-Body

Ft,Fmax (GHz)

140 120

Ft Fmax

100 80 60 Body-Contacted 40 0

1

2

3

4

5

W finger (µm)

Figure 3.8: Cut-off frequencies of PD SOI MOSFET transistor in 130 nm technology.

52

3.3

3.3

DESIGN

Design

The state of the art in 2003 shows that the best DA in CMOS was designed by Liu et al. [1] (Table 3.1). His work was used as reference to choose the specifications for our design in SOI technology.

3.3.1

Step1: Specifications

• Gain : 7 dB. • Bandwidth : 0.5 − 20 GHz. • Number of sections : 4 (because the number of stages used in the state of the art is around 4. Simulation results using lossy passive and complete model for the transistors are given in Fig.3.9. It shows that adding more transistors does not enhance the gain). • Bias : use the voltage values which provide the maximum gm . The biasing will be provided via the RF probes which are used for the measurements.

Several simulations were run to confirm the choice of the number of stages. In these simulations, the number of stages for the DAs was varied from 3 to 8 (Fig.3.9).

Gain (dB)

The goal was to achieve a bandwidth as wide as possible.

10 8 6 4 2 0

N=05 N=06

0

N=04

10

N=03

20

30

Frequency (GHz) Figure 3.9: Influence of the number of stages on the gain of a distributed amplifier. We also note an increase of the ripple due to the intensification of the Miller effect, which is proportional to the number of the stages. This Miller effect accentuates the feedback signal which causes the ripple in the gain curve. From Fig. 3.9 and using equation (2.32), the optimum number of stages was calculated to be 4.

53


3.3.2

Step2: Topology

The topology chosen is the conventional distributed amplifier, i.e. the transistor is used in the common source configuration (CSDA: Common Source Distributed Amplifier). The number of sections is given in the specifications.

3.3.3

Step3: Choice of the active device

The FET chosen for the DA is a Floating Body Partially Depleted 0.13 µm SOI MOSFET transistor. As shown in Fig.3.8, a design with 30 fingers did not provide good results, i.e. a low gain and a lot of ripple. The number of fingers was chosen in order to get a higher gm (Number of fingers: 60, finger’s width: 2 µm). The simulated S parameters are obtained using a linear RF model developed at IEMN (Annex B). The large signal RF MOSFET model was recently developed for sub-250 nm channel MOSFET transistors [17]. It is based on DC and S-parameters measurements. The drain current is modeled with a nonlinear expression which is continuous and infinitely derivable, leading to the transconductance and output conductance to be continuous. The capacitances Cgs and Cgd are modeled with nonlinear expressions derived directly from gate charge expression, thus ensuring charge conservation. Model parameters are consistent with S-parameters measurements. Noise simulation was also performed with a linear MOSFET model also developed at IEMN [18].

Drain rail (Cu-1+V12+…+V56+Cu-6)

Source rail

Source

(Cu-1+V12+ …+ V34+Cu-4)

Cu-4 Via (V34) Cu-3 Via (V23) Cu-2 Via (V12) Cu-1

Drain Gate

Gate

Gate rail

Contact Active zone Buried oxide

(Poly+Cu-1+V12+…+V56+Cu-6)

Figure 3.10: MOSFET on 130 nm SOI CMOS Technology. After parameters optimization on ADS r , in order to determine the drain-source current which allows the highest transconductance, we obtain ids = 19.7 mA for gm = 81 mS. 54

3.3

DESIGN

Because the chip will be constructed using microstrip lines playing the role of inductors, such a substitution is accomplished by adjusting the values of the inductances used as passives in the design of the DA, by finding, first, the equivalent model of the computed inductances’ values, and then the equivalent microstrip transmission line length and width. Fig. 3.11 is a circuit that illustrates a DA design with transmission line components replaced with Π model approximation and transistors replaced with ideal equivalents.

Figure 3.11: DA section illustrated with transmission line components replaced with Π model. The microstrip losses are divided into two components, one modeling the metalization losses in series with the inductor and the substrate losses in shunt with the inductor (Fig. 3.11). From the resulting circuit, the interactions between reactive elements are clear. The amplifier’s topology is a four-section distributed amplifier structure using 50 Ω gate and drain lines. The inductance per section of the artificial transmission lines can be calculated:

s

Z0 =

Lg,d Cg,d

(3.15)

The inductors are realized by short lengths of high impedance Thin Film Microstrip Lines (TFMS).

55


The TFMS structure is composed of metal 1 and metal 2 layers stacked together to form the ground plane, a 2.9 µm-thick silicon dioxide dielectric layer as a spacer, with a 2 µm-wide conductor patterned on the metal 6 layer. Line losses at 20 GHz of around 0.6 dB/mm were measured [19]. The design of these lines was done in collaboration with IEMN. TFMS lines were modeled through full-wave EM simulations with HF SS r Ansoft

W Alucap Copper (M6) 0.9 µm

1.78 µm 2.9 µm

Mulilayered-dielectric (oxide/nitride) Copper (M1 + VIA1 + M2) STI (oxide) Buried Oxide Si Substrate Figure 3.12: TFMS on 130 nm SOI CMOS Technology. Software (at IEMN). The multilayered structure of the dielectric with numerous silicon dioxide and silicon nitride layers was simplified using Kraszewski formulation for the effective permittivity [20]. The correctness of TFMS line description using HF SS r was verified by comparison with the S-parameters measurements of lines with different characteristic impedances, ranging from 20 to 75 Ω. An excellent agreement between HF SS r simulation and measurement was obtained (Fig. 3.13). The TFMS line model obtained through HF SS r was implemented in ADS r using a four elements RLCG model [19].

56

3.3

DESIGN

Alpha (dB/mm)

2,5 2 1,5 1 HFSS

0,5 0 0

10

20

30

40

50

60

70

80

90

Frequency (GHz) Figure 3.13: Measured and HF SS r simulated attenuation for a 2 µm wide TFMS line. Impact of line losses As previously said, one of the main challenges in silicon process is not anymore high performance transistors but ultra low loss transmission lines for achieving higher frequency and noise performances.

The transmission lines implemented here for

our design are microstrip lines. the signal conductor is shielded from the substrate avoiding coupling effects and thus TFMS electrical characteristics are unrelated to substrate resistivity, allowing the use of standard resistivity SOI substrates (around 20 Ω.cm). The drawback of TFMS is that high characteristic impedance is achieved while reducing microstrip width and while increasing dielectric thickness. These lead to high metal losses when TFMS are implemented on thin dielectric film, which is often the case with digital CMOS process. The additional Alucap can be stacked with copper-6 layer giving 1.78 µm-thick. Conductor losses of 1 dB/mm and 0.75 dB/mm at 20 GHz for 50 Ω TFMS (W = 7 µm) with copper-6 layer only, and with copper-6 and Alucap layers, respectively, were measured (Fig. 3.14). In Fig.3.15 the impact of the TFMS losses on the gain of the CSDA is shown. The designed CSDA is compared to an ideal one where the microstrip line used as passives are lossless.

57


2 Losses (dB/mm)

TFM S copper-6 TFM S copper-6+ALU

1,5 1 0,5 0 0

10

20 Frequency (GHz)

30

40

Figure 3.14: Comparison of measured lines losses for a 50 Ω TFMS using or not Alucap.

15

S21 (dB)

Ideal TFMS CSDA 10

5 Real CSDA 0 0

10

20

30

Frequency (GHz) Figure 3.15: Impact of the line losses on the gain of the DA.

58

3.3

DESIGN

We note a degradation of the gain of about 5 dB comparing the ideal CSDA (i.e. with ideal TFMS) and the realized one. In our design, because the values of the inductors are low, the chip will be constructed using TFMS lines (Fig. 3.12) playing the role of inductors. Such a substitution is accomplished by using the tuning in ADS r to find the equivalent microstrip transmission line length and width.

3.3.4

Lg = 0.28 nH =⇒ L = 400 µm, W = 4.5 µm.

(3.16)

Ld = 0.23 nH =⇒ L = 600 µm, W = 9 µm.

(3.17)

Step4: Power and noise figure matching conditions

There are no specified power or noise requirements for this amplifier, but we can calculate the consumption as follows: Pdc =

n X

Ids Vds

(3.18)

i=1

Distributed Amplifier Noise Figure The noise figure of a DA is calculated in [21] assuming only Van der Ziel noise sources at the gate and the drain of an individual MOSFET and lossless gate and drain transmission lines. Furthermore, it can be shown that in the limit of large n there exists an optimal value of n resulting in a minimum noise figure. In this work, we are not focusing on the minimization the average noise factor in the frequency band of interest. For our simulations on ADS r , we have used the high frequency SOI MOSFET model, developed in IEMN by Prof. G. Dambrine [18]. As shown in Fig. 3.16, two uncorrelated noise sources are used: an input noise voltage source ein and an output noise current source iout . By adding these two-uncorrelated noise sources model, all the FET’s noise parameters ( N Fmin , Rn , |Γopt | and arg (Γopt ) ) can be deduced. This noise model described in Fig. 3.16 is a Pospieszalski based model applied to the extrinsic device [18].

3.3.5

Step5: Choice of a bias circuit

The gate and the drain line circuits are DC isolated from their terminations by blocking capacitors. To bias a DA, we use two DC supplies for the gate and drain lines. 59


!

Figure 3.16: Equivalent circuit of MOSFET including two uncorrelated noise sources. The voltage biasing is chosen in order to get the highest gm . Using the tuning, we obtain the following values for gate and drain voltages: Vgs = 0.6 V, Vds = 0.8 V . Due to the metallic losses of the TFMS lines, we have to provide a higher voltage in order to bias all the transistors (imposing the above Vgs and Vds at the pads, only the two first transistors are correctly biased !). The simulation shows that in order to get a sufficient biasing voltage (0.8 V ) for the last transistor, we should provide a drain DC voltage of 1.1 V , as shown in the following table:

Vds 1.1 V

Vds1 1.033 V

Vds2 933.8 mV

Vds3 868.3 mV

Vds4 835.7 mV

Table 3.3: DC bias voltage distribution along the drain line. To apply these voltages to the transistors without disturbing the RF performances, an inductance bias choke (RFC) is connected a shown in Fig. 3.17. In our case, the bias will be provided by RF probes with an external bias T.

3.3.6

Step6: Basic circuit simulation and optimization

The basic topology, shown in Fig. 3.18, is analyzed and optimized using ADS r . A trade-off is necessary between losses and size: minimum microstrip line width assures that the inductances per line length will be maximized. On the other hand, narrow lines prove to be very lossy, so it is necessary to think about the trade-off “loss-size”. 60

3.3

DESIGN

Figure 3.17: Basic distributed amplifier.

Access lines

Figure 3.18: Common source distributed amplifier. We use meander shape for the gate and drain line structures in order to minimize the layout’s area, the meander pattern is always the same, and so the basic gate and lines unit are repeated as many times as is the number of stages (Fig. 3.19).

61


3.4

Common source distributed amplifier

After an optimization step of the CSDA, the obtained design parameters are summarized in table 3.4. The final layout is given in Fig. 3.19 with an area of 500 µm x 1500 µm including RF pads.

Transistors Gate line Drain line

Type: Floating Body WT = 60 × 2 LG /WG (µm/µm) = 400/4.5 RG (Ω)/CG (pF ) = 30/20 LG /WG (µm/µm) = 600/9 RG (Ω)/CG (pF ) = 40/20

Table 3.4: CSDA design parameters on 130 nm SOI technology.

Drain line Output RF pad Cg Cd Input RF pad Gate line

Transistors

Figure 3.19: Chip microphotograph of the designed CSDA.

3.5

Measures and discussion

The scattering parameters were measured using an Anritsu 37369A network analyzer operating up to 40 GHz. A high frequency coplanar Probes have been used for signal measurement and for circuit biasing (gate and drain lines). At room temperature (25o C), the CSDA shows a measured |S21 | gain of 4.5 ± 2 dB

and an unity-gain bandwidth of 30 GHz (Fig. 3.20). The input and output reflection

coefficients have been measured up to 40 GHz with a return loss better than −6 dB

for |S11 | and −7 dB for |S22 |, up to 25 GHz. The measured |S12 | coefficient (not

shown) is lower than −15 dB over the whole bandwidth.

62

3.5

MEASURES AND DISCUSSION

S21, S11 (dB)

10 5 S21

0

S11

-5 -10 -15 0

10

20 Frequency (GHz)

30

40

30

40

NF, S22 (dB)

10 5 NF

0

S 22

-5 -10 -15 0

10

20 Frequency (GHz)

Figure 3.20: Simulated and measured data for (top) power gain and input reflection coefficient, (bottom) noise figure and output return loss for the CSDA at room temperature.

On-wafer noise measurements were carried out between 6 and 20 GHz on 50 Ω , with an HP 8971C test set extension and HP 8970B noise figure meter, at IEMN. The measured noise figure is of 4.6 dB at 6 GHz and 7.0 dB at 20 GHz. The optimized performances were found for 1.4 V supply voltage, which corresponds to a DC power consumption of 66 mW .

63


3.6

Cascode distributed amplifier

The required gain is not achieved (< 7 dB). This is mainly due to the Miller capacitance effect which contributes to the mismatch of the sections causing the ripple in the gain . In this section, we will examine another topology in order to enhance the gain. In the following, the common source MOSFET configuration will be replaced by a cascode element consisting of a common-source first stage followed by a common-gate second stage [22]. The Miller capacitance effect is the main contributor to the mismatch of the sections causing the ripple in the gain. Nanometer-scale MOS devices deeply suffer from high Miller effect, which limits the amplifier’s high-frequency response. FB devices have a gate-to-drain capacitance Cgd of around 60 f F , for a total width of 60 µm. The gate-to-source capacitance Cgs to the gate-to-drain capacitance Cgd (Miller capacitance) ratio is Cgs /Cgd ≈ 2.8.

The impact of Miller effect on DA performance are: (i) less bandwidth, (ii) more ripple in the gain curve and (iii) less isolation (higher S12 ) which causes mismatch and instability of the DA. In the following, the common source MOSFET configuration cell will be replaced by a cascode element consisting of a common source transistor connected to a common-gate transistor at its drain terminal. The cascode configuration, known for its high maximum available gain, wide bandwidth, improved input-output isolation, has been used in many applications such as mixers, frequency multipliers and distributed amplifiers [23]. The cascode pair is used to obtain wideband characteristics (i) in the gate artificial line, because the amplifier does not suffer from the Miller effects, and (ii) in the drain line, because the frequency behavior of the real part of the output impedance compensates the drain line losses at high frequencies. Therefore, thanks to the cascode cell a drastic reduction of the Miller effect is obtained. As a consequence, higher power gain, wider bandwidth and improved reverse isolation are achievable, compared to common-source FET gain cells. A schematic of the loss compensation circuit in Fig. 3.21 constructed with a cascode pair of transistors and two additional transmission lines, Lcg and Lsd . The equivalent circuit is shown in Fig. 3.22. The output impedance is given by [23]:

Zoutcomp =

(Zds1 + jωLsd ) (Zds1 + jωLsd ) + (Zgs2 + jωLcg )

gm Zds2 + (Zgs2 + jωLcg ) + Zds2 jωCgs2 (3.19)

where Zgs and Zds are the gate-to-source and drain-to-source impedances of the 64

3.6

CASCODE DISTRIBUTED AMPLIFIER

transistor. The real part of the output impedance can be written as [23]:

ℜ Zoutcomp =

Rds2 (1 + ω 2 Cds2 2 Rds2 2 )

1−

gm2 Rds2 Cds2 Cgs2

(3.20)

On the hand, the real part of the output impedance of the single common-source transistor is written as:

ℜ Zoutcomp =

Rds (1 + ω 2 Cds 2 Rds 2 )

(3.21)

which is the first term in 3.20. The second term operates as negative resistance and it decreases the real part of the output impedance that causes the loss of the drain artificial line [23]. Because Lcg cancels the Zgs2 in the denominator, the negative resistance increases and gain is improved at high frequencies. The key to the design of the cascode gain cell is the matching network between the

Figure 3.21: Cascode distributed amplifier. two stages: if the length of Lcg is increased, S21 and S22 increase at high frequencies and the amplifier becomes instable. On the other hand, if the length of the other transmission line Lsd is increased, the stability of the amplifier is restored and we can obtain a flatter response. The transistor used is a 30 × 2 × 0.13 µm SOI FB transistor. After optimiza-

tion, the different design parameters are summarized in table 3.5. The final layout 65


Figure 3.22: Loss compensation circuit. is given in Fig. 3.23 with an area of 500 µm×1500 µm including RF and biasing pads.

Transistors Gate line

Drain line

compensation

Types: Floating Body WT = 30 × 2 LG /WG (µm/µm) = 480/2 LA /WA (µm/µm) = 30/2 RG (Ω)/CG (pF ) = 30/20 LD /WD (µm/µm) = 380/2 LA /WA (µm/µm) = 30/2 RG (Ω)/CG (pF ) = 30/20 LCG /WCG (µm/µm) = 350/2 LSD /WSD (µm/µm) = 350/2 Cdec (pF ) = 5

Table 3.5: CDA design parameters on 130 nm SOI technology. Another design of the CDA has been realized using a body contact instead of floating body transistors (designed by C. Pavageau from IEMN-CEA [16]). The same design parameters as before were kept except the compensation lines dimensions: (LCG /WCG (µm/µm) = 600/2) and (LSD /WSD (µm/µm) = 500/5). • Body contacted transistors In SOI technology, the partially depleted (PD) SOI processes scale well to smaller dimensions. However, the presence of buried oxide layer results in a floating body region and the low thermal conductivity causes self heating effects. Additionally, because of the floating body, SOI devices exhibit premature bipolar conduction 66

3.6

CASCODE DISTRIBUTED AMPLIFIER

Drain Line

RF pad

DC bias

Cd

Output RF pad

Input RF pad Gate Line

T2 Cdec Lcg T1

Cg

Drain line Biasing of T2’s Gate Lsd

Gate line

Figure 3.23: Chip microphotograph of the designed CDA.

relative to bulk silicon devices which coupled with the increase in the body voltage causes kink seen in the output characteristics of PD SOI n-MOSFETs [15]. Several approaches have been proposed to minimize the floating body effects in PD SOI based on either reducing life time of generated holes by introducing traps or using P+ body contacts for n-MOSFETs [24]. The latter approach includes H-gate body contact, which has considerably large foot print while allowing independent control of the body voltage. On the other hand, introducing P+ regions in the source end of the device allow low resistance path to the holes at the expense of reduced current drive for the SOI MOSFET (Fig. 3.24). This becomes more critical as device dimensions become a significant part of the device and affects device and circuit performances. For example, application of SOI devices for RF circuits such as voltage controlled oscillators, demands higher current drive to achieve lower phase noise [25]. This makes it necessary to optimize body contact structures and develop ways to minimize body contact area and/or keep current drive high [26]. Body contacted (BC) MOSFETs is widely used in critical analog circuits like 67


phase-lock loops. There are a number of ways to provide body contact, but the most common one resemble the structure shown in Fig. 3.25. The aim of this contact is to suppress the kink effect.

Figure 3.24: Floating Body and the Body Contacted SOI transistors. Floating body

Source Gate Drain

Body contacted

Source Gate Drain

Substrat contacts

Contact

n+ doping

ADLVTN

Active zone

p+ doping

ADLVTP

Gate polysilicon

N well

Figure 3.25: Comparison between the Floating Body and the Body Contacted architecture.

68

3.7


The main small-signal equivalent elements for FB and BC MOSFET transistors are extracted and presented in Table 3.6. The BC MOSFET exhibits a lower (ft /fmax ), compared to the FB, because of the increase of the parasitic capacitance Cgse as well as the gate resistance Rg [16].

SOI MOS 60x2 FB 30x2 FB 30x2 BC

Vth (V) 0.274 0.29 0.4

gm (mS) 75 40 43

gd (mS) 6.34 7.5

ft (GHz) 91 89 63

fmax (GHz) 83 125 76

Table 3.6: Comparison of the measured characteristics of the used FB and BC MOSFET transistors in 130 nm SOI technology.

3.7


Using the same measurement setup as before, the FB CDA was measured with a bias current of 40.8 mA at Vdd = 1.4 V .

10

CDA

Gain (dB)

8 6 4

CSDA

2 0 0

10 20 Frequency (GHz)

30

Figure 3.26: Reduction of the ripple using the cascode topology. As expected, the use of the cascode topology has not only increased the gain but also reduced the Miller effect. This reduction results in an improvement of the gain flatness as shown in Fig. 3.26, going from 4.5 ± 2 dB for the CSDA to 6.8 ± 1 dB for the CDA.

The difference in the 0 dB cut-off frequency is due to the fact that the input capacitance of the cascode cell is higher (around 270 f F ) than the common source MOSFET 69


used in the CSDA (around 225 f F ), which explain the lower cut-off frequency of the CDA. Both of the CDAs were measured with a bias current of 41.3 mA and 40.8 mA, respectively, and at V dd = 1.4 V . The BCDA shows a measured gain |S21 | of 5.4 ± 1.4 dB from 1 GHz to 20 GHz , with a unity-gain bandwidth of 23 GHz

(Fig. 3.28). Input and output return losses are better than −8 dB up to 20 GHz.

The FBDA has a measured S21 gain of 7.1 ± 1.1 dB from 1 GHz to 26 GHz, with

an unity-gain bandwidth of 27 GHz (Fig. 3.28). Input and output return losses are

better than −6 dB up to 23 GHz. The higher cut-off frequency of the FBDA is due to a lower capacitance Cgs for FB devices compared to BC devices. Measured values

1,4

1,4

1,2

1,2

1

1,0

0,8

0,8

0,6

0,6

0,4

Cgd (pF/mm)

Cgs (pF/mm)

of Cgs are 84 f F and 52 f F for BC and FB devices, respectively, as shown in Fig. 3.27.

0,4 FB 30x2 µm BC 30x2 µm

0,2 0

0,2 0,0

0

100

200

300 400 |Ids| (mA/mm)

500

600

700

Figure 3.27: Measured values of Cgs and Cgd for BC and FB SOI transistors. The measured noise figure is 6.5−7.5 dB over 6−20 GHz for both DAs. Although DAs are not optimized for noise performance, the noise figure is still comparable to those recently published for CMOS DA (Table 3.1). The measured output power at 1 dB compression is 5 dBm at 5 GHz for both DAs. The gain compression simulation at 5 GHz shows also an excellent agreement with measurements (Fig 3.29). As a final result obtained using the large signal RF model developed for the SOI devices, Fig 3.30 shows the simulated power gain and output power at 1 dB compression at 15 GHz as a function of the power consumption PDC. A maximum 6.3 dB power gain is reached for a power consumption of 110 mW 70

S21, S11 (dB)

3.7


10 S21

0 -10

S11

-20 -30 0

10

FBDA B CDA


40

S22, NF (dB)

10 NF

0

-10 S22

-20

FBDA BCDA

-30 0

10


40

Figure 3.28: Measured gain and input return loss (top), noise figure and output return loss (bottom) for the BCDA and FBDA at Vdd = 1.4 V . (Vdd = 2 V ), while the maximum gain to power consumption ratio is reached for a power consumption of 70 mW (Vdd = 1.4 V ). Depending upon biasing conditions, a trade off can be made either in power gain, or output power, or DC power consumption.

71

Output (dBm)

15 10 5 0 -5 -10 -15 -20 -25 -30

Output (dBm)


15 10 5 0 -5 -10 -15 -20 -25 -30

1 dB Comp

1 dB Comp

-35 -30 -25 -20 -15 -10 -5 Input power (dBm)

0

5

10

8 7 6 5 4 3 2 1 0 -1

Vdd=3 V

7 5 3

Vdd=2.5

1

Vdd=1.9 Vdd=1.4

50

75

100

125

150

175

Output power at 1 dB compression (dBm)

Power gain (dB)

Figure 3.29: 1 dB compression point @ 5 (top) and 10 (bottom) GHz.

-1 200

PDC (mW) Figure 3.30: Simulated power gain and output power at 1 dB compression as a function of power consumption at 15 GHz, for the BCDA.

72

3.7

3.7.1


Group delay

Group delay is a measure of how long it takes a signal to traverse a network, or its transit time. It is a strong function of the length of the network, and usually a weak function of frequency. It is expressed in units of time, pico-seconds for short distances or nanoseconds for longer distances. Group delay consistency (unit-to-unit, over temperature, over frequency, over attenuation state) is extremely important in receivers such as monopulse, where amplitude and phase tracking is required. So, it is important to optimize group delay in optoelectronic high bandwidth links. From a theoretical point of view, all designers would prefer to measure a constant, or relatively constant, transit time over frequency because heavy signal distortion occurs when transit time exhibits large variations over the frequency band of interest. Group delay is the negative-slope of the transmission phase angle with respect to frequency: GroupDelay = −

∆Φ ∆ω

(3.22)

where Φ is the phase angle and ω is the frequency. In a DA, the flatness of the gain is also related to the group delay fluctuations. The measured group delay dispersion was ±5 ps from 2 to 16 GHz for the BCDA

and from 3 to 20 GHz for the FBDA, respectively.

Group delay (ps)

80 70

CDA_FB

60

CDA_BC

50 40 30 20 10 0

5

10

15

20

25

Frequency (GHz) Figure 3.31: Measured group delay for the FB and BC CDA. 73


Type Transistors Width (µm) Fmax (GHz) GBW (GHz) Gain (dB) BW (GHz) Area (mm2 ) Pdc (mW)

Common Source FB 60 × 2 125 47 4 ± 1.6 1 - 30 0.75 66

Cascode FB 30 × 2 125 59 7.1 ± 1.1 1 - 26 0.75 55

Cascode BC 30 × 2 76 41 5.4 ± 1.4 1 - 20 0.75 58

Table 3.7: Measured data of the designed 4-stage common source cascode DAs. The measured characteristics are summarized and compared in the following table. The cascode SOI DAs show very good results comparing to the state-of-the-art in term of power consumption and occupied die area. FBDA and BCDA have equivalent performances compared with previously reported DAs in bulk CMOS using cascode architecture and equivalent structure layers for passive components, along with MOSFET with equivalent cut-off frequencies [1][27]. Because SOI CMOS process achieves high speed while reducing the overall power consumption, it is well suited for the ever growing high-speed microprocessor market. Moreover, the performances achieved by the BCDA and FBDA demonstrate the ability of standard SOI CMOS process for the jointed integration of microwave circuits together with high-speed DSP functions. The cascode pair is used to obtain wideband characteristics because the amplifier does not suffer from the Miller effect which limits the high frequency response and the frequency behavior of the real part of the output impedance compensates the drain line losses at high frequencies. Moreover, the output impedance is higher in a cascode pair than in the common source FET, supplying higher output currents when loaded on a 50 Ω drain line. The former characteristics give a wider bandwidths, and the latter a higher gain.

3.8

Conclusion

By reducing the gate length of the transistors, the analog performances of MOSFET for RF applications are usually improved. But this requires an increase of the fabrication process complexity. 74

3.8

CONCLUSION

The designs of fully integrated DAs with 130 nm partially depleted SOI technology using TFMS are described. Two architectures are presented: the Common Source DA and the Cascode DA. The later exhibits a flatter gain because it uses a cascode cell which reduces the Miller effect. The two DAs demonstrate a very low power consumption comparing to other DAs previously published on CMOS process (Table 3.8). They merely differ by the transistors used (Number of fingers: 60, W = 2 µm, for the CSDA, Number of fingers: 30, W = 2 µm, for the CDA) and the TFMS lines dimensions. The lower leakage current and parasitic capacitances of the SOI CMOS circuits lead to higher speed and to lower power consumption. Improvements in terms of gain, noise and bandwidth can be reached with improvement reduction of TFMS conductor losses. This is often found in the DAs using cascode gain cells, which are commonly used in high-gain/high-frequency DAs since they offer high input-output isolation, high output impedance, and high voltage swing. Furthermore, they are often used to maximize the gain-bandwidth product by inducing the negative resistance. With proper negative resistance loading, the losses in the gate and drain artificial transmission lines can be compensated, resulting in improved gain and extended bandwidth. This also allows one to use a larger number of gain cells without compromising the bandwidth. TFMS is very attractive because it keeps the amplifier performances independent on the substrate resistivity and makes the circuit layout more compact comparing to CPW or large lumped integrated inductors. Because SOI CMOS process achieves high speed while reducing the overall power consumption, it is well suited for the ever growing high-speed microprocessor market. Moreover, the performances achieved by the CDA demonstrate the ability of standard SOI CMOS process for the jointed integration of microwave circuits together with high-speed DSP functions.

Techno.

0.15µm

0.12µm

This work

This work

CMOS

SOI

SOI

SOI

SOI

Liu et al.

Plouchard et al.

CSDA

CDA-FB

CDA-BC

This work

S21 (dB)

7.3 ± 0.8

4 ± 1.2

4.5 ± 2.0

6.8 ± 1.0

5.4 ± 1.4

S11 /S22 (dB)

< −8/ < −9

< −7/ < −7

< −7.9/ < −6.7

< −6.2/ < −6.7

< −8/ < −8

BW (GHz)

0.6 − 22

4 − 91

0.4 − 30

0.4 − 26

0.4 − 20

Area (mm2 ) N F (dB)

0.9 × 1.5 4.3 − 6.1

0.8 4.2 − 6.4

0.5 × 1.5 4.6 − 7.0

0.5 × 1.5 6.4 − 7.8

0.5 × 1.5 6.5 − 7.5

Vdd (V ) Pdc (mW )

1.3

2.6

1.4

1.4

1.4

52

90

66

55

58

Table 3.8: Gain, Matching, Bandwidth, Area, Noise Figure, DC Power for state-of-the art DA’s.

75


References [1] R. C. Liu, K. L. Deng, and H. Wang, “A 0.6 - 22 - GHz Broadband CMOS Distributed Amplifier,” MTT-S Int. Mic. Symposium Digest, June 2003. [2] P.F. Chen, R.A. Johnson, M. Wetzel, P.R. de la Houssaye, G.A. Garcia, P.M Asbeck, and I. Lagnado, “Silicon-on-Sapphire MOSFET Distributed Amplifier with Coplanar Waveguide Matching,” IEEE RFIC symposium, 1998, pp. 161 – 164. [3] B.M Ballweber, R. Gupta, and D.J. Allstot, “A fully integrated 0.5 - 5.5 GHz CMOS distributed amplifier,” IEEE Journal of Solid-State Circuits, vol. 35, no. 2, pp. 231 – 239, February 2000. [4] J.Sullivan, B.A. Xaiver, D. Costa, and W.H.Ku, “An Integrated CMOS Distributed amplifier Utilizing Packaging Inductance,” IEEE Trans. Microwave Theory Techniques, vol. 45, no. 10, pp. 1969–1976, October 1997. [5] B Kleveland, C. H. Diaz, D. Vook, L. Madden, T. H. Lee, and S. S. Wong, “Exploiting CMOS Reverse Interconnect Scaling in Multigigahertz Amplifier and Oscillator Design,” IEEE Journal of Solid State Circuits, vol. 36, no. 10, pp. 1480–1488, October 2001. [6] R. Amaya, “A 0.5-10.5 GHz CMOS Distributed Amplifier using Copper Inductors,” Poster TEXPO 2001. [7] H. T. Ahn and D. J Allstot, “A 0.5-8.5 GHz fully differential CMOS distributed amplifier,” IEEE Journal of Solid-State Circuits, vol. 37, no. 8, pp. 985 – 993, August 2002. [8] B. M. Frankand A. P. Freundorfer and Y. M. M. Antar, “Performance of 1-10GHz traveling wave amplifiers in 0.18-/spl mu/m CMOS,” IEEE Microwave and Wireless Components Letters, vol. 12, no. 9, pp. 327– 329, September 2002. [9] J. O. Plouchart, J. Kim, N. Zamdmer, L. Lu, M Sherony, Y. Tan, R. Groves, R. Trzcinski, M. Talbi, A. Ray, and L. Wagner, “A 4-91 GHz Distributed Amplifier in a Standard 0.12 um SOI CMOS Microprocessor Technology,” IEEE CICC, October 2003. [10] G. A. Lee, H. Ko, and ” F. De Flaviis., “Advanced Design of Broadband Distributed Amplifier using a SiGe BiCMOS Technology,” June 2003, MTT-S Int. Mic. Symposium Digest. [11] K. W. Kobayashi, J. Cowles, L. T. Tran, T. R. Block, A. K. Oki, and D. Streit, “A 2-50 GHz InAlAs/InGaAs-InP HBT distributed amplifier,” Gallium Arsenide Integrated Circuit(GaAs IC) Symposium, 18th Annual Technical Digest, 1996. 76

3.8

CONCLUSION

[12] S. Masuda, T. Hirose, T. Takahashi, M. Nishi, S. Yokokawa, S. Iijima, K. Ono, N. Hara, and K. Joshin, “An over 110-GHz InP HEMT flip-chip distributed baseband amplifier with inverted microstrip line structure for optical transmission systems,” Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 24th Annual Technical Digest, 2002. [13] J. M. Carroll, A. Coutant, M. S. Heins, C. F. Campbell, and E. Reese, “0.25 um pHEMT 40Gb/s E/O modulator drivers,” 2002, vol. 1, MTT-S Int. Mic. Symposium Digest. [14] A. A. Sweet, MIC & MMIC Amplifier and Oscillator Circuit Design, Artech House, 1990. [15] J.-P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI, Kluwer Academic Publishers, 2 edition, 1997. [16] C .Pavageau, Utilisation des technologies MOS avances pour des applications en gamme millimtriques, Ph.D. thesis, IEMN - Lille - FRANCE, Decemeber 2005. [17] A. Siligaris, G. Dambrine, D. Schreurs, and F. Danneville, “A new empirical nonlinear model for sub-250 nm channel MOSFET,” IEEE-Transactions-onElectron- Devices, vol. 51, no. 10, pp. 1605–1612, October 2004. [18] G. Dambrine, J.-P. Raskin, F. Danneville, D. Vanhoenacker Janvier, J.-P. Colinge, and A. Cappy, “High-frequency four noise parameters of silicon-oninsulator-based technology MOSFET for the design of low-noise RF integrated circuits,” IEEE-Transactions-on-Electron- Devices, vol. 46, no. 8, pp. 1733–1741, August 1999. [19] C. Pavageau, M. Si Moussa, A. Siligaris, L. Picheta, F. Danneville, J-P. Raskin, D. Vanhoenacker-Janvier, J. Russat, and N. Fel, “Low Power 23-GHz and 27GHz Distributed Cascode Amplifiers in a Standard 130nm SOI CMOS Process,” IEEE MTT - S International Microwave Symposium, June 11-17 2005. [20] A. Kraszewski, “Prediction of the dielectric properties of two phases mixtures,” Journal of Microwave Power, vol. 12, no. 3, pp. 215, 1977. [21] C. S. Aitchinson, “The intrinsic noise figure of the MESFET distributed amplifier,” IEEE Trans. Microwave Theory Techniques, vol. 33, no. 6, pp. 460 – 466, June 1985. [22] F. Giannini, E. Limiti, G. Orengo, A. Serino, and M. DE Dominics, “Design improvements in distributed amplifires for optical receiver front ends,” Microwave and Optical Technology Letters, vol. 39, no. 3, pp. 190 – 193, November 5 2003. 77

[23] S. Kimura, Y. Imai, Y. Umedo, and T. Enoki, “Loss-Compensated Distributed BaseBand Amplifier IC’s for Optical Transmission Systems,” IEEE Trans. Microwave Theory Techniques, vol. 44, no. 10, pp. 1688 – 1693, October 1996. [24] Y. Tseng, W. M. Huang, D. J. Monk, P. Welch, J. M. Ford, and J. C. S. Woo, “AC floating body effect and the resultant analog circuit issues in submicron floating body and body-grounded SOI MOSFETs,” IEEE-Transactions-on-ElectronDevices, vol. 46, no. 8, pp. 1685 – 1692, August 1999. [25] A. Hajimiri and T. H. Lee, “Design issues in CMOS differential LC oscillators,” IEEE Journal of Solid State Circuits, vol. 34, no. 5, pp. 717 – 724, May 1999. [26] A. Daghighi and M. A. Osman, “Two-dimensional model for investigating body contact structures in PD SOI MOSFETs,” Microeletronic engineering, vol. 70, pp. 83 – 92, 2003. [27] R. E. Amaya, N.-G. Tarr, and C.-P. Plett, “A 27 GHz Fully Integrated CMOS Distributed Amplifier using Coplanar Waveguides,” IEEE RFIC Symposium, pp. 193–196, 2004.

CHAPTER 4 PERFORMANCES VS. TEMPERATURE 4.1

Introduction

One of the main market for SOI devices is the high-temperature applications. In the last decade, the technology advances to deep submicron to improve device performances in term of cut-off frequency. Recently, a SOI CMOS technology with a transit frequency (ft ) of 243 GHz and maximum frequency of oscillation (fmax ) of 208 GHz has been reported [1]. Some applications (such as well logging, avionics, automotive, ...) require electronic circuits capable of operating at temperature up to 300o C. The capability of SOI circuits to expand the operating temperature range of integrated circuits up to 250o C has been demonstrated [2][3]. SOI devices and circuits present advantages in this field over bulk counterparts such as the absence of thermally-activated latchup and reduced leakage current. This is because SOI MOSFETs present several properties which allow them to operate in harsh environment such as the small volume of silicon in which the devices are made and the small area of the source-body and drain-body junctions. The temperature ranges within electronics devices may have to work in oil wells, gas wells, steam injection processes and geothermal energy plant applications are listed in Table 4.1 [3]. High temperature is a large value market that has been difficult to serve up to now. In automotive electronics, on-engine and on-transmission applications are projected to require maximum temperatures of up to 200o C with the wheel-mounted applications going even higher. These applications include engine control, transmission control, antilock brake system (ABS), active suspension and wheel speed sensors. Further high temperature application areas include aerospace and environmental monitoring, such as mining and well logging. A system in which both the sensor and control electronics are fabricated in SOI technology would allow the complete assembly to reside in a thermally harsh environment. This would allow cost and weight reduction by eliminating requirements for cabling for remotely located electronics [4]. In the following, we will study the behavior of an RF amplifier vs. high temperature. the studied amplifier is a four stage DA is designed on a 130 nm partially depleted (PD) SOI technology, using floating body (FB) transistors and Thin Film 79

CHAPTER 4. PERFORMANCES VS. TEMPERATURE

Applications Well logging Oil Wells Gas Wells Steam injection Geothermal energy Automotive Underhood Engine sensors Combustion and exhaust sensors ABS Aircraft Internal equipment Engine monitoring Surface controls Satellites (Venus probe) Commercial nuclear

Temperatures 75 − 600o C 75 − 175o C 150 − 225o C 200 − 300o C 200 − 600o C 150-600C −50 − 600o C up to 600o C up to 600o C up to 600o C 150 − 600o C 150 − 250o C 300 − 600o C 300 − 600o C 150 − 600o C 30 − 550o C

Table 4.1: Temperature requirements for electronics components used in several consumer or industrial applications [3]. Micro Strip (TFMS) lines. This amplifier was simulated with ADS r Agilent Technologies Software. The active devices used in the design are FB transistors composed of 30 and 60 fingers having a width of 2 µm per finger.

4.2

SOI at high temperature

All harsh environment electronic systems are dependent upon the performance and life of Si components, from a simple field effect transistor (FET) to very large scale integrated circuits (VLSIs). Conventional semiconductor components are based on bulk Si structures but these devices suffer from performance and life concerns at elevated temperature. At least three major challenges exist in the bulk Si CMOS structure at elevated temperature: • Device leakage current due to bipolar transistors found in bulk CMOS. • Gate oxide leakage and punch through. • Surface metal migration. In a digital component the delays increase, the slew rate reduces and the device once again will stop functioning at a (device) specific temperature. In an analogue component the leakage current will affect almost all parameters such as input bias 80

4.3

ACTIVE DEVICES

and offset current, input offset voltage to gain bandwidth and noise margins. The life of a CMOS component is also affected by the increasing leakage current of the bipolar transistors: the leakage current in the bipolar transistors increases with time at elevated temperature and will result in destructive latchup. Another life issue with bulk Si at elevated temperature is gate oxide breakdown. As temperature increases gate oxide breakdown occurs, first seen as increased leakage then as gate punch through. The effect of this can be seen in loss of non-volatile memory due to destructive gate breakdown over time at temperature [5]. There are further life concerns associated with bulk Si metal systems at high temperature. Standard aluminum metal will migrate at elevated temperature and this can result in open or short circuit devices. Migration is a function of temperature and current density. This is also a concern in die shrink at lower temperatures as the current density is generally increasing in the small feature size. A list of the Honeywell device design parameter adjustments made in addition to their special die metal structures is shown in Table 4.2 [5]. Issue Junction leakage Sub-threshold leakage Electro migration Reduced mobility Bias voltage drift with temperature Self heating Floating-body effect Back-gate transistors

Primary mitigation strategies SOI process Vth adjustment Design rules to lower maximum current density Design adjustment: Temp. compensated biasing Design techniques (eg ZTC biasing) Design for lower power density, layout floor planning, metal-interconnect heat-spreading etc Partially-depleted SOI with body tie Increased back-oxide thickness

Table 4.2: Mitigation strategies for issues in harsh environment SOI (Honeywell) [5].

4.3

Active devices

The use of the bulk CMOS MOSFET’s in the high-temperature range is limited by the latch-up due to the leakage current through the well junction which becomes very large at high temperature. The SOI CMOS can be a viable alternative because the almost perfect isolation of NMOS and PMOS is afforded by the elimination of the CMOS well junction which results in latchup-free operation. Therefore, there is a practical need for a temperature-dependent SOI MOSFET model for circuit and device simulation [6]. SOI MOSFETs have lower leakage currents than bulk devices at high temperature, as well as a smaller variation of threshold voltage with temperature. They are also immune to temperature-induced latchup. As a result, SOI circuits can operate at 81


temperatures above 300o C, while bulk CMOS is usually limited to 150o C. Lowtemperature operation improves mobility and subthreshold slope. PD-SOI MOSFET, still the most popular SOI technology in the industry, (Fig. 4.1) shows a quasi-neutral region sandwiched between the space-charge regions extending from the front, lateral and back oxide/Si interfaces and S/D junctions, and hence, usually left electrically unconnected or floating.

Figure 4.1: Partially depleted SOI MOSFET transistor. A variety of circuit design methods, can be used to improve high temperature performance of microelectronics. Analog circuits, in particular, are required not only to function, but to have some measures stability over temperature. An example of that is studying the Zero-Temperature-Coefficient (ZTC) point of MOSFETs. The Zero-Temperature-Coefficient (ZTC) bias point is defined as the bias at which (T ) the drain current exhibits zero variation temperature ( dIds = 0) [7]. dT

In the following a 60 × 2 × 0.13 SOI PD MOSFET is measured in DC and RF for

a temperature range going from 25 to 250o C.

4.3.1

DC Measures

The n- and p-MOSFET characteristics in saturated or linear region have a ZTC point where the temperature mobility compensates the threshold voltage shift (Fig. 4.2). On the contrary to bulk devices, the ZTC point of SOI MOSFETs is approximately constant with temperature, corresponding to a constant threshold voltage shift (Fig. 4.3) and low leakage current. In bulk semiconductor technologies, reverse-biased p/n junctions are used to isolate the devices, and the leakage current of these parasitic diodes is most likely the 82

4.3

ACTIVE DEVICES

35 T=25°C

30

Ids (mA)

25 20 15

T=250°C

ZTC 10 5 0 0

0.2

0.4

0.6

0.8

1

1.2

1.4

Vgs (V)

Figure 4.2: Ids vs. Vgs @ saturation Vds = 1.2 V .

limiting factor for high-temperature operation. Bulk silicon integrated circuits generally cannot function properly at temperatures beyond 200o C, due to this problem. At moderate temperatures, the reverse saturation current of the parasitic diodes is quite small. However, this leakage current increases rapidly at high temperatures, and is comparable to channel currents. Leakage currents can cause an operating point shift in analog circuits, and cause loss of data stored in dynamic digital circuits. The current also contributes to self-heating of the device, and the power dissipation can be very large at elevated temperatures. The leakage current of a p/n junction mainly consists two components: diffusion current and space-charge generation current. The diffusion current is generated in neutral regions where there is no significant electric field. The carriers move by diffusion from areas of higher carrier concentration to areas of lower carrier concentration. When these carriers reach the edge of the depletion region, they are swept across the junction by the electric field. On the other hand, generation current is due to thermal generation of electron-hole pairs inside the depletion region. These carriers are separated and swept across the region by the electric field. It is clear that both leakage currents are proportional to junction area, which should be minimized [8]. The junction leakage current is smaller by orders of magnitude in thin-film SOI as compared to bulk transistors due to the absence of diffusion leakage to the substrate. Since the dominant leakage current is the generation term in the fully depleted volume under the channel, the leakage current decreases with reduction of the device length. However, beyond a minimum limit corresponding to an optimum length, the junction leakage current increases rapidly with the reduction of the device length as 83


a result of short-channel effects including sub-threshold leakage [8] [3].

Figure 4.3: Measured threshold voltage versus temperature. The output conductance of partially depleted SOI MOSFETS is relatively insensitive to temperature, a tremendous advantage compared to bulk MOSFETs in which output conductance is known to increase very rapidly above 150o C, since the drain junction leakage current becomes a significant component of the overall drain current [8].

0.06

gd (S)

0.05 0.04 Vgs=0.3V 0.03 0.02

Vgs=0.6V

0.01 Vgs=0.9V 0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

1

1.1

Vds (V)

Figure 4.4: Output conductance gd for Vgs=0.3, 0.6 and 0.9 V. Because the body of the SOI devices is electrically floating, impact ionization84

4.3

ACTIVE DEVICES

related effects (kink effect, parasitic bipolar action, ...) tend to degrade the output conductance of SOI MOSFETs. It is observed that output conductance of SOI MOSFETs actually improves when temperature is increased (Fig. 4.5).

Figure 4.5: Output conductance gd dependence on temperature. This is explained by several mechanisms: high temperature reduce impact ionization near the drain, excess minority carrier concentration in he device body is reduced through increased recombination, and the body potential variations are reduced owing to an increase of the saturation current of the source junction [3]. A Si CMOS transistor in the saturation region has higher transconductance gm at room temperature than at high temperature since carrier mobility decreases when temperature is increased (Fig. 4.6). The saturation region gm exhibits a ZTC point at 0.27 V as can be seen in Fig 4.6. The value of gm at ZTC bias is almost 50% its value at 25o C. The saturation region gm ZTC bias point can be utilized in analog circuit design for high temperature applications [9]. As shown in Fig. 4.7, PD-SOI devices exhibit the kink effect, a circuit behavior not present in bulk technology, which is effect is caused by the floating body. The floating body also gives rise to hysteresis, causing different switching delays on subsequent switching edges in digital circuits.

85


Figure 4.6: Gate transoncductance gm @ saturation for different temperatures.

0.025

T=25°C

Ids (A)

0.02

Vgs=0.9V

0.015

T=25°C

T=250°C

0.01

Vgs=0.6V T=250°C

0.005

T=250°C

0

Vgs=0.3V

T=25°C -0.005

0

0.2

0.4

0.6

0.8

1

1.2

1.4

Vds (V)

Figure 4.7: Ids vs. Vds for Vgs=0.3, 0.6 and 0.9 V.

86

4.3

ACTIVE DEVICES

The following figure depicts the behavior of a PDSOI transistor with the increase of temperature [3].

Figure 4.8: Temperature increase effect on a PD SOI. In the high temperature, the reduction of the front-channel threshold voltage and the increase of leakage current in the body-drain junction due to the increased thermal generation in the reverse biased junction and in the depleted body film. The channel mobility degradation in the high temperature due to the increased phonon scattering results in reduced drain current. The decrease of drain current and the increase of saturation voltage due to the reduction of threshold voltage cause the reduction of generation by weak impact ionization and hence, the shift in the kink effect to higher drain biases [6].

87


4.3.2

RF Measures

In the following, some specific aspects of the frequency behavior of the MOSFET vs. high temperature are studied. RF measurements were performed with a Anritsu 37369A vector network analyzer operating up to 40 GHz. Temperature control is provided by a Temptronics 8-in temperature chuck up to 250o C. The gate length reduction of MOSFETs has increased significantly the cut-off frequency of transistors, allowing designing circuits working at several GHz. The most relevant figure-of-merit for the high-frequency capabilities of a process is the maximum frequency of oscillation. Based on the different gains, it is possible to define several cut-off frequencies, as the frequency for which a gain becomes equal to unity or 0 dB. The most used ones are the followings [10]:

• ft : This is the most widely used definition of cut-off frequency. And it is defined as cut-off frequency of the current gain H21. It can be approximated for a MOSFET by the following relation: ft ≈

gm 2πCgg

(4.1)

where Cgg is the total gate capacitance of a MOSFET (Cgg = Cgs + Cgd ), and gm is the transconductance. ft is only function of the intrinsic parameters of the MOSFET. It is then an important coefficient to compare different technologies and devices. As it is nearly proportional to gm and 1/Cgg , which are proportional to the width of the transistor, ft is nearly not sensitive to the total width of a MOSFET. • fmax : Usually called the maximum frequency of oscillation, fmax is defined using

the MAG (Maximum available Gain) or the ULG (UniLateral Gain). It is the highest frequency where the device is able to provide power when it is in a stable state. As for ft , it is possible to develop a simplified expression of fmax as follows: ft fmax = p 2 2πft Rg Cgd + gd (Rg + Rs + Rgsi )

(4.2)

It is important to notice that fmax is expressed as a function of ft . Contrarily to ft , fmax is sensitive to the width of the gate, and to all the parasitics which surround the transistor. ft and fmax are directly extracted from S-parameters measurement as the cut-off frequencies of H21 and MAG respectively [10].

88

4.3

ACTIVE DEVICES

160 Ft Fmax

Ft, Fmax (GHz)

140 120 100 80 60 40 20 0 0

100 200 Temperature (°C)

300

Figure 4.9: Ft and Fmax versus T. As shown in Fig. 4.9, the degradation of the current gain cut-off frequency is due to the decrease of the transconductance gm and an increase of 10 to 15% observed on the capacitances, as shown in the following figures, for gate, drain and Miller capacitances. The capacitances values are computed after performing an open substation, in order to remove the effects of the access pads, and computed using the Y parameters as follows:

ℑ (Y11 + Y12 ) 2πf −ℑ (Y12 ) Cgd = 2πf ℑ (Y22 + Y12 ) = 2πf

Cin =

Cout

(4.3) (4.4) (4.5)

where f is the frequency.

89


Cgs(fF)

70

T = 250 °C

60

50 T = 25 °C

40 5

10

15

20

Frequency (GHz)

Figure 4.10: Measured input capacitance Cgs versus temperature.

36

Cgd (fF)

34

T = 250 °C

32 30 T = 25 °C

28 5

10

15

20

Frequency (GHz)

Figure 4.11: Measured Miller capacitance Cgd versus temperature.

90

4.3

ACTIVE DEVICES

40

Cds (fF)

35

T = 250 °C

30 25

T = 25 °C

20 5

10

15

20

Frequency (GHz)

Figure 4.12: Measured output capacitance Cds versus temperature. In the following table are summarized the degradation of some measured parameters for the studied transistor.

Vth ft fmax gm gd Cgs Cgd Cds

30 × 2 × 0.13 FB SOI MOSFET − 3% − 42% − 30% − 25% − 7% + 15% + 10% + 20%

Table 4.3: Degradation of some measured parameters for the studied transistor from 25 to 250o C. The table shows a decrease of the gate transconductance for all the studied transistors with the increase of temperature. The decrease in the transconductance of the SOI MOSFET of about 28% as shown in Fig. 4.6. Also shown in this figure the evolution of the threshold voltage as a function of temperature which drops by 20% from room temperature up to 250o C. This can be explained by the fact that gm exhibits a negative temperature coefficient [11]. It has shown that, when the device is operated in the saturation region the gm characteristics at different temperatures intersect at a single gate bias. When a device is biased at Ids ZTC bias point in the saturation region, the gate 91


transconductance drop by 50% between room temperature and 200o C. However, for a device biased at gm ZTC in the saturation region, the transconductance remains constant over the temperature range.

4.3.3

Conclusion

Bulk Si devices, which rely on electrical isolation through reverse biased p/n junctions, fail above 200o C, primarily due to high leakage currents. Several attempts have been successful at 200o C, but beyond that temperature it seems unlikely to design a reliable circuit. Silicon IC chips fabricated using silicon-on-insulator (SOI) technology can operate at temperatures up to 300o C. Because this fabrication technology uses dielectric materials to isolate devices rather than reverse-biased junctions, leakage currents at high temperatures can be reduced by two to four orders of magnitude. Here, the effect of the increasing temperature on some MOSFET’s parameters is shown. The present analysis can help RF engineers to understand the temperature dependence of the performances of RF MOSFETs, which is very important for designing less temperature-sensitive RF MOSFETs and RF-IC’s. Robust circuit design is highly influenced by the accuracy of MOSFET RF parameters which impact calculation of many circuit parameters such as gain, bandwidth and design stability. One of the adopted techniques is to use devices biased at their saturation (ZTC) points to maintain constant DC biasing over temperature.

92

4.4

4.4

PASSIVE DEVICES

Passive devices

Practical application of integrated circuits requires the consideration of a wide temperature range, and transmission lines are widely used in MMIC’s as interconnects and matching networks. Therefore, there is a need to investigate the practical application of the transmission line structures on SOI substrate through temperature as a function of frequency. Transmission lines can be implemented using thin film microstrip (TFMS) or coplanar waveguide (CPW) lines. For the TFMS, metal1 and 2 were used for the ground plane and metal6 for the signal line. The CPW is implemented on metal6 layer. Both configurations on 130 nm SOI process were modeled through full-wave EM simulations with HF SS r Ansoft software environment [12]. In the next paragraphs, the behavior of transmission line topologies (TFMS and CPW) versus temperature is presented. Their performances, in terms of attenuation coefficient, using both low and high resistivity silicon substrate are presented. On-wafer measurements were performed on the TFMS and CPW, with a Anritsu 37369A vector network analyzer. Temperature control is provided by a Temptronics 8 − in temperature chuck up to 250o C. 100 µm-pitch ground-signal-ground (GSG) high frequency coplanar Probes have been used for signal measurement. The measurements were done over the temperature range from 25o C to 250o C. To characterize the studied lines, we have to go through two steps calibration. Using standards made on an alumina substrate. These standards are certified, and allow us making an accurate calibration up to 40 GHz. After this calibration, the reference planes move at the end of the probe tips, and the reference impedance is equal to 50 Ω. The next step consist of a TRL (Thru-Reflect-Line) calibration in order to determine the characteristics of the TFMS and CPW lines made on the silicon-wafer, in term of lineic losses. The latter step is repeated for each temperature level.

4.4.1

Microstrip Lines

Microstrip lines TFMS are made of a conductor, laying above a ground plane. Fig. 4.13 shows the cross section of the line. TFMS lines were realized on high resistivity (HR) and standard resistivity (STD) SOI wafers. Six metal layers+Alucap layer were available on the 130 nm SOI process. In a TFMS structure, the ground plane avoids coupling between the signal and the substrate. Thus, the properties of TFMS are independent of the substrate used, and the conductor losses are dominant. 93


Figure 4.13: Top view (a) and cross section (b) of TFMS. For our study, we have drawn 4 calibration kits with different widths as summarized in the following table.

Metal layers M6+Alucap M6 M6 M6+Alucap M6+Alucap

Metal width W (µm) 7 7 2 5 9

Table 4.4: TFMS calibration kit. The calibration kit contains a microstrip line, a thru line, a short and an open structure (Fig. 4.14). These structures allow the computation of the losses after using a TRL de-embedding method [13]. The standards usually utilized for TRL calibration are two lines, and a reflective device. The latter can be an open or a short circuit. The line is designed to have a characteristic impedance of nearly 50 Ω . Fig. 4.14 shows typical standards necessary for a TRL calibration. The strip line is embedded in CPW to Strip line transitions. Their effects are canceled by the TRL calibration. Two versions of the 7 µm-wide TFMS structure were designed, for one the signal conductor is made only in metal6 and the orther stacking metal6 and an extra aluminimun layer (Alucap) of 0.88 µm. The TFMS Lines were implemented using the upmost 0.9−µm-thick metal 6 layer as signal conductor, and using metal1 and metal 2 layers stacked together to form the ground plane. The total dielectric layer thickness is 2.9 µm. It is composed of a multilayered structure of silicon dioxide and silicon nitride spacers, as shown in Fig. 4.15.

94

4.4

PASSIVE DEVICES

Line

Open

Short

Thru

Figure 4.14: Chip microphotograph of the designed TFMS calibration kit.

W Alucap Copper (M6) 0.9 µm

1.78 µm 2.9 µm

Mulilayered-dielectric (oxide/nitride) Copper (M1 + VIA1 + M2) STI (oxide) Buried Oxide Si Substrate Figure 4.15: Geometry of TFMS.

The following figure shows the losses versus frequency for various available TFMS geometries. The lineic losses are defined as the ratio of the real part of the propagation constant (γ = α + jβ) and the length of the line. As expected, the line losses increase with the reduction of the conductor width. Two versions of the 7 µm calkit were designed: one with metal 6 layers and the other with metal6+Alucap. What was not expected is the influence of the Alucap layer on the losses of the TFMS as shown on Fig. 4.17. The use of the Alucap layer enables a reduction of 33% of the losses at 20 GHz .

95


Figure 4.16: Measured losses for various TFMS line geometries.

4.4.2

Coplanar Waveguide

Coplanar waveguides are made of a central conductor, surrounded by two ground planes. It is usually laying between two mediums, the mechanical substrate, and air. Fig. 5.6 shows a cross section and a top view of the CPW structure used in SOI technology. The characteristic impedance of CPW can be fixed on a wide range by changing the width of the central conductor (W), or the spacing between the central conductor and the ground planes (S). The losses in CPWs are of two kinds: conductor losses, due to the resistivity of the metal and substrate losses, due to the coupling between the line and the substrate. In order to investigate the behavior of a CPW in RF for high temperature application, a complete Calibration kit was drawn for 50 Ω characteristic impedance (W = 40 µm, S = 24 µm), containing 1 through line, 1 short, 1 open and 1 long line, in Metal 6 only, as shown on the following figure. The actual multilayered structure drawn on the 130 nm SOI process is detailed in the Fig. 4.20. The calkit was designed on standard (STD) as well as on high resistivity (HR) substrate, and the measured losses are obtained after a TRL deembedding method. Fig. 4.21 compares lines losses for a 50 Ω CPW line on standard and high resistivity SOI substrates. High resistivity substrate exhibits significantly reduced losses 96

4.4

PASSIVE DEVICES

Figure 4.17: Effect of the Alucap layer on the losses.

Figure 4.18: Top view (a) and cross section (b) of CPW. with a value of 0.3 dB/mm at 15 GHz. The attenuations of the CPW structures were also compared to the 50 Ω TFMS lines designed with and without the Alucap layer (Fig 4.22. TFMS even without Alucap layer is still better than CPW on standard resistivity. We note clearly the advantage of the CPW HR comparing to the CPW STD in term of losses, as already demonstrated in several published papers [14]. This is due to the quality of HR substrate which contributes to reduce drastically the substrate losses. On the other hand, with CPW configuration, characteristic impedance is depending on the aspect ratio k = W/d, d = (W + 2S). This means that high impedance values are achieved for small value of k and are not only related to the signal conductor width. This enables to use wide lines for reducing metal losses with the drawback of large area use.

97


Short

Open

Thru

Line

Figure 4.19: Chip microphotograph of the designed CPW calibration kit.

W

S 0.9 µm Cu

STD-Si substrate (20 Ω.cm) OR HR-Si substrate (>1000 Ω.cm)

Oxide (SiO2) (2.2 µm) Dielectric (770 nm) BOX (400 nm)

Figure 4.20: Geometry of the designed CPW.

98

4.4

PASSIVE DEVICES

Figure 4.21: Measured lineic losses of CPW on STD, HR substrate at room temperature.

Figure 4.22: Measured lineic losses of CPW on STD, HR @ room temperature.

99


4.4.3

Temperature behavior

In order to study the behavior versus temperature, the measurements were performed over the temperature range from 25 to 250o C. Using a classical TRL de-embedding method, the lineic losses were extracted as shown in Fig. 4.23, the measurements done on the TFMS show an increase of 80% of the lineic losses with respect to temperature which is due to the positive temperature coefficient of the metallic strip. The temperature dependence of resistivity is often represented by the empirical relationship [15]: ρ(T ) = ρ0 + k(T − T0 )

(4.6)

where ρ0 is the resistivity of the material at a reference temperature T0 , usually room temperature, and k is the temperature coefficient [15].

Figure 4.23: Measured lineic losses vs. frequency and temperature (W = 7 µm). The same measurements setup was also applied to the CPW on standard and high resistivity (STD and HR) SOI substrates (Fig 4.24). For CPW, the increase of the losses is more important on HR compared to STD, but its performance is still interesting at 250o C: compared to a 50 Ω TFMS, the CPW HR shows 50% less loss, because CPW structures enable using wider lines to achieve the same characteristic impedance which allows reducing the metallic losses. Lineic losses of CPW HR, CPW STD and TFMS were plotted in Fig. 4.25 with respect to temperature. We note a decrease of the losses for the CPW STD (because 100

4.4

PASSIVE DEVICES

Figure 4.24: Measured lineic losses vs. frequency of CPW on STD and HR Si Substrate (W = 40 µm, S = 24 µm). of the decrease of the substrate losses), till 200o C due to the mobility reduction of free carriers in the substrate at higher temperature [16]. Above 200o C, the losses start to increase for both CPW STD and CPW HR. This is due to the increase of the metallic losses on the one hand, and the degradation of the substrate resistivity on the other hand for the HR substrate. For the TFMS, there is a linear increase of lineic losses as expected, because the conductor losses are dominant, as shown earlier.

Figure 4.25: Comparison of measured lineic losses vs. temperature of CPW and TFMS @ 10 GHz.

101


4.4.4

Resistivity Behavior

In TFMS, the back ground plane shields the Si substrate and therefore avoids coupling between the signal and the lossy substrate. Thus the electrical characteristics of TFMS are independent of the substrate resistivity, as shown in Fig. 4.26. Consequently, the TFMS allows the use of standard resistivity (20 Ω.cm) SOI substrates. Furthermore, compared to coplanar transmission lines, microstrip lines are preferred since they have a higher effective inductance per length. Thus, the lines can be kept compact.

Figure 4.26: Losses versus frequency for TFMS lying on low (LR, 20 Ω.cm) and high (HR, > 1000 Ω.cm) SOI substrates. For CPW, as shown in Fig. 4.27, comparing the attenuation coefficient (α) of the two lines made on SOI, the importance of the substrate losses is highlighted. The substrate losses dominate in the case of standard resistivity substrate. Up to now, CPW lines on standard resistivity substrates (20 Ω.cm) exhibited very high losses. But recent availability of high resistivity SOI substrate (5 kΩ.cm) [17] or the transfer onto fused silica of SOI standard resistivity substrates makes CPW configuration an interesting solution for implementing low loss lines [18]. High frequency characteristics of transferred layers are compared to the ones on standard SOI substrates by measuring coplanar transmission lines. Fig. 4.28 shows the geometry of the measured coplanar line [18]. The coplanar waveguide (CPW) is fabricated with a 0.4 − µm thick Al metalization on 0.25 µm CMOS SOI technology from

CEA-LETI. The underlying silicon substrate has a resistivity of 20 Ω.cm. On the 102

4.4

PASSIVE DEVICES

Figure 4.27: Measured lineic losses vs. frequency of CPW on STD and HR Si Substrate at room temperature (W = 40 µm, S = 24 µm). other hand, the ”transferred layer substrate” is entirely composed of silicon dioxide, including the passivation, the buried oxide and the fused silica substrate. The CPW structure has been measured at CEA-LETI. Fig. 4.29 compares attenuation a in the CPW line on the standard substrate and on fused silica substrate.

Figure 4.28: 3D view of the measured transmission coplanar waveguide on standard substrate and transferred substrate on fused silica. The fused silica substrate clearly exhibits a significantly reduced loss, with a value lower than 0.25 dB/mm at 10 GHz. Even if the resistivity of aluminum strips 103


Figure 4.29: Extracted lineic losses on standard substrate, and transferred substrate on fused silica for the measured coplanar transmission line. and CPW geometry can slightly modify the attenuation, these low values are comparable to results obtained on GaAs semi-insulating substrates and high resistivity Si-substrates [19] [20]. The transfer process preserves the electrical properties of active transistors. It also provides a significant performance improvement for high frequency devices, by reducing substrate loss of transmission lines and passive elements. The industrialization of such a technology leaves a lot of scope for wafer level packaging approach of SOI devices and for processed layers stacking for 3D devices.

104

4.4

4.4.5

PASSIVE DEVICES

Discussion

• TFMS do not see the substrate, but suffer from higher losses than

CPW lines on HR substrates due to small conductor width: the properties of TFMS are independent of the substrate used, because the ground plane avoids coupling between the signal and the substrate. Thus, the conductor losses are dominant.

• AluCap is efficient in reducing conductor losses for TFMS: we note a reduction in losses of 0.35 dB/mm at 20 GHz when using Alucap. Adding Alucap

exhibits much more impact comparing to the effect of increasing the width of the microstrip line W.

• CPW losses are twice lower, despite the use of Metal6 only: more than 50% less loss for a 50 Ω CPW on HR compared to a 50 Ω TFMS with

Alucap. Because CPW structures enables using wider lines to achieve the same characteristic impedance which allows reducing the metallic losses. • Behavior of passives versus temperature: the loss characteristics of STD and HR CPW and TFMS structures were investigated over a wide range of temperature. As expected, the losses increase with respect to the temperature except for the STD CPW: the substrate resistivity increases with the rise of temperature which compensates the metallic losses and thus makes the CPW losses decreasing with respect to temperature till 200o C. These results demonstrate the feasibility and practical applicability of different passive structures in circuits design for both room and high temperature applications.

In CMOS processes, the steady increase in the number of metal layers and the increase of interlayer dielectric thickness enables using wider lines and yields conductor losses reduction with TFMS. Moreover, signal conductor is shielded from the substrate avoiding coupling effects and thus TFMS electrical characteristics are unrelated to substrate resistivity, allowing standard resistivity SOI substrates (20 Ω.cm). The drawback of TFMS is that high characteristic impedance are achieved while reducing microstrip width and while increasing dielectric thickness. These lead to high metal losses when TFMS are implemented on thin dielectric film, which is often the case with digital CMOS process.

105


Due to the rapid increase in the number of metallic interconnects, the top level metals will be situated further away from the SOI substrate as the technology scales, thus reducing the substrate losses for CPW and widen the metallic strip for TFMS. In a near future, 12 metal levels will be available [21] and will enable using 5 times wider strips for TFMS and thus reduce the losses by a factor of 3 making TFMS as a very promising structure for RF design for the next technological node.

4.4.6

Conclusion

SOI CMOS technology is now emerging as a mature technology for the realization of high-temperature integrated circuits. TFMS can then be an interesting topology if the losses can be lowered to the same level than CPW made on HR SOI. Losses of TFMS and CPW made on HR and STD SOI wafers were analyzed with respect to temperature. TFMS allows the use of STD substrate because the back ground plane shields the Si substrate. TFMS can then be an interesting topology if the losses can be lowered to the same level than CPW made on HR SOI. For the CPW, the losses are of two kinds: conductor losses, due to the metal resistivity, and substrate losses, due to the coupling between the line and the substrate. These results demonstrate the feasibility and practical applicability of different passive structures in circuits design for both room and high temperature applications. To reduce the attenuation coefficient of TFMS lines, the width and the thickness of the conductor must be increased, but the capacitance between the conductor and the ground plane must be kept constant ensuring the same characteristic impedance. To achieve this goal, the thickness of the dielectric layer must be increased, or low-K dielectric must be used instead of silicon dioxide. These solutions are in agreement with the tendencies of semiconductor industries. Indeed, more and more metal levels are used, allowing a thicker isolator layer between the conductor, made with the top metal layer, and the ground plane. Furthermore, low-K dielectric will be used as insulator between the different metal layers to reduce the capacitive coupling between metal lines.

106

4.5

4.5

ANALYSIS OF THE DESIGNED DAS AT HIGH TEMPERATURE

Analysis of the designed DAs at high temperature

The use of the bulk CMOS MOSFET’s in the high-temperature range is limited by the latchup due to the leakage current through the well junction which becomes very large at high temperature. The SOI CMOS can be a viable alternative because the almost perfect isolation of NMOS and PMOS is afforded by the elimination of the CMOS well junction which results in latchup-free operation. Therefore, there is a practical need for a temperature-dependent SOI MOSFET model for circuit and device simulation. For the temperature analysis, on-wafer measurements were performed on the designed distributed amplifiers, FB CSDA and CDA [22][23], using Anritsu 37369A vector network analyzer operating up to 40 GHz. 100 µm-pitch ground-signal-ground (GSG) high frequency coplanar were used for signal measurement and for circuit biasing. The measurements were done at Vdd = 1.4 V , over the temperature range from 25 to 300o C. The measured results include the parasitic effects of the RF pads.

4.5.1

Behavior of the CSDA at high temperature 8

6 |S21| (dB)

T=25°C 4

2 T=300°C 0 0

10

20 Frequency (GHz)

30

Figure 4.30: Measured CSDA gain versus frequency at various temperatures (25, 50, 100, 150, 200, 250 and 300o C). As shown in Fig. 4.30, the decrease in gain and bandwidth versus temperature is important: gain at midband and bandwidth are of 4.5 dB and 30 GHz, respectively, at room temperature and of around 2 dB and 15 GHz at 300o C.

107


Temperature o C Room temperature 50 100 150 200 250 300

S21 @ midband (dB) 4.61 4.17 3.36 2.46 1.9 1.54 1.46

Cut-off frequency @ 0 dB (GHz) 31 30 28 22 20 18 15.7

Table 4.5: Gain and bandwidth of the CSDA vs. temperature. As shown in [24], the gain of the CSDA depends mainly on the gate transconductance of the transistor gm , the characteristic impedance Zo of 50 Ω, and the gate and drain line losses αg and αd , respectively, as shown in the following equation [24]: 2 gm Z0g Z0d sinh2 [0.5.n(αd − αg )] e−0.5.n(αg +αd ) Gp = 2 2 4 1 + ωωg 1 − ωωg sinh2 12 (αd − αg )

(4.7)

The increase of 80% of the lineic losses in TFMS and a decrease of 28% in the gate transconductance of the MOSFET, as shown previously, causes the degradation in the gain and the bandwidth of the designed CSDA. Another problem related to the common source CSDA is the Miller effect which limits the high frequency response. The Miller capacitance effect contributes also to the mismatch of the TWA sections causing the ripple in the gain [12][22], increases with the temperature as shown in Fig. 4.31.

Figure 4.31: Contribution of the passive and active devices to the degradation of CSDA performance at 250o C.

108

4.5

4.5.2

ANALYSIS OF THE DESIGNED DAS AT HIGH TEMPERATURE

Behavior of the FBCDA at high temperature

The designed CDA is measured vs. temperature (Fig. 4.32), and the results summarized in the following table.

10 9

|S21| (dB)

8 7

T=25°C

6

T=50°C

5 T=100°C

4 3

T=150°C

2 1

T=250°C

T=200°C

0 0

10

20

30

Frequency (GHz)

Figure 4.32: Measured FBCDA gain versus frequency for various temperatures. The decrease in gain and bandwidth is notable: gain and bandwidth are 6.8 dB and 27 GHz, respectively, at romm temperature and 4 dB and 12 GHz, at 250o C. Furthermore, at high temperature, the gain is not constant over the bandwidth.

Temperature o C Room temperature 50 100 150 200 250

S21 @ midband (dB) 6.8 6.2 4.3 3.6 3.2 2.7

Cut-off frequency @ 0 dB (GHz) 27 27 26 25 25 12

Table 4.6: Gain and bandwidth of the FBCDA vs. temperature.

4.5.3

Analysis and discussion

Simulations were carried out with ADS r in order to investigate the main origin of the drop in the gain and the bandwidth. The comparison is done at 25 and 250o C on the gain of the CDA. 109


The following curve shows the contribution of the losses due to the passive (TFMS), and active (FB MOSFET) devices on the gain and the bandwidth of the CDA. The effect of each contributor has been simulated separately in order to quantify the impact of each on the CDA frequency behavior. From Fig. 4.33, it is clear that the largest contribution to the gain and bandwidth degradation is due to the metallic losses of the TFMS. This is an important guideline parameter in the design of CDA for high temperature applications.

9 T=25°C

8 7

|S21| (dB)

6

FET effect

5 TFMS effect

4 3

TFMS & FET effect

2 1 0 0

5

10

15

20

25

30

35

Frequency (GHz)

Figure 4.33: Contribution of the passive and active devices to the degradation of CDA performance at 250o C.

4.6

Conclusion

SOI technology is emerging as the most mature solution for high temperature applications. Indeed, SOI MOSFETs present lower leakage currents than bulk devices at high temperature, as well as a smaller variation of threshold voltage with temperature. They are also immune to temperature-induced latchup. As a result, SOI circuits can operate at temperatures above 300o C, while bulk CMOS is usually limited to 150o C. DAs were designed in a standard 130 nm SOI PD CMOS process, with FB devices and TFMS lines. TFMS is very attractive because it keeps the amplifier performances independent on the substrate resistivity and makes the circuit layout more compact comparing to CPW or large area consumed by integrated lumped inductors. The excellent behavior of SOI CMOS circuits at high temperature suggests the use of this technology for different applications. For this reason, the behavior of the DAs 110

4.6

CONCLUSION

is investigated with respect to temperature. The results show that the losses induced in the TFMS are the main contributor to the decrease of the gain and the bandwidth of the DAs at high temperature.

111


References [1] N. Zamdmer, J. Kim, R. Trzcinski, J. O. Plouchart, S. Narasimha, M. Khare, L. Wagner, and S. Chaloux, “A 243-GHz Ft and 208-GHz Fmax 90-nm SOI CMOS SoC technology with low-power millimeter-wave digital and RF circuit capability,” Symposium on VLSI Technology. Digest of Technical Papers., pp. 98–99, June 2004. [2] D. Flandre, A. N. Nazarov, and P. L. F. Hemment, Science and Technology of Semiconductor-On-Insulator Structures and Devices Operating in a Harsh Environment, Kluwer Academic Publishers, 2005. [3] J.-P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI, Kluwer Academic Publishers, 2 edition, 1997. [4] D. Corson and P. Delatte,

“Why all the buzz about SOI ?,”

http :

//rf design.com/mag/radio why buzz soi/ , October 2003. [5] Global Watch service, “Electronics and electronic materials for harsh environments a mission to the USA,” Tech. Rep., The UK Government Department of Trade and Industry (DTI), www.faraday-advance.net/content/news/28.pdf, October 2003. [6] D. S. Jeon and D. E. Burk, “A Temperature-Dependant SOI MOSFET Model for High-Temperature Application (27o C −300o C),” IEEE Transactions on Electron Devices, vol. 38, no. 9, pp. 2101–2111, September 1991.

[7] A. A. Osman, M. A. Osman, N. S. Dogan, and M. A. Imam, “Zero-TemperatureCoefficient Biasing Point of Partially Depelted SOI MOSFET’s,” IEEE Transactions on Electron Devices, vol. 42, no. 9, pp. 1709–1711, September 1995. [8] L. Toygur, Interface Circuits In SOI-CMOS For High-Temperature Wireless Micro-Sensors, Ph.D. thesis, Department of Electrical Engineering and Computer Science Case Western Reserve University, 2004. [9] A.A. Osman and M.A. Osman, “Investigation of High Temperature Effects on MOSFET Gate Transconductance,” Proceeding of 1998 High Temperature Electronics Conference, 1998. [10] M. Dehan, Characterization and Modeling of SOI RF integrated components, Ph.D. thesis, UCL, November 2003. [11] Y. S. Lin, “Temperature dependence of the power gain and scattering parameters S11 and S22 of an RF NMOSFET with advanced RF-CMOS technology,” Microwave and Optical Technology Letters, vol. 44, no. 2, pp. 180–185, January, 20 2005. 112

4.6

CONCLUSION

[12] C. Pavageau, M. Si Moussa, A. Siligaris, L. Picheta, F. Danneville, J-P. Raskin, D. Vanhoenacker-Janvier, J. Russat, and N. Fel, “Low Power 23-GHz and 27GHz Distributed Cascode Amplifiers in a Standard 130nm SOI CMOS Process,” IEEE MTT - S International Microwave Symposium, June 11-17 2005. [13] H. Heuerman and B. Schiek, “Robust algorithms for txx network analyzer selfcalibration procedures,” IEEE Trans. on Instrumentation and measurements, vol. 43, no. 1, pp. 18–22, January 1994. [14] A. C. Reyes, S. M. El-Ghazaly, S.J. Dorn, M. Dydyk, D. K. Schroeder, and H. Patterson, “Coplanar waveguides and microwave inductors on silicon substrates,” IEEE Trans. Microwave Theory Techniques, vol. 43, no. 9, pp. 2016– 2021, September 1995. [15] S. O. Kasap, Electronic Materials and Devices, McGraw-Hill Higher Education, 1997. [16] D. Lederer and J.-P. Raskin, “Temperature dependence of RF losses in HR SOI substrates,” in Proceedings of NATO Advanced Research Workshop on science and technology of SOI structures and devices operating in harsh environment. NATO Science, April 2004, pp. 192–196, Series Elsevier. [17] D. Lederer and J. P. Raskin, “Effective resistivity of fully-processed soi substrates,” Solid-State Electronics, vol. 49, pp. 491–496, 2005. [18] B. Aspar, C. Lagahe-Blanchard, P. Paillet, V. Ferlet-Cavrois, N.Fel, C. Pavageau, J. du Port de Poncharra, and H. Moriceau, “New SOI Devices Transferred Onto Fused Silica By Direct Wafer Bonding,” 207th Electro-Chemical Symp, May 2005. [19] W. Heinrich, J. Gerdes, F. J. Schmuckle, C. Rheinfelder, and K. Strohm, “Coplanar passive elements on Si substrate for frequencies up to 110 GHz,” IEEE Trans. Microwave Theory Techniques, vol. 46, no. 5, pp. 709–712, May 1998. [20] O. Rozeau, J. Jomaah, J. Boussey, Y. Omura, and J. Lescot, “Experimental investigation of MOSFET’s and coplanar waveguides on P-type high resistivity SIMOX substrate for radio-frequency applications,” IEEE International SOI conference, pp. 27–28, October 1998. [21] T. N. Theis, “The future of interconnection technology,” IBM J. RES. DEV., vol. 44, pp. 379–390, 2000. [22] M. Si Moussa, C. Pavageau, P. Simon, F. Danneville, J. Russat, N. Fel, J.-P. Raskin, and D. Vanhoenacker-Janvier, “Behavior of a Common Source Traveling Wave Amplifier versus Temperature in SOI Technology,” 35 European Microwave Week EuMW’2005- GAAS’2005, pp. 1075–1078, October 3-7, 2005 2005. 113

[23] M. Si Moussa, C. Pavageau, F. Danneville, J. Russat, N. Fel, J-P. Raskin, and D. Vanhoenacker-Janvier, “Temperature Effect on the Performance of a Traveling Wave Amplifier in 130 nm SOI Technology ,”

IEEE Radio Frequency

Integrated Circuits Symposium, pp. 495–498, June 11-17, 2005 2005. [24] J. B. Beyer, S. N. Prasad, R. C. Becker, J. E. Nordman, and G. K.Hohenwarter, “MESFET distributed amplifier design guidelines,” IEEE Trans. Microwave Theory Techniques, vol. 32, no. 3, pp. 268 – 275, March 1984.

CHAPTER 5 OPTIMIZED DISTRIBUTED AMPLIFIERS AND OSCILLATORS 5.1

Introduction

We have shown, in the previous chapters, the design and analysis of fully integrated DAs with 130 nm partially depleted SOI technology using TFMS lines, with very good results compared to the state-of-the art, especially in terms of power consumption (Table 3.8). It has also been show that the main losses in the DAs are mainly due to the passives (TFMS lines), even if it gives us the possibility of using a low resistivity silicon substrate. In the following, using the same 130 nm SOI technology, we will focus on the optimization of the DAs: in the one hand, pointing out the power consumption, by using a Dynamic Threshold (DTMOS) transistor as an active device in our design, and enhancing the passives performances by using CPW lines, on the other hand. We will also take a benefit of using this distributed architecture to design an oscillator, which has high tuning capabilities comparing to classical oscillators.

5.2

Distributed Amplifiers using DTMOS

The Silicon-on-Insulator (SOI) CMOS technology has become a competitive technology for radio transceiver implementation of various wireless communication systems due mainly to low-power, low-cost, higher level of integrability, high performance mixed-mode circuits, etc. [1]. Power consumption constitutes one of the most important parameter in the design of the circuits dedicated for portable and wireless applications. The most usual approach for reducing power consumption is the choice of the bias point. Another promising solution is to use MOSFET with dynamic Vth named Dynamic Threshold MOS (DTMOS); it provides low Vth when the device is turned-on for high current drive, and high Vth when the device is turned-off for low subthreshold voltage [2]. In a DTMOS the body is tied to the gate, which leads to an extremely high transconductance (gm ) under very low supply voltage. For voltages higher than 0.7 V , the drain/body diode starts conducting and current limiters have to be introduced. DTMOS transistors have two main drawbacks: a larger layout area and a larger gate 115

CHAPTER 5. OPTIMIZED DISTRIBUTED AMPLIFIERS AND OSCILLATORS

capacitance [3]. However, several papers [4][5] have shown that DTMOS can exhibit very high cut-off frequencies under low bias conditions. Nevertheless, to our knowledge, SOI DTMOS architecture has not been introduced yet into the design of high speed or high frequency circuit design. With the motivation of high gain under low-power consumption, a CDA using DTMOS transistors is designed, by keeping the same architecture as before and replacing the FBMOS by DTMOS transistors.

5.2.1

DTMOS transistor

Portable applications that traditionally required a modest performance are now dominated by devices that demand a very high performance. The demand for portability of these new systems limits their battery weight and size, placing a severe constraint on their power dissipation. Thus, lower consumption that was not a concern in these systems is now becoming a critical parameter. The most common approach for reducing power is power supply scaling. However, the lower limit for threshold voltage is set by the amount of off-state leakage current that can be tolerated. It is seen that if standard MOSFET’s are used, a lower bound for power supply voltage or a larger leakage current become inevitable. To extend the lower bound of power supply to ultra-low voltages (0.6 V and below), the Dynamic Threshold Voltage MOSFET (DTMOS) was proposed [3]. The DTMOS SOI transistor is a partially depleted device with a contact between the gate and the floating body. DTMOS are fabricated using standard SOI PD CMOS processes. The floating body of the SOI MOSFET is connected to the gate using a P+ -metal contact, as shown in Fig. 5.1.

Figure 5.1: Schematic (a) top view and (b) cross section of the body contact for a DT nMOSFET. 116

5.2

DISTRIBUTED AMPLIFIERS USING DTMOS

A DTMOS is a Body Contacted SOI transistor whose Threshold Voltage is dynamically controlled by connecting the body to the gate. As the body-source voltage Vbs is controlled, there is no floating body effect, and the threshold voltage swing is maximized, improving the Ion /Iof f ratio. Nevertheless, DTMOS transistors have two main drawbacks: a much larger layout area, and a larger gate capacitance. However, The DTMOS is a good candidate for a DA because it exhibits a higher transconductance and lower output conductance compared to a FB NMOS of the same size, as shown in Fig. 5.2.

gm & gd (mS/mm)

1.2 1.0

gm DTMOS

0.8

gm FBMOS

0.6 0.4

gd FBMOS

0.2 gd DTMOS

00

0.2 0.4 0.6 0.8 Drain current (mA/mm)

1.0

Figure 5.2: gm and gd versus drain current for a 30x2x0.13 FB et DT MOS SOI transistors (@ saturation: Vds = 1.2 V ).

The DTMOS gm is larger due to the Vth reduction and the resultant increase of the gate drive. The DTMOS gd is smaller for short gate lengths, which suggests that drain currents saturate very well due to the small channel length modulation effect caused by a reduction in the drain’s electrical field. However, the DTMOS capacitances are larger due to the additional body-source/drain capacitances [5]. The main small-signal equivalent elements for FB and DTMOS are extracted and presented in Table 5.1.

DTMOS demonstrates an increase of around 15% of ft and fmax , compared to FB MOS thanks to its larger transconductance gm which cancels the increase of its parasitic capacitances.

117


SOI MOS 60x2 FB 30x2 FB 30x2 DT

Vth (V) 0.274 0.29 0.29

gm (mS) 75 40 60

gd (mS) 6.34 4.17

Cgs (fF) 170 50 60

Cgd (fF) 60 32 72

ft (GHz) 91 89 113

fmax (GHz) 83 125 150

Table 5.1: Comparison of the measured characteristics of the used FB and DT MOSFET transistors in 130 nm SOI technology.

5.2.2

Design

In the following, we design a cascode DA (CDA) using DTMOS transistors, by keeping the same architecture as before and replacing the FBMOS by DTMOS. The chip layout is shown in Fig. 5.3. Chip area is kept the same (0.75 mm2 ).

Figure 5.3: Layout of the designed CDA using DTMOS transistors. Fig. 5.4 shows simulated and measured gains obtained using the Common Source (CSDA) and two Cascode (CDA) configurations using a 30 × 2 × 0.13 FB or a

30 × 2 × 0.13 DTMOS.

As we can see, the CDA-DTMOS which uses the same passives as the CDA-FB shows already an enhancement of gain and bandwidth. An optimization of the passives, where the lengths and the widths of the gate and the drain microstrip lines were recomputed, combined to the used 30 × 2 × 0.13 DTMOS transistor allows a simulated 0 dB cut-off frequency of 69 GHz.

5.2.3


As shown in Fig. 5.5, where a comparison between both FB and DTMOS CDA is done, there is an evident enhancement of the bandwidth, but lower than predicted by 118

5.2

DISTRIBUTED AMPLIFIERS USING DTMOS

Figure 5.4: Simulated and measured gains of the Common Source and Cascode CDA with FB and DTMOS transistors. the simulations. This is due to an under-estimation of the input capacitance of the DTMOS transistor, which (as explained earlier) is higher compared to a FB transistor. An accurate modeling of the DTMOS transistor is ongoing.

10 CDA_DTMOS

S21 (dB)

8

CDA_FB

6 4 2 0 0

10


40

Figure 5.5: Measured gains of the Cascode CDA with FB and DTMOS transistors.

119


5.3

Distributed Amplifiers using CPW

Nanometer-scale CMOS on Silicon-on-Insulator (SOI) technologies benefit from parasitic junctions reduction and sharp subthreshold slope for achieving high speed and high gain devices while reducing voltage and power consumption. SOI technology is therefore a good candidate for the ever growing market of high performance, low cost microprocessor, networking and DSP applications. These abilities together with very high Ft and Fmax cutoff frequencies of SOI transistors, enable the joint integration of microwave circuits and high-speed digital functions. But high losses in silicon transmission lines is SOI technologies main limiting factors, reducing high frequencies performances of microwave circuits. Distributed amplifiers (DA) architecture achieves multi-decades flat gain and is an interesting benchmark reflecting both transistors and transmission lines performances of a semiconductor technology.

As previously said, one of the main challenge in silicon process is not anymore high performance transistors but ultra low loss transmission lines for achieving higher frequency and better noise performances. Transmission lines can be implemented using microstrip lines (TFMS) configuration or coplanar waveguide configuration (CPW). Microstrip lines, with ground plane on the first layer of metal and signal on the last layer of metal can be used. However, since the last layer of Cu metal is only few µm from the Si substrate, the integration of low-losses 50 Ω microstrips is difficult. In the coplanar waveguide (CPW) configuration, the distance between the ground planes and the signal line is a free parameter (Fig. 5.6). The drawback of CPW is that the signal is not any more shielded from the substrate, and if the signal line is too wide, substrate losses are high. The signal line width can be used to minimize conductor losses, while the signal-to-ground spacing controls the characteristic impedance Zo [6] [7].

Electric field Magnetic field

Figure 5.6: CPW with its electromagnetic field.

120

5.3

5.3.1

DISTRIBUTED AMPLIFIERS USING CPW

Design

Two 4-stage cascode DAs with loss compensation technique have been fabricated and measured on 130 nm SOI process [8]. They make use of either conventional FB or BC devices, and CPW implemented on copper-6 and alucap layers. After validating the transistors’ and transmission line models with the measures done for the previous designed DAs, simulations were carried out for CPW as transmission lines, with an improvement of the gain and the bandwidth. Fig. 5.7 shows power gain and noise figure for DAs using TFMS on copper-6 layer only, and TFMS or CPW lines on copper-6 and Alucap layers. Table 5.3 gives a summary of these data. As a figure-of-merit, we investigated gain bandwidth product (GBW) showing gain and bandwidth dependency. As summarized in Table 5.2, there is a twofold increased GBW product for DA using TFMS and CPW lines on copper-6 and Alucap layers, compared with the DA using TFMS on copper-6 layer only. The use of lower losses lines allows attenuation reduction in gate and drain lines. Furthermore, DA with CPW lines achieve a noise figure of 6 dB at 20 GHz instead of 7.8 dB for the DA with TFMS on copper-6 only.

16

TFMS M6 (1) CPW M6/ALU (2) TFMS M6/ALU (2)

10

14 12

0

10

-5

8

-10

6

|S21| (dB)

5

-15

NF (dB)

15

4 0

10

20

30 40 50 60 Frequency (GHz) (1) Measured data, (2) Simulated data

70

Figure 5.7: Measured and simulated power gain and noise figure of FB-DA with different transmission lines layout.

121

CHAPTER 5. OPTIMIZED DISTRIBUTED AMPLIFIERS AND OSCILLATORS Transmission lines charac.

TFMS (Cu-6) (W = 2 µm)

TFMS (Cu-6+Al) (W = 4.4 µm) BC

CPW (Cu-6+Al) (W = 10 µm) (G = 11.7 µm) BC

CPW (Cu-6+Al) (W = 10 µm) (G = 11.7 µm) FB

Transistors (30 × 2 × 0.13) Design Att. coefficient @ 20 GHz (dB) ft /fmax (GHz) Gain (dB) f−3dB (GHz) GBW (GHz) S11 /S22 (dB) Area (µm)

BC Measured 1

Simulated 0.75

Simulated 0.3

Simulated 0.3

63/76 5.4 ± 1.4 21 40 < −8/ < −8 1500 × 500

63/76 6.0 ± 0.3 41 82 < −5/ < −9 1060 × 710

63/76 9.6 ± 0.3 38 114 < −10/ < −6 2140 × 750

89/125 9.6 ± 0.2 42 126 < −10/ < −6 2180 × 675

Table 5.2: Measured and simulated data of 4-stage cascode DAs using different transmission lines layout.

5.3.2


The CPW-DA using BC and FB PD SOI MOSFET transistors were designed by C. Pavageau from IEMN during his PhD thesis [9], giving the following layout (Fig 5.8). On-wafer measurements were performed using an Agilent 8510 network analyzer operating up to 110 GHz for the CDA with Floating-Body devices. The measured results are presented in Fig.5.9 showing measured S-parameters at Vdd = 1.8 V with a bias current of 42 mA. Vdd was increased, compared to the previous run, in order to increase the flatness of the gain [9]. Input and output return losses are better than −8 dB and −6 dB up to 40 GHz, respectively.

The CDA using CPW lines exhibits a gain of around 7 dB and 0 dB cut-off frequency of 50 GHz. There is a clear enhancement of the bandwidth. The DA with Body-Contacted devices has an average gain of 7 ± 0.5 dB from 1 to

43 GHz. Input and output return losses are better than −8 dB and −6 dB up to

40 GHz, respectively.

There is a clear enhancement of the bandwidth (twofold increase) because of the diminution of the passives losses (as demonstrated in Chapter 4), as summarized in Table 5.3.

122

5.3


Drain line

Vbias RF pad

Output RF pad

Cd

Input RF pad

Cg

Cdec

Gate line Drain line

Bias transmission line

Connexion gnd-gnd (Metal -1) T2 Cdec T1

Gate line

(a)

(b) Figure 5.8: (a) Layout and (b) Chip microphotograph of the CDA with CPW transmission lines (675 µm × 2180 µm).

123


Figure 5.9: Simulated and measured S parameters of the designed FB CDA using CPW transmission lines.

124

5.3

Transistors Lines Fmax (GHz) GBW (GHz) Gain (dB) BW (GHz) Area (mm2 ) Pdc (mW)


FB TFMS Wo Al 125 59 7.1 ± 1.1 1 - 26 0.75 55

FB CPW on HR Si 125 91 7.1 ± 1.6 1 - 40 1.5 75

BC CPW on HR Si 76 98 7.1 ± 0.5 1 - 43 1.75 75

Table 5.3: Measured data of 4-stage cascode DAs using TFMS and CPW different transmission lines.

125


5.4

Distributed Oscillation

Although it is possible to design LC oscillators on a silicon substrate up to 10 GHz, it becomes excessively hard to achieve a wide tuning range and good phase noise as the frequency of operation approaches fmax of transistors [10]. This is mainly due to the trade-off between the self-resonance frequency and the quality factor, Q, of the inductors and varactors. This trade-off becomes prohibitive as the operation frequency increases. This limitation has made it more attractive to pursue alternative approaches, such as distributed oscillators. A 4 GHz distributed oscillator was demonstrated using four discrete pHEMTs and microstrip lines on a printed circuit board [11]. In 1999, Kleveland et al. showed an integrated (with off-chip termination and bias) distributed oscillator operating at 17 GHz without any tuning capability using a 0.18 µm CMOS technology [12]. A 10 GHz distributed oscillator was also designed in a 0.35 µm BiCMOS process technology using only CMOS transistors by Wu et al. in 2001 [13].

5.4.1

Distributed Oscillators

The oscillator in communication and measurement systems, be they radio, coaxial, cable, microwave, satellite, radar or optical fiber, defines the reference signal onto which modulation is coded and later demodulated. The phase noise and power consumption in such oscillators are central and setting the ultimate of modern communications [14]. The main specification on the design of oscillators are [15]: • Center frequency: the output frequency fo of the oscillator with the control voltage at its center value.

• Tuning range: the range of output frequencies that the circuit oscillates at over the full range of the control voltage.

• Tuning sensitivity: the change of output frequencies per unit change in the control voltage, typically expressed in [Hz/V].

• Spectral purity around the oscillation: in the frequency domain, the spectral purity is specified in term of phase noise; it is surely the most important specification in the design of oscillators. • Load pulling: the sensitivity of the output frequency to changes in its output load; this specification depends strongly on the output stage in the oscillator.

126

5.4

DISTRIBUTED OSCILLATION

• Supply pulling: the sensitivity of the output frequency to changes in the power supply, expressed in [Hz/V].

• Power consumption: the DC power drained by the oscillator. • Output power: the power delivered by the oscillator to a specified load. • Harmonic suppression: specifies how much smaller the harmonics of the output spectrum are compared to the fundamental component, typically expressed in [dBc].

5.4.1.1

Basic Phase Noise Theory

The output spectrum of oscillators is ideally a Dirac function. In practical cases, a spreading of the signal occurs due to the action of noise. Noise affects both amplitude and phase of the signal. The output amplitude modulation may be corrected by automatic amplitude control loops, but phase noise cannot be corrected. Indeed, an oscillator is an autonomous system for which no phase reference does exist. Phase noise quantifies the signal broadening. There are, at present, two separate but closely related models of phase noise of oscillator output. The first is a collection of ideas put together by Leeson [16]. It will be referred to here as Leeson’s model. Noise prediction using Leeson’s model is based on the time-invariant properties of the oscillator such as resonator, feedback gain, output power, and noise figure. The second, an improvement on Leeson’s model, was proposed by Lee and Hajimiri [17] [18]. Lee and Hajimiri’s model is based on the timevarying properties of the oscillator current waveform and the resultant implications on phase noise production. The phase noise output of an oscillator is measured as power relative to the power output at the center frequency. It is referred to in units of decibels below the carrier per hertz (dBc/Hz). The general phase noise output spectrum of an oscillator consists of three distinct sections located in the sidebands of the carrier frequency. Fig. 5.10 shows a single sideband (SSB) view of the oscillator phase noise for simplicity. Immediately surrounding the carrier frequency there exists a region of noise which decays as 1/f 3 . At some frequency offset called the 1/f 3 − 1/f 2 corner frequency, the noise spectrum changes to a 1/f dependence. The

1/f 2 region continues on to the phase-noise floor of the circuit. The noise floor of the circuit is a result of thermal and shot noise sources. The noise floor exists across all frequencies, even in the 1/f 2 and 1/f 3 regions. The relative powers associated with each section depend on each section’s corner frequency and the noise floor level [19].

127

Power Spectral Density


Flicker FM noise , 1/f³

White FM noise , 1/f² Flicker PM noise , 1/f White PM noise

Frequency offset from carrier

Figure 5.10: SSB oscillator phase noise output spectrum.

The single sideband-to-carrier ratio (SSCR) is a suitable measure of the phase noise (Fig. 5.11). It corresponds to the ratio between the output noise power in a 1-Hz bandwidth at the frequency offset ∆ω from the carrier and the power of the carrier:

L(∆ω) = 10log

Psideband (ωo + ∆ω, 1Hz) Pcarrier

(5.1)

Figure 5.11: Definition of Phase Noise. where Psideband (ωo + ∆ω, 1 Hz) represents the power of a 1 Hz bandwidth contained in a lateral band of the output spectrum. This power is measured at a ∆ω shift from the center frequency ωo . L(∆ω) is usually expressed in [dBc/Hz], i.e. decibels in a 1 Hz bandwidth relative to the carrier. Note that both amplitude and phase noise are included in 5.1. The relation 5.1 also relates an important trade-off: the higher the signal magnitude, the lower the phase noise, but the higher the amplitude also means the higher the power consumption in most practical realizations [15].

128

5.4

5.4.1.2


Topology

A distributed amplifier can be placed in a feedback loop to form an oscillator. To this end, the total delay of the inverting amplifier must translate to a phase shift of 180o at the frequency of interest fosc (Fig. 5.12). This oscillator uses the delay introduced by the distributed amplifier to sustain electrical oscillation by continuous amplification of the signal around a loop. The oscillation frequency is determined by the round trip time delay, i.e., the time it takes the wave to travel through the transmission lines and get amplified by the transistors [20]. In the following, we use a 130 nm SOI technology with thin film microstrip (TFMS) lines on a standard resistivity substrate to design the cascode distributed amplifier and oscillator using floating body (FB) transistors.

Vdrain Zd

Port 3

Port 4 Vgate Zg

Port 1

Feedback path

Port 2

(Oscillator only)

Figure 5.12: Distributed amplifier and oscillator schematic. As for a distributed amplifier, the performance of distributed oscillators is constrained by five effects. First, the limited supply voltage places an upper bound on the number of stages and hence the achievable voltage gain. Second, resistive losses in the input transmission lines gradually attenuate the signal applied to the gates of the transistors, leading to lower signal amplitude for the stages near the far end. Third, as in passive transmission lines, resistive losses limit the bandwidth in both the input and the output networks. Fourth, the output resistance of the transistors raises the loss in the output transmission line. Fifth, the Miller effect of each transistor’s gate-drain overlap capacitance becomes more significant as the wave travels toward the far end [10]. The chip microphotograph of the designed cascode distributed amplifier (CDA) is shown in Fig. 5.13 and the measurements results of the module and the phase of |S21 | are given in Fig. 5.14. 129


Drain Line

RF pad

DC bias

Cd

Output RF pad

Input RF pad Gate Line

T2

Cg

Drain line Biasing of T2’s Gate

Cdec

Lsd

Lcg

Gate line

T1

Figure 5.13: Chip microphotograph of the designed CDA. T1 : common source transistor, T2 : common gate transistor, Cdec : decoupling capacitor.

S21 (dB)

10 0 -10 -20 -30 0

10


40

0

10


40

Phase (deg)

180 90 0 -90

-180

Figure 5.14: S21 module and phase of the designed CDA at room temperature.

130

5.4

5.4.1.3


Design and measurements

In the CDO’s design, the feedback connection is critical for the operation of the distributed oscillator. The frequency of a distributed oscillator (DO) is controlled by the delay time of its transmission lines, and tuning can be achieved by adjusting the DC bias of the gate line by introducing an AC coupling capacitor, Cc , between the drain and gate lines [13]. This capacitor allows tunning the gate bias without disturbing the supply voltage Vdd (Fig. 5.15).

Figure 5.15: Layout of the designed CDO. We have started the design of the oscillator by connecting the output of our CDA back to the input, taking the physical distance between the output (Port 4) and the input (Port 1) (Fig. 5.12)as a starting point for our S parameters simulations on ADS r . After that, the feedback transmission line dimensions were optimized using ADS r to obtain a DO with an oscillation frequency of 10 GHz (Fig. 5.16).

m1

10

m1

S11 (dB)

5

F= 10.00GHz S11=9.400 dB

0 -5 -10 -15

0

10

20

30

40

50

Frequency (GHz)

Figure 5.16: S parameters simulations of the CDO.

131


With the obtained design and using Harmonic Balance simulations with ADS r for the analysis of the oscillator, a phase noise of around −112 dBc/Hz at 1 M Hz is

predicted. This is a good indication about the level of the phase noise that we have to expect, but we have to keep in mind that these simulations do not take into account the transistors’ noise, and the model used for the passives does not take into account the quality of the silicon substrate in term of resistivity. The final design has a loop length for the oscillator is 2 mm, increasing the chip area to 0.67 × 1.36 mm2 with testing pads (Fig. 5.15). The oscillator is tested by connecting the bias terminal to a bias-T and the output terminal directly to a spectrum analyzer (Fig. 5.17).

Figure 5.17: Power Spectrum of the designed CDO: first harmonic at 10 GHz. As shown in Fig. 5.18, the CDO exhibits an output power of 4.76 dBm at 10.10 GHz for 2.5 V supply voltage. On-wafer measurements were performed with the Agilent spectrum analyzer HP E4440A. A phase noise of around −130 dBc/Hz at 1 M Hz offset from a 10 GHz

carrier is achieved on 2.5 V DC supply (Fig. C.3). This value is confirmed by the

measurements done with an HP8562A spectrum analyzer (details of the setup are provided in appendix C). The difference between the measurements and the simulation can be due to the better quality of the silicon substrate used, and was not taken into account during the simulations. Indeed, it has already been demonstrated in several published papers [21, 22], that the use of high resistivity silicon substrate improves the phase noise of oscillators and VCOs. 132

5.4


Figure 5.18: Detailed Power Spectrum of the designed CDO.

Calculation shows that one can change the oscillation frequency by choosing a smaller input capacitance for the transistor, but the worst phase noise performance is predicted at the highest oscillation frequency. On the other hand, there will be more noise sources when we increase of the number of stages, but each will contribute lower to the noise amplitude due to its smaller transconductance. Similarly, the oscillator with fewer stages will have fewer noise sources, but each one with greater relative amplitude. Therefore, it is expected that the phase noise from two DOs will give about the same performance despite the different number of stages employed [23]. In the following, we will examine the tuning range capabilities of the designed CDO. As shown in table 5.4, a tuning range of 14% (9.9 − 11.5 GHz) can be obtained

adjusting the DC biases, as explained earlier.

Vgs (V) Vcasc (V) Vdd (V) Oscillation Frequency (GHz)

0.65 2.5 2.5 9.9

0.60 2.5 2.5 10

0.80 2.1 1.5 10.1

0.75 2.1 1.6 10.3

0.75 1.9 1.6 10.5

0.70 2.1 2.5 10.8

0.75 1.9 2.5 11.5

Table 5.4: Tuning of the SOI CDO. Based the design of a cascode distributed amplifier, a 10 GHz CMOS SOI cascode DO is proposed. To the authors’ knowledge, this is the first distributed oscillator designed on SOI technology. The frequency of the CDO is controlled by the time delay of its transmission lines. This delay can be changed in several different ways. One approach is to adjust the delay of the line by changing its capacitive loading, and this 133


(a)

(b) Figure 5.19: Phase Noise of the designed CDO measured with the HP E4440A spectrum: (a) Phase Noise curve, (b) the Marker Noise.

134

5.4


is achieved by adjusting the DC bias of the gate line. The CDO demonstrates very interesting characteristics comparing to other DOs previously published on CMOS process (Table 5.5).

Techno.

Oscillation Frequency (GHz) Phase Noise (dBc/Hz@1MHz) Area (mm2 ) Vdd (V) Pdc (mW) Output power (dBm)

0.18µm Bulk CMOS [24] 13.3

0.18µm Bulk CMOS [12] 16.6

0.35µm Bulk BiCMOS [13] 10.2

This work CDO

−117

−110

−114

−130.35

0.2 × 1.5 1 26 -

0.3 × 1.5 1.3 52 -3.5

1 × 1.4 2.5 35 -8.83

0.67 × 1.36 2.5 156 4.76

10

Table 5.5: State-of-the art DO’s.

5.4.1.4

High temperature behavior

For high temperature measurements, the same setup is used as for the distributed amplifiers. The die is heated from ambient to 250o C, and for each temperature plateau (50, 100, 150, 200 and 250o C), we measure the output power spectrum and the consumption, in order to see the tendencies versus high temperatures. The first results are summarized as shown in Table 5.6. There is a slight decrease of the performances till 200o C, even if we note a little shift in the oscillation frequency and a drop of the level of the output power At 250o C.

Temperature o C 25 50 100 150 200 250

Oscillation frequency (GHz) 10 10.05 9.88 9.59 9.34 9.26

Output power (dBm) 4.76 4.74 3.25 0.85 -2.53 -61.64

Consumption (mW ) 156 150.75 143.00 131.75 121.25 107.50

Table 5.6: CDO characteristics’ vs. temperature.

135


5.5

Conclusion

Different distributed amplifiers and oscillators have been designed using different transistors and transmission line topologies, with 130 nm partially depleted SOI technology using TFMS. By tying the gate and the body of an SOI MOSFET together, a Dynamic Threshold Voltage MOSFET (DTMOS) is obtained. DTMOS has the theoretically ideal subthreshold swing and higher carrier mobility than the standard MOSFET. Furthermore, DTMOS threshold voltage drops as the gate voltage is raised, resulting in a much higher current drive than a conventional bulk or SOI MOSFET. As the AC and RF experimental and simulation results demonstrate, DTMOS is a good candidate for very low voltage operation. After showing the important gain in using CPW lines on HR Si substrate instead of TFMS, a CDA using CPW lines was designed and measured. The obtained results demonstrated the good enhancement in the gain and the bandwidth, the only drawback being the increase of the layout area. A 10 GHz CMOS SOI CDO is designed, based on the designed CDA. The frequency of the DO is controlled by the time delay of its transmission lines. This delay can be changed in several different ways. One approach is to adjust the delay of the line by changing its capacitive loading, and this is achieved by adjusting the DC bias of the gate line.

136

5.5

CONCLUSION

References [1] J.-P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI, Kluwer Academic Publishers, 2 edition, 1997. [2] C. Wann, “channel Profile Optimization and Device Design for Low-Power HighPerformance Dynamic-threshold MOSFET,” IEEE IEDM, pp. 113 – 116, December 1996. [3] F. Assaderaghi, D. Sinitsky, S. A. Parke, J. Bokor, P. K. Ko, and Chenming Hu,

“Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage

VLSI,” IEEE-Transactions-on-Electron- Devices, vol. 44, no. 3, pp. 414–422, March 1997. [4] M. Dehan and J.-P. Raskin, “Dynamic threshold voltage MOS in partially depleted SOI technology: a wide frequency band analysis,” Solid-State Electronics, vol. 49, pp. 67 – 72, January 2005. [5] T. Tanaka, Y. Momiyama, and T. Sugii,

“Fmax Enhancement of Dynamic

Threshold-Voltage MOSFET (DTMOS) Under Ultra-Low Supply Voltage,” IEEE IEDM, pp. pp. 423 – 426, December 1997. [6] J-O. Plouchart, J. Kim, N. Zamdmer, L-H. Lu, M. Sherony, Y. Tan, R. A. Groves, R. Trzcinski, M Talbi, A. Ray, and L. F. Wagner, “A 491-GHz Traveling-Wave Amplifier in a Standard 0.12-m SOI CMOS Microprocessor Technology,” IEEE Journal of Solid State Circuits, vol. 39, no. 9, pp. 1455–1461, September 2004. [7] C. H. Doan, S. Emami, A. M. Niknejad, and R. W. Brodersen, “MillimeterWave CMOS Design,” IEEE Journal of Solid State Circuits, vol. 40, no. 1, pp. 144–155, January 2005. [8] C. Pavageau, M. Si Moussa, A. Siligaris, L. Picheta, F. Danneville, J-P. Raskin, D. Vanhoenacker-Janvier, J. Russat, and N. Fel, “Low Power 23-GHz and 27GHz Distributed Cascode Amplifiers in a Standard 130nm SOI CMOS Process,” IEEE MTT - S International Microwave Symposium, June 11-17 2005. [9] C .Pavageau, Utilisation des technologies MOS avances pour des applications en gamme millimtriques, Ph.D. thesis, IEMN - Lille - FRANCE, Decemeber 2005. [10] B. Razavi, “The Role of Monolithic Transmission Lines in High-Speed Integrated Circuits,” http://web.doe.carleton.ca/courses/97578/topic7&8/, 2002. [11] L. Divina and Z. Skvor, “The distributed oscillator at 4 GHz,” IEEE Trans. Microwave Theory Techniques, vol. 46, no. 12, pp. 2240–2243, December 1998. [12] B Kleveland, C. H. Diaz, D. Vook, L. Madden, T. H. Lee, and S. S. Wong, “Exploiting CMOS Reverse Interconnect Scaling in Multigigahertz Amplifier and 137


Oscillator Design,” IEEE Journal of Solid State Circuits, vol. 36, no. 10, pp. 1480–1488, October 2001. [13] H. Wu and A. Hajimiri, “A 10 GHz CMOS Distributed Voltage Controlled Oscillator,” Proc. of IEEE Custom Integrated Circuits Conference, pp. 581–584, May 2000, http://www.its.caltech.edu/ leectr/workshop/hajimiri1.pdf. [14] J. Everard, Fundamentals of RF Circuit Design, John Wiley & Sons, 2001. [15] B. Parvais, Nonlinear Devices Characterization and Micromachining Techniques for RF Integrated Circuits,

Ph.D. thesis, Université catholique de Louvain,

September 2004. [16] D. B. Leeson, “A simple model of feedback oscillator noise spectrum,” Proceedings of the IEEE, pp. 329–330, February 1966. [17] T. H. Lee and A. Hajimiri, “Oscillator phase noise: A tutorial.,” IEEE Journal of Solid State Circuits, vol. 35, no. 3, pp. 326–336, March 2000. [18] A. Hajimiri and T. H. Lee, “A general theory of phase noise in electrical oscillators,” IEEE Journal of Solid State Circuits, vol. 33, no. 2, pp. 179–194, February 1998. [19] D. S. M. Steinbach, “Oscillator Phase Noise Reduction Using Nonlinear Design Techniques,” M.S. thesis, Virginia Polytechnic Institute and State University, 2001. [20] A. Hajimiri, “Distributed Integrated Circuits: Wideband Communications for the 21st Century,”

http://www.eas.caltech.edu/engenious/win03/hajimiri.pdf,

2003. [21] J. Kim, J-O. Plouchart, and N. Zamdmer, “Design and Manufacturability Aspect of SOI CMOS RFICs,” IEEE 2004 Custon Integrated Circuits Conference, pp. 541–548, 2004. [22] J. Kim, J-O. Plouchart, N. Zamdmer, M. Sherony, Y. Tan, M. Yoon, R. Trzcinski, M. Talbi, J. Safran, A. Ray, and L. Wagner, “A Power-Optimized WidelyTunable 5-GHz Monolithic VCO in a Digital SOI CMOS Technology on High Resistivity Substrate,” International Symposium on Low Power Electronics and Design, pp. 434–439, August 2003. [23] J. Zhang, H. Mei, and T. Kwasniewski, “Prediction of Phase Noise in CMOS Distributed Oscillators,” Proceedings of SBMO/IEEE MTT-S IMOC, pp. 157– 162, 2003. 138

[24] E. C. Park and E. Yoon, “A 13 GHz CMOS Distributed Oscillator Using MEMS Coupled Transmission Lines for Low Phase Noise,” IEEE Int. Solid-State Circ. Conf., February 2004, Paper MP 16.8.


140

CHAPTER 6 CONCLUSION

Broadband distributed amplification is traditionally considered a domain for IIIV technologies. This is partially due to the inherent higher operating frequency of GaAs- and InP-based devices compared to their silicon counterparts; moreover, the semi-insulating nature of III-V substrates facilitates the realization of low-loss transmission lines and inductors, which are essential for the design of a distributed amplifier. Distributed amplifiers (DAs) are good candidate to achieve amplification over very broad bandwidths, as ultra wide band (UWB) transceivers, high speed applications and optical communications. The demonstration of SOI CMOS as a viable alternative to the implementation of low-cost monolithic microwave integrated circuits (MMIC) has generated considerable interests in the development of CMOS DAs. Power consumption is a major concern for high-performance digital systems and portable applications. The most efficient technological approach for reducing power consumption is power-supply voltage (Vdd ) scaling. For this purpose SOI devices bring their unique inherent advantages over bulk devices: lower junction capacitance, lower junction leakage, no latchup, lower sensitivity to temperature variation, and full dielectric isolation. The frame of this work was the evaluation of the issues of design and modeling of DAs on a commercially SOI CMOS technology. The purpose was to investigate the advantages of a standard 130 nm SOI CMOS process. Indeed, this technology has already shown good performances for digital applications compared to bulk CMOS technology. At nanometer-scale, SOI CMOS transistors exhibit very high cut-off frequencies, enabling the design of millimeterwave integrated circuits and therefore the joint integration of microwave circuits with low frequency analog and high-speed digital functions for SoC applications. However, high losses in passive components remain the main limiting factor for microwave applications with CMOS technologies. The analysis of the performances of this technology for microwave applications beyond 20 GHz was carried out by designing DAs in collaboration with IEMN. It was demonstrated that using a cascode topology is mandatory to achieve a flat 141

CHAPTER 6. CONCLUSION

gain on a wide band. This is due to the fact that the MOSFET transistors deeply suffer from high Miller effect, which limits the amplifier’s high-frequency response. Despite high losses in transmission lines reducing achievable gain and bandwidth, measured performances show the interest in using SOI CMOS for microwave applications, especially in term of power consumption. Because of the passives losses, the behavior of both transmission line topologies, TFMS and CPW, versus frequency and silicon substrate resistivity was presented and compared. It has been clearly shown that CPWs made on high resistivity SOI exhibits better performance than TFMS, because CPW structures enable using wider lines to achieve the same characteristic impedance which leads to reduced metallic losses. In both structures, the losses are dominated by the conductor losses. However, TFMS allows the use of standard resistivity substrate because the back ground plane shields the Silicon substrate. TFMS can then be an interesting topology if the losses can be lowered to the same level than CPW made on high resistivity SOI.

State-of-The-Art Fig. 6.1 gives a summary of the performances achieved by our designs and a comparison with other state-of-the-art cascode distributed amplifiers in either bulk or SOI CMOS technologies. A particular attention is paid to gain and bandwidth performances in respect to active devices performance and passives technology. The 130 nm SOI CMOS DA with CPW lines exhibit higher performances in terms of bandwidth, gain and power consumption than previously reported in 180 nm bulk CMOS technology. The 120 nm SOI CMOS DA from [1][2] achieve the best performances in terms of bandwidth and gain, but it should be mentioned that these designs use in fact aggressive gate length shrinkage, with 60 nm gate length devices, leading to higher Ft /Fmax cut-off frequencies and wider operating bandwidth. Our designs with CPW lines achieve fairly good performances compared to other designs in more advanced SOI technology, if we consider the gate length of active device and the power consumption.

142

143

Figure 6.1: State-of-the art of cascode distributed amplifiers in CMOS process.

FT/Fmax (GHz)

Topology / Area

Unity gain cutoff frequency (GHz)

Operation BW (GHz)

Gain (dB)

Vdd (V)

PDC (mW)

180 nm Bulk CMOS 6M, Inductors – Liu et al.

70/58

3 Stg, 1.35 mm²

23

0.1-22

7.3±0.8

1.3

52

180 nm Bulk CMOS 6M-Aluminium, CPW – amaya et al.

62/55

4 Stg, 1.6 mm²

25

2-24

5±2

3.3

68.1

180nm Bulk CMOS MS – Shigematsu et al.

51/100

8 Stg, 3.3 mm²

39

1-37

4±1

n.a.

140

180nm Bulk CMOS CPW – Lu et al.

n.a.

8 Stg, 0.8 mm²

34

2-32

8±1

2.2

97

9 Stg 1.3 mm²

90

5-90

11±1.2

2.5

210

7 Stg 1.05 mm²

86

4-86

7.8±1.3

2.6

130

5 Stg 0.8 mm²

91

4-91

4±1.2

2.6

90

Technology Bulk CMOS

SOI CMOS 120 nm SOI CMOS 8M-copper, CPW – Kim et al. 120 nm SOI CMOS 8M-copper, CPW – Plouchart et al.

196/230 Lgate = 60nm

120 nm SOI CMOS 8M-copper, CPW – Plouchart et al. 90 nm SOI CMOS 8M-copper, MS – Plouchart et al.

147/150

4 Stg 0.3 mm²

70

10-59

9.7±1.6

2

132

130 nm SOI CMOS 6M-copper, TFMS

63/76 (BC)

4 Stg 0.75 mm²

23

1-20

5.4± ±1.4

1.4

58

130 nm SOI CMOS 6M-copper, TFMS

89/125 (FB)

4 Stg 0.75 mm²

27

1-26

7.1± ±1.1

1.4

57

130 nm SOI CMOS, 6M-copper, CPW on high resistivity

63/76 (BC)

4 Stg 1.75 mm²

47

1-43

7± ±0.5

1.8

75

130 nm SOI CMOS, 6M-copper, CPW on high resistivity

89/125 (FB)

4 Stg 1.5 mm²

51

1-40

7± ±1.6

1.8

75


Two 4-stages cascode distributed amplifiers have been first manufactured with both Floating Body and Body Contacted MOSFET and TFMS line on metal 6 layer having losses of 1 dB/mm at 20 GHz. The distributed amplifier with Floating-Body devices shows a measured gain of 7.1 ± 1.1 dB and a unity-gain cutoff frequency

of 27 GHz for a moderate power consumption of 58 mW . With the availability of high resistivity substrates (1 kΩ.cm) enabling low loss CPW transmission line, dis-

tributed amplifiers have been manufactured with the same architecture and using both Floating-Body and Body-Contacted devices. Measured performances exhibit a twofold increase of the bandwidth with a gain of 7 ± 1.6 dB, a unity-gain cutoff frequency of 51 GHz for a power consumption of 75 mW for the distributed amplifier

with Floating-Body devices. Fig. 6.2 compares the gain-bandwidth product (GBW) of published DAs, showing a linear increase as a function of stage number for the 5-stage, 7-stage and 9-stage in a 120 nm SOI process. GBW versus the number of stages is a good factor-of-merit for DAs. The 4-stage 130 nm SOI DA with TFMS lines on copper-6 layer exhibits lower performances compared to other published DAs with a GBW of 59 GHz, due to high losses in transmission lines. Using CPW on high substrate resistivity silicon substrate allows to expend the GBW to 98 GHz GBW, which are good performances

G BW (G Hz)

for a 130 nm SOI process.

Best-fit line (for comparison)

300 200

120 nm IBM CPW

120 nm IBM CPW

130 nm STM CPW on HR

120 nm IBM CPW

100 130 nm STM TFM S

0 3

5

7 9 Number of stages

11

Figure 6.2: Comparison of measured data and other published results with cascode architecture in SOI CMOS process. Another issue is the high temperature applications. Indeed, SOI technology is emerging as the most mature solution for high temperature applications. Indeed, SOI circuits can operate at temperatures above 300o C, while bulk CMOS is usually 144

limited to 150o C. The excellent behavior of SOI CMOS circuits at high temperature suggests the use of this technology for different applications. For this reason, the behavior of the DAs is investigated with respect to temperature. The results show that the losses induced in the TFMS are the main contributor to the decrease of the gain and the bandwidth of the DAs at high temperature. In the end, a new series of DAs, using transmission lines with lower losses were designed in IEMN. Performances simulations and measurements show a significant improvement with a twofold gain-bandwidth product increase for the distributed amplifier using a CPW lines on high resistivity substrate. Based on the “distributed architecture”, a distributed oscillator was designed to see the benefit of this design technique on the performances of the oscillator. A 10 GHz CMOS SOI CDO is designed, based on the designed CDA, with 130 nm partially depleted SOI technology using TFMS, where the frequency of the DO is controlled by the time delay of its transmission lines. Performances achieved by our designs demonstrate the ability of standard 130 nm SOI CMOS process for millimeter-wave operations. Because SOI CMOS process achieves high speed while reducing the overall power consumption, it is well suited for the ever growing high-speed microprocessor market and the joint integration of microwave circuits together with high-speed DSP functions. The obtained results demonstrate also the feasibility and practical applicability of different passive structures in circuits design for both room and high temperature applications on SOI technology. To reduce the attenuation coefficient of TFMS lines, the width and the thickness of the conductor must be increased, but the capacitance between the conductor and the ground plane must be kept constant ensuring the same characteristic impedance. To achieve this goal, the thickness of the dielectric layer must be increased, or low-k dielectric must be used instead of silicon dioxide. These solutions are in agreement with the tendencies of semiconductor industries. Indeed, more and more metal levels are used, allowing a thicker isolator layer between the conductor, made with the top metal layer, and the ground plane. Furthermore, low-K dielectric will be used as insulator between the different metal layers to reduce the capacitive coupling between metal lines.

145


References [1] J-O. Plouchart, J. Kim, N. Zamdmer, L-H. Lu, M. Sherony, Y. Tan, R. A. Groves, R. Trzcinski, M Talbi, A. Ray, and L. F. Wagner, “A 491-GHz Traveling-Wave Amplifier in a Standard 0.12-m SOI CMOS Microprocessor Technology,” IEEE Journal of Solid State Circuits, vol. 39, no. 9, pp. 1455–1461, September 2004. [2] J. Kim, J.-O. Plouchart, N. Zamdmer, R. Trzcinski, R. Groves, M. Sherony, Y. Tan, M. Talbi, J. Safran, and L. Wagner, “A 12 dBm 320 GHz GBW Distributed Amplifier in a 0.12 µ m SOI CMOS,” IEEE Int. Solid-State Circ. Conf., pp. 476–477, February 2004.

146

APPENDIX A GAIN FORMULA OF A DISTRIBUTED AMPLIFIER

A.1

What are the differences between power gain, transducer gain, available gain, and insertion gain?

• Power gain is the ratio of the power delivered to an arbitrary load (PdL ) to the power delivered to the network by the source (Pds ). It is a function of the load

reflection coefficient (ΓL ) and the S-parameters of the network. It is independent of source reflection coefficient. This can be expressed as shown in the following formula: P ower Gain Gp =

PdL Pds

(A.1)

• Transducer gain is the ratio of the power delivered by a network to a load (PdL ) to the power available from the source (Pas ). Transducer gain is a function of the

source and load reflection coefficients and the network S-parameters. This can be expressed as shown in the following formula: T ransducer Gain Gt =

PdL Pas

(A.2)

• Available gain is the ratio of the power available at the output of a network (Pao ) to the power available from the source the source (Pas ). Available gain is

a function of the network S-parameters and the source reflection coefficient (Γs ). It is independent of the load reflection coefficient (Γl ). This can be expressed as shown in the following formula: Available Gain Ga =

Pao Pas

(A.3)

• Insertion gain is the ratio of the power delivered to a load (PdL ), with a device

inserted between the source and the load, to the reference power of the source connected directly to the load (Pr ). This can be expressed as shown in the

following formula: Insertion Gain Ga =

I

PdL Pr

(A.4)

APPENDIX A. GAIN FORMULA OF A DISTRIBUTED AMPLIFIER

A.2

Constant-k and m-derived filter

Constantk filters are designed to reject certain frequencies but matches the characteristic impedances between the source and load throughout its pass band. A modified version of the constant-k filter is the m-derived filter. This type of filter exhibits an extremely sharp cut-off, while maintaining a constant impedance throughout its pass band [1][2]. A Low-pass ”L” type constant-k design filter is one in which Z1 × Z2 = k 2 ,

where Z1 is the impedance of the series arm of the filter, Z2 the impedance of the shunt arm of the filter and k a constant equal to characteristic impedance of the filter.

A.3

Gain of Distributed Amplifier

In order to compute the gain of a n section distributed amplifier (DA), we have, first, to consider the gate line elementary section (Fig. A.1), and express the voltage Vgk (k = 1, ..., n), as a function of the input voltage Vin . Lg/2

Lg/2

Vgk

Vk-1

Vk Ri

Zi1

Zi2

Figure A.1: Elementary gate line section.

Vk = Vk−1

r

Zi2 − γ2g e Zi1

(A.5)

where Zi1 and Zi2 are the image impedances of the elementary section, and γg = αg + jβg is its propagation constant. We can then find the voltage across the kth transistor: γg Vin e− 2 Vgk = p 2 2 (1 + xg )(1 − xc )

II

(A.6)

A.3

GAIN OF DISTRIBUTED AMPLIFIER

where Now, we have to consider the output current It , by summing up all the current contributions from each transistor: It =

n X

Iok

(A.7)

k=1

where Iok is he current delivered by the kth transistor, as shown in the following figure. Ld/2

Vk

Ik/2

Ik/2

Ld/2

Iok

Zds = Rds // Cds

Ik=gm Vgk

γd

Figure A.2: Elementary drain line section.

Iok =

−Ik 2

r

Zi2 −γd (n−k+ 21 ) e Zi1

(A.8)

where Ik = gm Vgk is the current produced by each transistor because of the internal transconductance gm , and γd = αd + jβd is its propagation constant [3]. So, we can write: It =

−gm Vin 2

r

n 1 Zi2 X Vgk e−γd (n−k+ 2 ) Zi1

(A.9)

k=1

and by replacing Vgk by its expression, we find:

−gm Vin It = p (1 + xg 2 )(1 − xc 2 )

r

Zi2 −0.5n(αg +αd ) sinh [0.5n (αg − αd )] e Zi1 sinh [(αd − αg )]

(A.10)

The phase shift per section or the propagation velocity of the gate and drain lines can be made the same by making the cut-off frequencies of both the lines equal. In order to make the cut-off frequencies equal, the gate and drain lines characteristic III


impedances should be made equal. Knowing the definition of the power gain: Gp =

|It |2 ℜ (ZL ) Pout = Vin 2 Pin Zi1 ℜ (Zi1 )

(A.11)

where ZL is the load at the output of the DA. Gp =

2 sinh [0.5n (αg − αd )] gm Zo2 e−0.5n(αg +αd ) 4(1 + xg 2 )(1 − xc 2 ) sinh [(αd − αg )]

where ωg =

IV

1 , Rgs Cgs

ωc = √

2 Lg Cgs

= √

2 , Ld Cds

xg =

ω ωg

and xc =

ω . ωc

(A.12)

A.3

GAIN OF DISTRIBUTED AMPLIFIER

References [1] D. M. Pozer, Microwave Egineering, Wiley, 2 edition, 1997. [2] T. T. Y. Wong, Fundamentals of Distributed Amplification, Artech House, 1993. [3] J. B. Beyer, S. N. Prasad, R. C. Becker, J. E. Nordman, and G. K.Hohenwarter, “MESFET distributed amplifier design guidelines,” IEEE Trans. Microwave Theory Techniques, vol. 32, no. 3, pp. 268 – 275, March 1984.

V


VI

APPENDIX B TRANSISTOR’S LINEAR AND NON-LINEAR MODELS B.1

The AC model for SOI MOSFET

This linear model for SOI MOSFET’s (FD and PD) is a table based model scalable and extracted from measures done on the transistors for two drain bias voltage (0.8 and 1.2 V ) This model includes a also the noise caused by the gate and the drain of the MOSFET, developed by Prof. G. Dambrine from IEMN (France) [1] (Fig. B.1).

Figure B.1: The RF model of the SOI MOSFET.

B.2

The non-linear model

This model describes accurately the electrical (DC-RF) characteristics of MOS devices. It includes a nonlinear drain current expression that is continuous and infinitely derivable, leading to the transconductance and the output conductance to be continuous. The capacitances are derived directly from a gate charge expression that ensures the charge conservation principle. In order to perform a validation of the model, large-signal simulations of bulk MOSFETs have been carried out and the measurements, using a Nonlinear Network Measurement System (NNMS), are compared to the simulations. Note that it is a general model for all MOS devices and it has been VII

APPENDIX B. TRANSISTOR’S LINEAR AND NON-LINEAR MODELS

validated for SOI MOSFETs Fig. B.2. This model is an empirical nonlinear model, which is charge conservative, for MOS transistors, useful for large signal RF circuit simulation, has been presented. This model is a compromise between compact models and look-up table models, and combines some advantages of each modeling technique. The electric equivalent circuit is similar to those used for all FETs, it includes a nonlinear drain current expression and a nonlinear gate charge equation. The model shows very good DC and RF prediction of the nonlinearitys and the harmonics level [2].

Cgd

Rgd

Gate Cgs Ri

Drain Vgsi

Cds

Ids = f (Vgs i ,V gd i ) Source

Figure B.2: Schematic of the non linear model of the SOI MOSFET.

VIII

B.2

THE NON-LINEAR MODEL

References [1] G. Dambrine, J.-P. Raskin, F. Danneville, D. Vanhoenacker Janvier, J.-P. Colinge, and A. Cappy, “High-frequency four noise parameters of silicon-on-insulator-based technology MOSFET for the design of low-noise RF integrated circuits,” IEEETransactions-on-Electron- Devices, vol. 46, no. 8, pp. 1733–1741, August 1999. [2] A. Siligaris, Modélisation grand signal de MOSFET en hyperfréquences: application ` a l’étude des non linéarités des filières SOI, Ph.D. thesis, IEMN- France., December 2004.

IX

APPENDIX B. TRANSISTOR’S LINEAR AND NON-LINEAR MODELS

X

APPENDIX C PHASE NOISE MEASUREMENTS WITH A SPECTRUM ANALYZER Microwave oscillator phase noise can be measured by several techniques, the least complicated of which is direct measurement with a spectrum analyzer. The spectrum analyzer may be used to measure phase noise directly provided that the spectrum analyzer dynamic range is sufficient for the input signal, the spectrum analyzer internal local oscillator phase noise is not greater than the noise from the device under test (DUT), the DUT output frequency remains reasonably stable during the spectrum analyzer sweep period, and the amplitude modulated (AM) noise of the DUT is much less than the devices phase noise. When applicable, this technique produces fast and reasonably accurate results; however, inappropriate use of this method will produce substantially erroneous data [1].

Fig. C.1 is a simplified block diagram of a superheterodyne spectrum analyzer. Heterodyne means to mix; that is, to translate frequency. And super refers to superaudio frequencies, or frequencies above the audio range. Referring to the block diagram in Figure 2-1, we see that an input signal passes through an attenuator, then through a low-pass filter to a mixer, where it mixes with a signal from the local oscillator (LO). Because the mixer is a non-linear device, its output includes not only the two original signals, but also their harmonics and the sums and differences of the original frequencies and their harmonics. If any of the mixed signals falls within the passband of the intermediate-frequency (IF) filter, it is further processed (amplified and perhaps compressed on a logarithmic scale). It is essentially rectified by the envelope detector, digitized, and displayed. A ramp generator creates the horizontal movement across the display from left to right. The ramp also tunes the LO so that its frequency change is in proportion to the ramp voltage [2].

The used measurement setup is a HP8562A spectrum analyzer (Fig. C.2). A DC block is placed at the input of the analyzer. The cable length should be as low as possible, even if a calibration is not necessary as phase noise is a ratio of power waves. The biasing of the circuits, specially for on-wafer measurements, have to be highly decoupled. XI

APPENDIX C. PHASE NOISE MEASUREMENTS WITH A SPECTRUM ANALYZER

Figure C.1: Block diagram of a spectrum analyzer.

Figure C.2: Setup for phase noise measurements.

C.1

Measurement procedure

The two quantity present in the definition of phase noise are measured separately.

L(∆ω) = 10log

Psideband (ω0 + ∆ω, 1Hz) Pcarrier

(C.1)

where Psideband (ω0 + ∆ω, 1 Hz) represents the power of a 1 Hz bandwidth contained in a lateral band of the output spectrum. This power is measured at a ∆ω shift from the center frequency ω0 . Pcarrier is measured with a large Resolution Bandwidth (RBW) in order to have the whole peak inside the filter bandwidth. Typical RBW value is 2 M Hz. The Video Bandwidth (VBW) should also be as high as possible (auto mode is OK). In order XII

C.1

MEASUREMENT PROCEDURE

to protect the setup, the attenuator should be put on its maximum value for the first measurements. Then, in order to increase the Signal-to-Noise Ratio (SNR), it should be turn to the minimum allowable value. Psideband is evaluated using a low RBW. Indeed, if a high RBW is used, it is the filter shape that is measured, and not the oscillator spectrum itself. However, the smaller the RBW, the longer the sweep time. This may be problematic in the case of free-running oscillators. In order to get Psideband , the power is measured inside the RBW and then normalized to a 1 Hz BW. A correction factor linked to the accuracy of the IF filter should be added [1] (Table C.1):

L(∆ω) = 10log

Psideband (ω0 + ∆ω, 1Hz) 1 Pcarrier αRBW

RBW range 1 Hz ... 300 KHz 300 KHz ... 1 M Hz 1 M Hz ... 2 M Hz

Filter accuracy ±10% ±25% +50% − 25%

(C.2)

α 1.1 1.25 1.4

Table C.1: Correction factor in function of the IF filter accuracy. The HP8562A permits to evaluate the noise power directly. Indeed, the Marker Noise option of the analyzer is used to get Psideband . The correction factors introduced previously are automatically taken into account. This function activates a 32 points averaging [3][4]. Fig. C.3 compares equation C.2 to the data from the marker noise option. The acquisition of the data make use of a Lab-View interface, using an application developed by P. Simon form EMIC lab. ([4], which provides the phase noise given by the the marker phase noise of the spectrum analyzer, and the curve obtained using equation C.2, as shown in the following figure, for the designed CDO.

XIII

APPENDIX C. PHASE NOISE MEASUREMENTS WITH A SPECTRUM ANALYZER

−60 Extracted from HP Calculated

SSB Phase Noise (dBc/Hz)

−70 −80 −90 −100 −110

PN = 128 dBc/ Hz @ 1 MHz −120 −130 −3 10

−2

10

−1

10

0

10

1

10

Offset from carrier frequency (MHz)

Figure C.3: Phase Noise of the designed CDO measured with the HP 8562 A spectrum.

Figure C.4: Power spectrum and Phase Noise of the designed CDO measured with the HP 8562 A spectrum, using the Lab-VIEW application.

XIV

C.1

MEASUREMENT PROCEDURE

Main limitations • Both amplitude and phase noise are measured, so AM should be at least 10 dB smaller than PN.

• Measurements close to the carrier (∆f < 1 KHz) are not possible. Better accuracy if ∆f > 10 KHz.

• Phase Noise of the circuit under test should be higher than the one of the spectrum analyzer.

XV

References [1] O. Grinbergs, “Determination of Microwave Oscillator Phase Noise by Direct Measurement With a Spectrum Analyzer,” Tech. Rep., University of South Florida, http://ee.eng.usf.edu/WAMI2/StudentProjects/projects.html, 1998. [2] Agilent Corp.,

Agilent Spectrum Analysis Basics. Application Note 150,

http://cp.literature.agilent.com/litweb/pdf/5952-0292.pdf, 2005. [3] B. Parvais, Nonlinear Devices Characterization and Micromachining Techniques for RF Integrated Circuits,

Ph.D. thesis, Université catholique de Louvain,

September 2004. [4] P. Simon, “Mesure du bruit de phase avec un analysuer de spectre,” Tech. Rep., Université catholique de Louvain, 2004.

XVI

CMOS SOI Distributed Amplifiers for New

CMOS SOI Distributed Amplifiers for New

Suggest Documents

CMOS Distributed Amplifiers With Extended Flat ... - Semantic Scholar

GRAPHENE SOI CMOS SENSORS FOR DETECTION

m SOI CMOS Microprocessor Technology

Chap. IV –CMOS Operational Amplifiers

Development FD-SOI MOSFET amplifiers for integrated read-out ...

Broadband CMOS-compatible SOI temperature ... - OSA Publishing

Comparison of Bulk and SOI CMOS Technologies

Synthesis of CMOS Operational Amplifiers Through ... - CiteSeerX

Adaptive biasing CMOS amplifiers - IEEE Xplore

Synthesis of CMOS Operational Amplifiers Through ... - CiteSeerX

3D CMOS SOI for High Performance Computing - CiteSeerX

SOI CMOS For HT Analog/MS Apps. - CiteSeerX

SOI CMOS Tunable Capacitors for RF Antenna Aperture ... - IEEE Xplore

A CMOS Readout Circuit for SOI Resonant ...

65nm SOI CMOS SoC Technology for Low-Power ... - IEEE Xplore

Fully Depleted CMOS/SOI Device Design Guidelines for ... - CiteSeerX

SOI CMOS For HT Analog/MS Apps.

Characterization of CMOS Fully Differential Amplifiers for ... - SBMicro

RF CMOS Class C Power Amplifiers for Wireless ... - CiteSeer

Bandwidth Extension Techniques for CMOS Amplifiers - IEEE Xplore

A Noise Optimization Formulation for CMOS Low-Noise Amplifiers ...

Design Procedure for Two-Stage CMOS Operational Amplifiers ...

Efficiency Enhancement Techniques for CMOS RF Power Amplifiers

Graphene Distributed Amplifiers: Generating ... - Semantic Scholar