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Digital Predictive Feed-Forward Controller for a DC–DC Converter in Plasma Display Panel Suyong Chae, Student Member, IEEE, Byungchul Hyun, Student Member, IEEE, Pankaj Agarwal, Woosup Kim, Student Member, IEEE, and Bohyung Cho, Senior Member, IEEE
Abstract—This paper describes a new digital control method to enhance the dynamic performance of a dc–dc converter used in plasma display panel (PDP). A simple digital PID compensator with duty ratio feed-forward control is proposed to minimize the output voltage variation while the load current is continuously changing. The duty ratio feed-forward is calculated using noise-free load current information which is predicted by the available video data of the PDP. No separate current sensing circuit is required. A small signal -domain feed-forward model is derived for the performance analysis and controller design. The proposed control method is experimentally verified on an asymmetrical half bridge dc–dc converter which supplies power to a 42 in PDP. Index Terms—DC–DC converter, digital feed-forward control, load current prediction, plasma display panel (PDP).
I. INTRODUCTION
I
N the area of flat panel display technology, the plasma display panel (PDP) stands out as a leading device with benefits including large screen size, high contrast ratio, and good color reproduction capability. The PDP requires various dc voltages ranging from 100 to 200 V to generate driving pulses for displaying image data. The driving pulse sequence is controlled by the digital video processing circuit using the input video data. The PDP power system normally consists of at least five dc–dc converters to supply those dc voltages. The important role of the PDP power system is to provide a precisely regulated output voltage of about 190 V during the sustaining period [1], [2] in order for high image quality; namely, bright uniformity. As the PDP typically uses a periodic pulsed type driving scheme [3], [4] for displaying the video data, the load current of the dc–dc converter is continuously changing from no load to full load with a 16.7 ms time constant. The video data can be another source of information to the dc–dc converter, in addition to the output voltage, since the load current is
Manuscript received March 21, 2007; revised July 26, 2007. This work was presented in part at the IEEE Applied Power Electronics Conference and Exposition (APEC), Anaheim, CA, 2007. This work was supported by Samsung SDI, Korea. Recommended for publication by Associate Editor S. Y. R. Hui. S. Y. Chae, B. C. Hyun, W. S. Kim, and B. Cho are with the Department of Electrical Engineering and Computer Science, Seoul National University, Seoul 151–744, Korea (e-mail :
[email protected];
[email protected];
[email protected];
[email protected]). P. Agarwal is with the Visual Display Division, Samsung Electronics, Suwon 443–742, Korea (e-mail :
[email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TPEL.2007.915646
proportional to the level of the video data. The digital control approach is advantageous when applied to the converter because the new information is digital and the digital video processing circuit can integrate the controller without an added cost. The conventional method of meeting the tight regulation specifications at this load condition is to design a feedback compensator with a wide bandwidth and a high dc gain. A two loop analog feedback control is normally applied to the dc–dc converter in the PDP. However, this control method may have a bandwidth limitation depending on the power stage topology. In the case of the digital control scheme [5], [6], the increase of bandwidth is additionally limited by the sampling effect and the computation delay. The load current feed-forward control has been used to improve the transient response and the regulation performance of dc–dc converters. The previous methods [7]–[12] were designed using the sensed load current. The feed-forward controller in [13] used the estimated load current, but the estimation was based on the sensed output inductor current and the output capacitor current. The digital predictive control method [14]–[17] normally focuses on the inductor current in implementing a current mode controller. However, the proposed method uses the predicted load current to enhance the performance of the low speed voltage mode feedback controller. This paper introduces a digitally implemented duty ratio feed-forward control method to improve the load regulation dynamics of the converter. To predict the load current information, the internal digital video data of the PDP is used without a separate sensing network. The proposed control method calculates the required duty ratio variation from the predicted load current. This method operates at both continuous conduction mode (CCM) and discontinuous conduction mode (DCM), where the operation mode is decided from the predicted load current. This paper is organized as follows. Section II explains the proposed feed-forward algorithm including the load current prediction method. The small signal -domain model and the stability analysis are introduced in Section III. Section IV presents the simulated and actual test results of the 400 W asymmetrical half bridge (AHB) dc–dc converter on a 42 in PDP. The conclusion will be presented in the final section. II. CONTROL METHOD AND LOAD CURRENT PREDICTION A. System Configuration Fig. 1 shows the proposed digital control scheme, which includes the duty ratio feed-forward and load current prediction
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Fig. 1. 400 W AHB dc–dc converter for a 42 in PDP.
block, in addition to the digital PID compensator. The output load current of the next switching period is predicted using the video information in the load current prediction block. In the case of the digital display device like the PDP, the input video data is rearranged by considering the driving method and driver integrated circuits (ICs) [18]. After the rearrangement of the video information, the dc–dc converter supplies current to the PDP for displaying the image on the screen. Hence, there exist a constant time interval between the input of video data and the change of the load current. During this time interval, the load current of the next switching cycle is predicted using the input video information. The predicted current information is utilized in the duty ratio feed-forward block to calculate the required with respect to the slowly varying duty duty ratio variation . This instantaneous adjustment of the duty ratio for ratio the load current variation enhances the dynamic performance of the converter, especially for load regulation. In addition, it is advantageous for noise immunity, because the proposed method does not use a current sensing circuit to obtain the load current information. Fig. 2. Inductor current and output load current waveform. (a) Continuous conduction mode. (b) Discontinuous conduction mode.
B. Duty Ratio Feed-Forward in CCM The inductor current waveform in CCM is shown in Fig. 2(a). for the th The predicted load current is denoted by 1 in switching period. It is also possible to determine advance because we can use the video information before the change of the load current. The operation mode is decided by the following condition:
where is the steady state duty ration in CCM, is the turns is the switching period. ratio of the transformer and The relation between the output load current and the duty is ratio
CCM DCM
(1)
(2)
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Fig. 3. DC–DC converter and input filter of PDP.
Then
is given by (3)
is restricted from 0 to 0.5 by the converter charSince is acteristic, the required duty ratio variation
(4)
Fig. 4. Load current comparison.
verter control loop should be designed to avoid interaction with the input filter. The current transfer function can be approximated as where
(8)
C. Duty Ratio Feed-Forward in DCM The inductor current waveform in DCM is shown in Fig. 2(b). 1 th switching period is The output load current at the expressed by
(5) If we define the voltage gain as M and the ratio of the inductor is given by current falling period as
The discharge current frequency of the PDP coincides with the frequency of the sustaining driving pulse. The sustaining driving pulse is generated by the full-bridge panel driver [19], [20] and its sequence is controlled by the digital video processing circuit of the PDP as shown in Fig. 1. From this digital sequence control signal (SCS), the timing information of the discharge current is obtained. The amplitude of the discharge current is proportional to the average signal level (ASL) of the video data [4]. The SCS and ASL are digitally transferred to the load current prediction block from the digital video processing circuit. The discharge current, , is simply modeled as (9)
(6) , can be pre-calculated for the whole DCM The duty ratio, range of 1 . The calculated value of is saved as a 1 lookup table in the digital controller and indexed by during operation. Furthermore, is obtained by a simple . subtraction process
where the SCS is a 1 b logic signal and the ASL is an 8 b logic vector. The multiplication of (9) is realized using a simple combinational logic approach. The state of the SCS is periodically checked by a logic comparator and it determines the value of . If the state of the SCS is logic 1, is equal to the value of the ASL. Otherwise, is set to be zero. with a fast sampling The -domain representation of period, , is as follows:
D. Load Current Prediction As the frequency and peak value of the discharge current is very high (400 kHz, 100 A), an input filter, as shown in Fig. 3, is generally used in the driving circuit of the PDP. The current transfer function between and is (7) where is the input filter capacitance, is the input filter is the closed loop output impedance of the inductance and dc–dc converter. Normally, the output impedance, , is much , as the consmaller than the impedance of the inductance,
(10) This current transfer function is implemented digitally in the load current prediction block of the controller. The load current, , is predicted immediately by inputting into the digital . current transfer function, Fig. 4 shows the predicted and measured load current in the white image mode. It is shown in Fig. 4 that the predicted load current tracks the real load current to within 0.3A.
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III. SMALL SIGNAL MODELING AND ANALYSIS A. Small Signal Modeling The performance and stability of the proposed controller is analyzed by means of a small signal model. The derivation of a small signal model is executed for the case in which the converter operates in CCM. The AHB dc–dc converter in Fig. 1 has two state equations within one switching period,
where Fig. 5. Open loop transfer functions.
open loop small signal -domain model of the converter can be calculated
(13) The and with parameters used in the experimental prototype are shown in Fig. 5. It is observed in Fig. 5 that the and limits the bandwidth increase second resonance of of the feedback compensator [22], [23]. The discrete time small signal modeling of the feed-forward controller is derived as follows. The duty ratio and output load current are composed of a steady state value and a small perturbation (11)
From (11), the averaged discrete time state equation is derived using a discrete time modeling method [21]
(14) Using (14) the linearization of (3) results in a -domain small signal representation of the feed-forward block (15)
where
The small signal block diagram, including the feed-forward model, , is depicted in Fig. 6. B. Output Impedance and Stability The load unterminated closed loop output impedance, expressed by
, is
(12)
(16)
If we consider a small perturbation from its steady state value , the
where is the open loop output impedance is the with a feed-forward block, , and load unterminated loop gain with a digital PID compensator,
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Fig. 6. Small signal model block diagram.
Fig. 8. Load unterminated loop gain(T ) and loading factor(T ).
Fig. 7. Closed loop output impedance comparison.
Fig. 9. Load terminated loop gain.
. In order to examine the influence of the feed-forward controller, the closed loop output impedance is plotted using the converter parameters that are used in the experiment. It is observed in Fig. 7 that the feed-forward controller decreases the closed loop output impedance, which results in a reduced output voltage variation in comparison to the conventional digital PID feedback controller at the same output load current. , terminated small signal loop gain, , is deThe load, rived for the stability assessment (17) The load unterminated loop gain, , is designed to be stable as shown in Fig. 8. Fig. 8 also shows that the magnitude of the , is lower than 0 dB for the entire frequency loading factor, range. From these observations we can judge that the system is stable without interaction between the converter and the load [24]. Finally, it is confirmed in Fig. 9 that the load terminated loop gain, , is stable.
IV. SIMULATIONS AND EXPERIMENTAL RESULTS A. Converter Implementation To demonstrate the performance improvement of the proposed control algorithm, a 400 W AHB dc–dc converter operating at a 70 kHz switching frequency was implemented. The converter parameters are listed in Table I. The output capacitance, , is selected to maintain the output voltage ripple below , is designed for CCM op0.3 V. The output inductance, , and eration above 30% load. The input filter inductance, , are the same as that in a 42 in PDP. The dc capacitance, blocking capacitance, , is the minimum possible value to keep the dc voltage. The transformer magnetizing inductance, , is chosen to prevent core saturation and the turns ratio, , is selected to limit the maximum duty ratio to 0.45. The damping resistance, , and capacitance, , are selected experimentally. The overall conversion efficiency of the prototype converter is 92%.
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TABLE I EXPERIMENTAL CONVERTER PARAMETERS
Fig. 10. Simulated output voltage variation.
B. Simulations Simulations are performed by MATLAB SIMULINK to verify the reduction of the output voltage variation by the proposed controller. The digital voltage mode PID controller, , is designed for the loop gain, , to have a 2 kHz bandwidth and 70 phase margin, as shown in Fig. 9. The bandwidth is selected to avoid the second resonance of the converter and to guarantee sufficient phase margins while considering the digital sampling effects. The simulation is executed in full white image mode. Fig. 10 clearly shows that the output voltage variation is reduced from 3 V to 1.5 V by the proposed control method. C. Experiments The proposed digital control algorithm is implemented using a Xilinx FPGA. The control performance is verified experimentally on a 42 in PDP. The feedback compensator is digitally implemented with the same parameters as the simulation. An analog peak current mode controlled [25] AHB converter with a 2 kHz bandwidth and 110 phase margin as shown in Fig. 11 is tested for the sake of comparison. All experiments are executed using a 42 in PDP operating in full white image mode, at which the PDP requires the maximum load current. It is shown in Figs. 12 and 13 that the proposed method reduced the output voltage variation by 50% when compared to the digital PID compensator without the feed-forward
Fig. 11. Transfer functions of the analog controller.
controller. The waveforms marked as (d) in Figs. 12 and 13 represent the duty ratio of the digital controller. The duty ratio in Fig. 12 changes faster than that in Fig. 13 in order to track the continuously changing load current. Through this fast tracking, the proposed method demonstrates better performance. The output voltage variation of the analog peak current mode controlled AHB converter is shown in Fig. 14. From Figs. 12 and 14, it is observed that the output voltage variation of the proposed method is reduced by 25% in comparison with the result of the two loop analog controller. The same PDP driving waveforms marked as (c) in Figs. 12–14 guarantee that all experiments are performed under the same conditions. V. CONCLUSION This paper introduces a new digital control method for a dc–dc converter, which utilizes the internal video information of the PDP. From this video information, the load current of a dc–dc converter is predicted by a digital current transfer function. No separate current sensing circuit is required. The proposed method can be implemented without any added cost,
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REFERENCES
Fig. 12. Digital controller with feed-forward: (a) output voltage V (50 V/div), (b) ac coupled V (1 V/div), (c) PDP driving waveform (200 V/div), and (d) duty ratio(1 V/div).
Fig. 13. Digital controller without feed-forward: (a) output voltage V (50 V/div), (b) ac coupled V (1 V/div), (c) PDP driving waveform (200 V/div), and (d) duty ratio(1 V/div).
Fig. 14. Analog peak current mode controller: (a) output voltage V (50 V/div), (b) ac coupled V (1 V/div), and (c) PDP driving waveform (200 V/div).
as there is enough available room in the digital video processing circuit of the PDP. The simulation and experimental results show that the variation of the output voltage is reduced by 50% compared to the conventional digital PID compensator. The proposed method also demonstrates an improved performance in comparison to an analog peak current mode controller. Test results were obtained with a 400 W AHB dc–dc converter of a 42 in PDP operating in full white image mode.
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[24] D. Lee, B. Choi, J. Sun, and B. H. Cho, “Interpretation and prediction of loop gain characteristics for switching power converters loaded with general load subsystem,” in Proc. IEEE Power Electron. Spec. Conf., 2005, pp. 1024–1029. [25] R. B. Ridley, “A new, continuous-time model for current-mode control,” IEEE Trans. Power Electron., vol. 6, no. 2, pp. 271–280, Apr. 1991.
Suyong Chae (S’07) received the B.S. and M.S. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejon, in 1998 and 2000, respectively, and is currently pursuing the Ph.D. degree at Seoul National University, Seoul, Korea. From 2000 to 2005, he was a Research Engineer with Samsung SDI where he developed plasma display panel video processing circuits. His research interests include digital display power systems and digital control approach of dc–dc converters.
Byungchul Hyun (S’07) received the B.S. degree from KyungPook National University (KNU), Daegu, Korea, in 2004 and the M.S. degree from Seoul National University (SNU), Seoul, Korea, in 2006 where he is currently pursuing the Ph.D. degree. His interests include resonant converters, multiple output converters, and power factor correction (PFC) circuits.
Pankaj Agarwal received the B.S. degree from the Indian Institute of Technology (IIT), Kanpur, in 2004 and the M.S. degree in electrical engineering and computer science from Seoul National University, Seoul, Korea, in 2006. He is currently a Research Engineer in the Advanced R & D Group, Visual Display Division, Samsung Electronics, Suwon, Korea. He has worked on the energy recovery circuits and power supply of PDP and other capacitive loads. His interests include analysis and design of resonant converters and inverters especially for display applications.
Woosup Kim (S’07) received the B.S. degree from Kwangwoon University, Seoul, Korea, in 2003 and is currently pursuing both the M.S. and Ph.D. degrees at Seoul National University. His interests include HID ballast, resonant converters, and flat panel device driver circuits.
Bohyung Cho (M’89–SM’95) received the B.S. and M.S. degrees from the California Institute of Technology, Pasadena, and the Ph.D. degree from the Virginia Polytechnic Institute and State Universtiy (Virginia Tech), Blacksburg, all in electrical engineering. Prior to his research at Virginia Tech, he worked as a member of technical staff with the Power Conversion Electronics Department, TRW Defense and Space System Group. From 1982 to 1995, he was a Professor with the Department of Electrical Engineering, Virginia Tech. In 1995, he joined School of Electrical Engineering, Seoul National University, Seoul, Korea, where he is currently a Professor. His research interests include power electronics, modeling, analysis and control of spacecraft power processing equipment, and distributed power systems. Dr. Cho received the 1989 Presidential Young Investigator Award from the National Science Foundation. He is a member of Tau Beta Pi.
