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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 2, FEBRUARY 2010

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Switch-Matrix-Based High-Density Microelectrode Array in CMOS Technology Urs Frey, Jan Sedivy, Flavio Heer, Member, IEEE, Rene Pedron, Marco Ballini, Jan Mueller, Douglas Bakkum, Sadik Hafizovic, Francesca D. Faraci, Frauke Greve, Kay-Uwe Kirstein, and Andreas Hierlemann, Member, IEEE

Abstract—We report on a CMOS-based microelectrode array (MEA) featuring 11,011 metal electrodes and 126 channels, each of which comprises recording and stimulation electronics, for extracellular bidirectional communication with electrogenic cells, such as neurons or cardiomyocytes. The important features include: (i) high spatial resolution at (sub)cellular level with 3150 electrodes per mm2 (electrode diameter 7 m, electrode pitch 18 m); (ii) a reconfigurable routing of the recording sites to the 126 channels; and (iii) low noise levels. Index Terms—CMOS-based microelectrode array (MEA), extracellular recording and stimulation, neuronal interface, reconfigurable switch matrix.

I. INTRODUCTION UBSTRATE-integrated microelectrode arrays (MEA) are arrangements of usually 60 electrodes that are used for multisite extracellular recordings from electrogenic cells, such as neurons, heart cells, retinal cells or muscle cells. They are used in the fields of neuroscience and biosensing to study fundamentals of learning processes, aging and mental diseases, to assess the behavior of electrogenic cells in vitro [1]–[4], for screening of pharmacological agents [5]–[8], or for the detection of hazardous substances [9]. Even though early publications on MEAs date back already several decades [10], the field of MEAs is still growing, and new applications are emerging. MEAs have become commercially available just within the last decade [11]–[13]. Most devices have electrodes with diameters ranging between 10 m and 30 m and feature densities of up to 100 electrodes per mm . For a summary of in vitro and in situ applications of MEAs, see, e.g., an article of Stett et al. [14]. The use of CMOS-based devices can overcome some limitations of passive MEAs, in particular for performing measure-

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Manuscript received December 19, 2008; revised July 22, 2009. Current version published February 05, 2010. This paper was approved by Associate Editor Kenneth Shepard. This work was supported by an ETH internal grant TH-1-03-1. U. Frey was with the Bio Engineering Laboratory, Department of Biosystems Science and Engineering, ETH Zurich, Switzerland, and is now with IBM Research, Zurich, Switzerland. F. Heer, M. Ballini, J. Müller, S. Hafizovic´, F. D. Faraci, and A. Hierlemann are with the Bio Engineering Laboratory, Department of Biosystems Science and Engineering, ETH Zurich, Switzerland. ˇ J. Sedivý is with the Bio Engineering Laboratory, Department of Biosystems Science and Engineering, ETH Zurich, Switzerland, and the Faculty of Electrical Engineering, Czech Technical University, Prague, Czech Republic. R. Pedron, F. Greve, and K.-U. Kirstein were with the Bio Engineering Laboratory, Department of Biosystems Science and Engineering, ETH Zurich, Switzerland. D. Bakkum is with the University of Tokyo, Tokyo, Japan. Digital Object Identifier 10.1109/JSSC.2009.2035196

ments at a high spatial and temporal resolution. Biological or electrophysiological experiments at cellular or subcellular resolution are highly desirable to elucidate the contributions of individual cells to collective network or colony behavior. The diameter of somata of most neuronal cells ranges between 10 m to 50 m for vertebrates [15], [16]. Three different approaches to achieve cellular resolution in extracellular electrical recordings have been realized so far: (i) constraining the cells with regard to the electrode positions [17], [18], (ii) adapting the electrode layout to the biological structure [19] or (iii) using high-density arrays that record from all electrodes simultaneously [20], [21]. The high-density arrays are usually CMOS-based devices that overcome the connectivity limitation by making use of on-chip signal multiplexing. The simultaneous recording from all electrodes requires the front-end amplifiers being placed in each pixel (recording site), which, due to area constraints, entails rather high noise levels. Instead of scanning the entire electrode array, the approach presented here provides a reconfigurable electrode/readout-channel routing to select an arbitrary subset of electrodes for recording and stimulation. This enables both, low-noise signal recording, and cellular or subcellular resolution, since the front-end circuitry can be placed outside the array (Fig. 1), where sufficient area for a low-noise circuit implementation is available [22]. Integrated neuronal amplifiers [23] are used for two different applications. They are, on the one hand, used in planar MEAs, which are in the focus of this paper. However, similar amplifiers with similar requirements are also used for needle-type implantable neuronal probes [24], [25]. The paper is organized as follows. Section I describes the implementation of the CMOS microsystem, Section II details the measurement setup to operate the chip, Section III describes the design methodology for the switch matrix, Section IV includes experimental results, and Section V concludes the paper. II. SYSTEM DESCRIPTION The 126 channels and the associated signal amplification and stimulation circuitry are located outside the reconfigurable electrode array, as depicted in the block diagram in Fig. 2. The electrode array with the implemented switch matrix is described in Section II-A. The block of the readout and stimulation channels includes two amplification and filter stages. They are implemented as Miller-compensated 2-stage amplifiers, which are detailed in Section II-B and Section II-C. Both stages feature digitally configurable gain and filter settings. The first stage provides a high-pass filter (HPF), a low-pass filter (LPF) and a gain of 30 dB. The second stage provides addi-

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Fig. 1. Micrograph of the fabricated device. The size of the chip is 7.5

2 6.1 mm , the size of the electrode array is 2.0 2 1.75 mm .

Fig. 2. Block diagram of the chip architecture and the on-chip electronics.

tional gain of either 0 dB, 20 dB or 30 dB with a second LPF. An offset compensation scheme, as described in Section II-C, was implemented in this stage. Amplifier settings, such as gain and LPF cut-off, are set to the same values for all channels. Eight channels are then multiplexed and buffered by a third stage with an additional gain of 0 dB, 6 dB, 14 dB or 20 dB, and finally digitized at 20 kHz using successive-approximation analog-to-digital converters (ADCs) with a resolution of 8-bit. The digital recording controller then transfers the data off chip by means of a 9-bit bus together with chip-status information and a CRC (cyclic redundancy check) for error detection, as described in Section II-F. The recording controller also controls

the ADCs and the multiplexers. A one-time programmable 16-bit ID was included on the device that allows for keeping track of the devices and enables automated database access for retrieving device-specific calibrations (such as electrode impedance data) and storing recording protocols. Two additional channels are used to monitor the temperature and the DC potential on a separate electrode (Section II-D). The command decoder and recording controller are implemented in their own clock domains, which allows for a simple interfacing circuitry on the PCB level. The command decoder decodes commands that are used to configure the array, to define the amplifier and bias settings, and for stimulation. The stimu-

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Fig. 3. Sketch of a reconfigurable switch matrix enabling a flexible subset selection for readout and stimulation. (a) Principle of routing a subset of electrodes (1–6) to channels (A-F) for readout and stimulation. (b) General implementation of a pixel (marked with the dashed line) within such an array (the implemented switch matrix is drastically simplified, see Fig. 4).

Fig. 4. Subset of the implemented switch matrix.

lation capability is provided through two 10-bit flash DACs and voltage stimulation buffers. A. Switch Matrix The flexibility in electrode selection is attained by the use of an analog switch matrix, integrated underneath the electrode array. The switch matrix consists of 13 k SRAM cells and analog ) to define the routing from the switches (PMOS, electrodes to the amplifiers as illustrated in Fig. 3(a). Fig. 3(b) shows a general form of such a switch matrix, which resembles routing schemes of field-programmable gate arrays (FPGAs). The small squares in this figure represent the switches required to connect the electrodes to the wires. Each electrode is connected through connection boxes (C-Boxes) to horizontal and vertical readout wires. The readout wires are then interconnected by switch boxes (S-Boxes) that contain switches to connect two wires, either a horizontal to a horizontal, a vertical to a vertical, or a horizontal to a vertical wire. Wires can also go through the S-Box without being interrupted by a switch.

The memory bits that drive the switches are located within the array and are implemented as standard 6T-SRAM cells, made of minimum-size transistors. An SRAM cell has the advantage of very small power consumption in static mode, thereby reducing the power dissipation within the array to a minimum. The feature size of the CMOS technology used for the fabrication of the device (0.6 m) and the constraints on the pixel area limit the number of switches within each pixel to one. As at least one C-Box with at least one switch is required for each electrode, some electrodes need to be sacrificed for pixels that contain a minimal version of an S-Box without any electrode. However, the resulting ‘holes’ are covered up by slightly shifting the other electrodes, so that finally the electrodes are evenly distributed (Fig. 14). The actual wiring is implemented as illustrated in Fig. 4, which is a drastic simplification of the general layout described in Fig. 3(b). To obtain the configuration for the switches, the switch matrix is represented as a graph, as illustrated in Fig. 5, and the routing problem is solved. The problem resembles a binary max-flow,

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Fig. 5. Graph representation to solve the routing problem.

min-cost problem, with the ‘interesting spots’ being the sources and the ‘channels’ being the sinks. The switch configuration should provide a maximum ‘flow’ with a minimum cost. However, there are some constraints that set the problem apart from the standard max-flow, min-cost problem and also from constraints normally used in FPGA routing algorithms: one electrode can, e.g., pick up the signal from two (or more) neurons. This means that we have a larger inflow into a node than outflow. To deal with this issue and with other special routing constraints, the optimization problem is solved with a general integer linear program (ILP) solver that permits any linear constraints. The ILP can be written as: Minimize (1) subject to (2) where is a vector of integers to be sought for, is the cost are vectors of defined lower and upper vector and and bounds. For our routing problem, represents the state of the switches, i.e., arcs in the graph. The constraint that renders them either open or closed, i.e., binary, is (3) The constraints for all the different node types, shown in Fig. 5, are given in (4), below. Additionally, an excess node is added with arcs from all neurons. Those arcs are assigned a high penalty cost to allow for convergence in the case that a neuron cannot be connected.

The solution of the ILP provides the state of all the switches within the array. The array is programmed row-by-row by serially shifting bits into a shift register, located below the electrode array (Fig. 1) and by then transferring the content to one row of SRAM cells. Some optimizations on the configuration stream are performed in software to reduce its length and, thereby, the necessary configuration time. An example of the routing performance is given here. The cost of the first arcs is given as the Euclidian distance from the electrodes to the center of the spots of interest. Simulations have been carried out for routing 126 randomly distributed spots of interest to the 126 channels. The average distance from any spot of interest to the closest electrode was found to be 6.75 m and provides the lower bound of for the used set the achievable routing performance. The implemented routing scheme provides an average distance to the connected electrode of 7.1 m, whereat 114.6 out of the 126 spots of interest are read out via the closest electrode, 10.1 through the second closest and the remaining 1.3 via the third or fourth closest electrodes. 102 electrodes in a 6 17 rectangular configuration constitute the largest obtainable coherent electrode block. B. Front-End Amplifier Offset and drift that occur at the electrode can significantly exceed the signal amplitude. Offsets of up to 1 V and drifts in the electrode potential of 100 mV within a few seconds have been measured [26]. For this reason, a HPF, with a cut-off frequency below 1 Hz has been used in the first stage, as shown in Fig. 6. As the wiring within the electrode array is single-ended, the

(4)

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Fig. 6. Amplification stages of the readout channels with the first stage featuring a low HPF cut-off frequency.

amplifier was also implemented in a single-ended way with a pseudo-differential input stage. The gain of the first stage is 30 dB and is defined by the capacitance ratio . The value of represents a tradeoff between gain accuracy, corner frequency and area. A value of 150 fF was chosen for , leading to a total area of 150 280 m for the first stage. The cut-off frequency and the of the first-order HPF is given by the capacitance resistive part of the feedback, which is implemented with two diode-connected transistors and [27]–[32]. To achieve a low cut-off frequency, the resistance must be large; therefore, the transistor is of minimum width. In order to reduce substrate leakage currents, the length was also kept small (1 m). To improve the symmetry of the structure and to get a more linear , a second diode was added in behavior for small values of reverse direction yielding better defined values of even for . This structure results in a cut-off frequency of below 1 Hz. The opamp used in the first stage was implemented with a two-stage amplifier with a differential input stage and a common-source output stage. and are operated in weak inversion: (5) The other transistors are operated with mV and therefore (6)

have to be conFor noise considerations, the transistors sidered. The equivalent input noise of a differential input stage is (7) which shows that the influence of and is smaller, if the ratio of is small. For a good tradeoff between low should be roughly noise and small area the terms equal to the term . Additionally, a noise must be made. The tradeoff between thermal and noise depends on the area of the transistor (8) and does not depend on the bias current. A larger area of the transistor cannot be achieved by increasing , as this would lower , which results in larger thermal noise. The thermal noise is given by (9) The thermal noise is dominant in the 5-kHz signal band. A larger bias current will decrease the thermal noise, as , but it will also increase the power consumption and will compromise stability. The transistor size of was chosen as 10/30, with a bias current of as 360/2 and that of A and A. The simulated noise level then amounts to 3.2 (output noise divided by the midband gain).

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An input offset of or less.

mV can be compensated in steps of 5 mV

D. Temperature Sensor and DC-Potential Sensor

Fig. 7. Miller-compensated two-stage opamp used in the first stage.

The LPF cut-off, , is realized using the Miller capacitance . The gain-bandwidth product of the opamp is (10) with being the transconductance of the first stage and the gain. The Miller capacitance is implemented as a 1.8 pF capacitor, and a second capacitor (4.8 pF) that can be switched on kHz or and off, which yields a LPF cut-off frequency of kHz. The exact value depends on the bias current, which, in turn, can be digitally adjusted at the chip level. A zeroing resistor was included to improve the stability, with a value of k . Additionally, the first stage can be bypassed, which provides a useful means to test features in DC mode, such as the array routing wires, the DACs and the ADCs. Due to the large signals that are applied during stimulation the first amplification stage can saturate. Therefore, this stage also features a reset (Fig. 6) switch to discharge the feedback capacitance C2 and to, thereby, bring the amplifier back to its operating point after it has been saturated. In a pseudo-differential configuration, the impedance at the output ot the amplifier is considerably larger than the impedance to analog ground. This impedance mismatch leads to unbalanced charge injection, which renders the reset to be ineffective. The resistor R6 with a nominal value of 100 k was added, which reduced this effect as it is evident from simulations. C. Second Stage and Offset Compensation The second amplification stage is a non-inverting amplifier, also implemented as a two-stage Miller compensated opamp. The adjustable gain of either 0 dB, 20 dB or 30 dB is achieved by switching between different resistors R , R and R in the kHz feedback, as shown in Fig. 6. An LPF with a cut-off of kHz is implemented in the same way as in the first stage. or This stage also contains an offset compensation mechanism. It is implemented by making the width of the current mirror transistor digitally adjustable (5 bits), as shown in Fig. 8. The , , and MS is length of the current mirror transistors 12 m, has a width of 28.8 m, of 19.2 m and MS feature values of 12.8 m, 6.4 m, 3.2 m, 1.6 m and 0.8 m.

Electrogenic cells are very temperature-sensitive. Therefore, one of the 128 recording channels has been used to monitor the on-chip temperature. It makes use of the difference in of two identical, diode-connected bipolar transistors, biased at different currents, to generate a voltage proportional to the absolute temperature (PTAT) [33], [34]. The implemented sensors are characterized and described in more detail in [26] and [35]. Another channel is used to monitor the electrode DC potential. It consists of a single amplifier stage with a gain of 0 dB that connects to an extra Pt electrode. Due to the undefined electrochemical potential of the Pt, the electrode does not monitor the real DC-value of the saline solution, instead, it monitors a potential similar to what all the other electrodes of the array measure. This potential information can be used for two applications. First, by monitoring the values of this channel the user of the system can make sure, that he operates the electrode array at a potential, at which the pMOS switches within the array are conducting. This cannot be done by observing the values of the regular HP-filtered recording channels. The second purpose is to detect the occurence of electrolysis anywhere on the chip. Electrolysis usually results in slow fluctuations of the potential within the culturing bath. Monitoring such electrolysis solely through the HP filtered channels is dangerous, as the fluctuations are filtered out, and, amplifiers hitting their rail may generate spike-like signals at their output. Therefore, this additional channel is intended to be used in parallel to normal operation to detect broken chips or other irregularities. E. Stimulation Buffer To provide electrical stimulation to the cells the HD-MEA includes the stimulation buffers described in [26] and shown in Fig. 9. A class-AB buffer was chosen to keep the quiescent power consumption low. The buffer has a slew rate of 0.5 V/ s at a load of 20 nF. The quiescent power consumption is 150 W. When slewing, the buffer can deliver up to 10 mA. The buffer occupies an area of 42 32 m . The buffers are switched off, when they are not selected for operation and connected to an electrode. Stimulation can be applied through two different routing architectures to the electrodes. The first routing scheme relies on the use of the readout switch matrix, which connects one readout channel directly to the output of the stimulation buffer. The second stimulation routing is implemented in a row- and column-like fashion, and will be described in more detail in Section II-G. This second routing scheme allows for using all recording channels simultaneously and independently of the stimulation buffer. It also allows for selecting larger rectangular patches of electrodes for stimulation. The input to the stimulation comes from one of the two 10-bit DACs provided for stimulation. Having two DACs allows for simultaneous stimulation with two different waveforms. The measurement implementation (see Section III) allows for sending commands with an 8 MHz clock, yielding a sampling rate of more than 100 kHz when controlling both DACs in parallel.

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Fig. 8. Second amplifier stage with offset compensation.

A command starts with a start-bit, followed by the chip address, the length of the command in nibbles, the command, the command arguments, and it ends with a CRC (CCITT-4). A command is only executed, if the chip address matches or if the chip address is the broadcast address 0xF, and when no CRC error is detected. Upon each successful command execution, the command counter is incremented. The command counter is implemented as a Gray counter, which simplifies the synchronization between the command decoder and recording controller clock domain. Commands are used to program the on-chip PROM ID, to configure the switch matrix, to define the amplifier settings (gain, LPF, biasing), to set the multiplexer switching scheme, to set the stimulation DACs, to adjust the DC-offset compensation FFs, to configure the stimulation buffers, and to execute the HPF reset. Before executing any commands, the command decoder checks the integrity of the received commands by means of the CRC. It also increments a command counter on successful execution of commands. The command counter is then transmitted off chip, providing a means to track the chip status. Fig. 9. Class-AB stimulation buffer (from [26]).

G. Validation and Testing F. Digital Part The digital part is split into two clock domains, one for the recording controller side, which also controls the ADCs and the multiplexers, and another one for the command decoder, which decodes and executes configuration and stimulation commands. The 16 ADCs in the recording controller part run at a clock frequency of 3.2 MHz, and need 10 clock cycles for one conversion at 8-bit resolution. One frame of output data consists of 160 bytes, 128 of which are used for the ADC data. The additional frames are used to transmit status information about the device, such as the multiplexer settings, the DAC values and amplifier settings. Additionally, the chip address, a 16-bit frame counter and the command counter are inserted. A CRC (CRC-16/CITT) used for error detection concludes the frame. For convenience, an additional pad is used to send frame synchronization pulses. On the command decoder side, the commands are received as a bitstream, clocked in by the separate command decoder clock. The commands are in the following format:

For electrical characterization, functional validation and testing of the fabricated devices several supporting blocks have been implemented. Electrical characterization and functional validation can be achieved through the test probe access, shown in Fig. 2. Fig. 10 sketches the implementation of this probe access. It consists of a shift register, into which probe settings can be serially loaded, independently of the operation of the digital core of the device. The probe shift register is divided into two parts that can be individually activated through the corresponding test mode pins. One part is for overriding the amplifier settings, which are normally provided by the digital core. This option can be used to overcome limitations caused by the digital controller, in using, e.g., unforeseen operation modes. The other part of the shift register holds settings that determine the routing of the probe input and probe output ports. Those access ports are wired in a way to give access to all amplifier stages and the stimulation buffer of channel 0, the ADC, the DACs, and directly to the electrode array. The output probe supports both, the buffered and unbuffered mode. The unbuffered mode is useful for current measurements. The testing of the digital part is supported through the implementation of two scan chains, one for each clock do-

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Fig. 10. Probe access for electrical characterization and validation.

Fig. 11. Block diagram of the system. A photograph of the support board with plugged-in chips is shown on the left side.

main. Testing of the analog part and, especially the ADCs, is simplified by using the bypass mode of the first stage, which eliminates the HP function (Fig. 6). To be able to validate and test the routing within the electrode array, a separate row of stimulation buffers has been implemented, which makes use of an additional wiring scheme within the array. These buffers can be connected to the electrodes without making use of the normal routing wires. They rely on a grid-like routing, which supplies the stimulation signals on horizontal stimulation wires, and which connects the buffers to the electrodes by means of vertical stimulation-enable lines. These additional stimulation buffers are also useful for, e.g., the stimulation of large rectangular blocks of electrodes. III. MEASUREMENT SETUP The measurement system as depicted in Fig. 11 consists of three main blocks. A custom-designed PCB was built that provides sockets for five HD-MEAs that can be operated simultaneously. It is essential to avoid mechanical perturbation by handling devices with plated cells prior to measurements. There-

fore, a multichip setup has been developed [3]. The board provides all necessary clock and digital control signals, as well as all required analog references to the chips. The value of the references can be programmed using the on-board microprocessor. This processor also monitors the environmental conditions (temperature and humidity). To minimize the amount of required connections, the data are serialized on the board and sent via two twisted-pair links at 16 MB/s. By using a serial LVDS protocol, a 6-wire ribbon cable is sufficient to connect the board with the rest of the system. The main data acquisition and feedback control unit is realized using the platform Xilinx Virtex-II-Pro FPGA. This component features fast data-processing algorithms, implemented on the programmable logic, and also hosts two PowerPC cores, both capable of running a Linux operating system with clock frequencies up to 300 MHz. The data are converted back to a parallel representation, the data streams from the different chips are separated, and a CRC check is performed. The extracted data are then distributed via an internal data bus to the data processing units, e.g., compression and spike-detection units. These

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Fig. 12. Diagram showing the blocks of the golden model, used for the design and during measurements with the system, and their functions.

units use direct memory access (DMA) to write the results into the system memory DRAM, where they can be accessed from applications running on the PowerPC. As the chips produce large amounts of data, which need to be stored for later processing, a compression block was designed. It is a lossless compression that encodes the difference between two data points in time using Rice coding [36] with an adaptive algorithm to update the compression parameters depending on the measured signal properties [37]. The application program running on the PowerPC core is responsible for the data transport between the FPGA core and the supervising computer. The third component is the software running on the PC. It consists of a server application and several clients connected to the server. As HD-MEAs have a complex structure with an electrode routing matrix and a programmable gain, the server implements five chip-emulator modules. Every time the real chip configuration is changed, the same changes are applied to the corresponding emulators. The client applications can then retrieve the currently connected electrodes, gain and filter settings from the emulators (Section IV). All communication links from the chip to the PC are protected by CRCs in either direction, allowing for error detection and thereby ensuring data integrity. IV. DESIGN METHODOLOGY FOR SWITCH MATRIX AND SYSTEM A golden model of the switch matrix and the overall system has been implemented in C++ and was used in all design cycles of the HD-MEA and was also used during measurements.

The golden model was used in design exploration for determining the optimal routing within the array, during the design implementation for generating the netlists and the automatic layout placement scripts, during the functional verification and post-fabrication validation for generating test bench stimuli and simulated expected responses. But it has also been used during measurements with the device for generating configurations and command streams and for emulating the system to keep track of its status. Fig. 12 shows a diagram listing the different applications and functions of this golden model. At its core is the model of the switch array and the routing algorithm, described in Section II-A. Each pixel within the array is described with its electrode, its SRAM switch, the routing wires, a small graph detailing the connectivity of the respective subunits, and a list of terminals (ports) at its boundary. The array is then built by assembling all the different pixels. At this point, the model combines all individual pixel graphs based on the pixels terminals, so that a graph representation as shown in Fig. 5 results. From this representation, the netlist and the skill code for layout placement are exported, allowing to construct the layout of the array and to perform an LVS (layout versus schematic). The graph representation is further used by the ILP routing algorithm to obtain the SRAM content for the desired configuration. This configuration is then used to generate command streams in different formats (stimuli vectors for digital and AMS simulation, vcd for analog simulations, bitstreams for direct interfacing with the devices and formatted streams for interfacing with the FPGA). The golden model also

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Fig. 13. SEM pictures of the fabricated high-density microelectode array. (a) Electrodes plated with chicken dorsal root ganglion neurons, cultured for 2 DIV, scale bar: 20 m. (b) Chip cross section to illustrate the 3-mask post-processing steps, scale bar: 2 m.

Fig. 14. Uniform electrochemically grown Pt-Black. Scale bar: 50 m.

contains emulation blocks for all the other parts of the system, allowing to generate expected responses based on command streams. The stimulus vectors and expected responses are used to perform circuit simulations on the behavioral and transistor level. During laboratory use of the devices the golden model and the system emulators are embedded in the server (see Section III) that interfaces with the FPGA. Commands are sent via the server to the chips. The CRCs and the command counter, included in the digital part of the HD-MEAs, are used to check on the proper execution of the commands. This information, together with the recorded data, is sent back to the server, which buffers the data and emulates the system status for the application clients that are connected. This procedure simplifies the interfacing of different tools to the system, such as Neurotalker [38], MEA-Bench [39], a LabView based client for data visualization, Matlab for data analysis, or others.

Fig. 15. Packaged device.

V. EXPERIMENTAL RESULTS A. Fabrication The chip was fabricated in an industrial 0.6 m 3-metal, 2-polysilicon CMOS-process. A micrograph of the device is

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Fig. 16. Measured transfer function of the three amplifier stages for a gain of 1000 and the lowest possible LPF cut-off settings. The bottom part shows the input-referred noise spectrum for the same settings.

shown in Fig. 1. The total device size is 7.5 6.1 mm , and the electrode array covers an area of 2.0 1.75 mm . Special post-CMOS processing and packaging steps are required to render the chip capable of operating in physiological solution with cell cultures on top. The 2-mask post-processing step includes sputtering Ti:W (20 nm) as adhesion and platinum (200 nm) as electrode materials and patterning of the metals with the help of a lift-off process. Thereafter a 1.6- m-thick passivation layer stack (SiO and Si N ) is deposited for corrosion protection [26]. The Pt electrode openings are shifted away from the locations of the original CMOS aluminum contacts to ensure long-term stability. Together with the electrodes a large integrated on-chip Pt-reference-electrode has been fabricated. It is placed around the electrode array and has a total area of roughly 0.6 mm . Fig. 13(a) shows the fabricated chip, on which chicken dorsal root ganglion neurons have been cultured for 2 days in vitro (DIV). The 2-mask post-CMOS processing sequence yielded good results with chips being operable for several weeks in culture. During long term culturing of several months, however, it was found that the areas, where the thick insulating passivation stack has been opened to access the Pt electrodes, constitute weak spots in the overall protection, since the rather thin and uneven CMOS foundry passivation is the only protection there. Failure repeatedly occured after about 6–7 weeks in culture. Therefore, the post-processing was changed to a 3-mask sequence with the first and additional step being a deposition of 500 nm Si N to increase the thickness of the bottom passivation. Fig. 13(b) illustrates the 3-mask post-processing steps with the shifted-electrode design. Up to now, failures due to a degradation of the improved passivation layer have no more been observed. To reduce the electrode impedance, Pt-black can be electrochemically deposited on the electrodes, using 1.0 nA/m current density in a solution containing 7 mM hexachloroplatinic acid, 0.3 mM lead acetate, and hydrochloric acid to adjust the solution pH to 1. A platinum wire was used as a counter electrode, connected to an external current source, and the on-chip stimulation

circuitry was used to set the electrode to a defined potential. A uniform platinization could be obtained as it is shown in Fig. 14. The electrode-electrolyte interface can in first order be approximated by an ideal capacitor C and a so called charge transfer in parallel [40]. is in the order of 1 G and resistor the capacitance C is 0.5 nF for bright Pt electrode and increases to around 5 nF for Pt-Black electrodes. The electrode capacitance is orders of magnitudes larger than the input capacitance of the amplifiers, so the voltage drop across it can be neglected. The yield in the electrode fabrication was moderate for the first batch of wafers featuring high spatial resolution. Good devices showed 100% functional electrodes, however, in bad devices up to a few percent of all electrodes have been damaged. Automated image processing algorithms and manual electrode testing was used to identify the broken electrodes and to automatically blank them out for the subsequent use in measurements and the associated data processing. In more recent batches of wafers, the electrode yield has been reliably and reproducibly improved to close to 100%. The electrode shape and morphology have been very uniform on the recently processed wafers, as can be seen in Fig. 14. B. Packaging To allow for culturing of cells, the chips have been packaged as illustrated in Fig. 15. The processed chip is mounted and wire-bonded on a custom-designed printed-circuit board (PCB) with an electroplated nickel/gold edge-connector. A glass ring is then glued on the PCB, and a water-resistant medical epoxy (EPOTEK 302-3M) is used to encapsulate the bond wires and the pads. The packaging yield is currently limited by the poor adhesion of the epoxy to the chip substrate. If the epoxy lifts off from the substrate, culture media can flow to the bond wires leading to electrolysis and corrosion, which renders the chips unusable. For short term cultivation or acute preparation an estimated yield of about 90% has been achieved. For long term culturing over several weeks, the yield drops to an estimated

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Fig. 17. Recording from adjacent electrodes during stimulation. (a) shows the percentage of electrodes that can be recorded from directly (0.25 s) after stimulation versus distance to the stimulation electrode. (b) shows stimulus-induced activity in a culture of dissociated neurons. The recording electrode is located 130 m away from the stimulation electrode. 35 traces are shown in gray, one of which is highlighted in black, the amplitude is input referred.

70%. It has to be noted that the yield figures for packaging are strongly depending on the way of handling the HD-MEAs. C. Electrical Characterization The measured transfer function of the readout channels is shown in Fig. 16, measured for a gain of 1000 and the lowest possible LPF cut-off frequency. The bottom part shows the noise spectrum using the same settings for three different cases: (i) the amplifiers with shorted inputs (2.4 output noise within the band of 1 Hz to 100 kHz, divided by the midband gain), (ii) use of bare Pt-electrodes (3.9 ) and (iii) use of dendritic Pt-black electrodes (3.0 ) in saline solution. Compared to [26], the noise has been reduced by 10 dB, which

is mainly due to the use of the diodes, , and the relaxed area constraints (i.e., larger input transistors). The ADC contributes 0.5 LSB quantization noise. Worst-case signal crosstalk within the array (2 mm long, parallel readout wires with minimum spacing) was assessed to be 67 dB in a saline solution using Pt-black electrodes. The standard deviation of the inputreferred offset is 0.7 mV. The gain accuracy of the first stage is smaller than 1.1% (std). The overall chip power consumption is 135 mW, 115 mW of which are consumed by the third amplification stage, the ADCs and the digital core located more than 2 mm away from the array (Fig. 1). The power dissipation within the array itself is negligible. One readout channel (stage 1, 2) consumes 160 W in an area of 0.07 mm .

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Fig. 18. Electrophysiological signals obtained from different biological preparations. The input-referred signal amplitudes are shown.

Experiments to compare the reset operation for architectures with and without the additional resistor R6 in the first stage (Fig. 6) showed that R6 considerably reduces the time, during which the amplifiers stay out of range. For a total gain of 60 dB, which is used in most experiments, most amplifiers will stay out of range during 10 or more milliseconds. On the stimulation electrode itself, it was not possible to achieve reliable recordings with a gain of 60 dB during the approximately first 50 ms after stimulation. This drawback of the architecture is alleviated by the fact that, due to the high spatial electrode density, it is sufficient for many applications to be able to simultaneously perform recordings on electrodes nearby the stimulation electrode. Fig. 17 shows the capability to simultaneously record on neighboring electrodes during stimulation: the percentage of non-saturated electrodes versus distance between recording electrode and stimulation electrode is displayed. Biphasic pulses with amplitudes of mV and a duration of 400 s per phase have been used with a HD-MEA featuring Pt-Black electrodes, immersed in saline buffer solution. D. Electrophysiological Measurements Stimulation experiments have been done with cortical neuronal cells cultured for 46 DIV on the HD-MEA. Fig. 17 shows 35 traces containing directly evoked activity through stimulation

of neuronal cells. The recording electrode was located 130 m away from the stimulation electrode. Stimulation consisted of biphasic voltage pulses with 500 s per phase, featuring an amplitude of 800 mV at an inter-stimulation interval of 300 ms. The gain was set to 60 dB. MEA-Bench [39] was used to control the experiment. The evoked spikes with an amplitude of less than 200 V followed 1 ms after the stimulation artifact. For this experiment, cells from E18 rat cortices, dissociated in trypsin, were grown in DMEM (Invitrogen) with 10% horse serum on top of the CMOS arrays. A thin layer of poylethyleneimide and a 15 L drop of laminin were used for cell adhesion. Experiments were conducted inside an incubator to control environmental conditions. Fig. 18 shows spontaneous electrical activity in several biological preparations, recorded using the HD-MEA, to illustrate the broad applicability of the microsystem. The top trace was obtained from neonatal rat cardiomyocytes (NRCs) cultured for 3 days. NRCs were isolated from the hearts of newborn Wistar rats (Elevage Janvier, Le Genest Saint Isle, France) by digestion with collagenase (Worthington Biochemical Corp., Freehold, NJ, USA) and pancreatin (Invitrogen, Carlsbad, CA, USA), followed by density gradient purification. One thousand NRCs were seeded in 1 ml plating media containing DMEM (67%, Invitrogen), M199 EBS (17%, AMIMED, Switzerland), horse serum (10%, Invitrogen), fetal

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TABLE I PERFORMANCE SUMMARY

matrix provides a high degree of flexibility in the electrode selection and allows for low-noise amplifier implementations outside the array. A system for data acquisition has been developed. The functionality of the overall system has been verified with electrical tests and measurements in biological preparations. A summary of the main parameters of the microsystem is given in Table I. ACKNOWLEDGMENT The authors would like to thank U. Müller, S. Senn, and S. Berg for contributing to the circuit and system design, D. Scheiwiller for help with the post processing, Prof. Dr. U. Egert, C. D. Sanchez-Bustamante, D. Jäckel, U. Wahlen, E. Perriard, T. Neumann, Dr. A. Blau, and Dr. B. Roscic for help with the biological measurements and data analysis, the EMZ at the University Zurich for providing Fig. 13(a), and Prof. Dr. H. Baltes for his interest in their work.

bovine serum (5%, PAN biotech GmbH, Germany), and penicillin/streptomycin solution (1%, Sigma), and then placed onto a HD-MEA that had been previously incubated with 20 g/ml laminin (Sigma) for 2 hours at 37 C. HD-MEAs containing cells were cultivated at 37 C in a humidified atmosphere containing 5% CO for up to 10 days. The middle trace stems from dissociated rat hippocampal neurons cultured for 16 DIV. The neurons were taken from hippocampal tissue that was extracted from newborn Sprague-Dawley rats and dissociated by trypsinization (0.25% Trypsin/EDTA) and gentle trituration. Cells were plated on laminin (10 g/ml) and poly-L-lysine (10 g/ml)-coated CMOS chips at a density of 15,000 cells/mm and held in neurobasal medium (Gibco) containing B27 supplement (2%, Gibco), fatty acid supplement (0.1%, Sigma), lipid mixture (0.1%, Sigma), alanyl-glutamine (2 mM, Gibco) and sodium pyruvate (1 mM, Sigma). The two traces at the bottom show recordings with spike activity from acute brain slices (parasagittal slice of the cerebellum of a Long-Evans rat). The preparation was performed at room temperature as described in [41]. Oxygen was supplied through a perfusion system containing artificial cerebrospinal fluid. The on-chip counter electrode was used as a reference for recording. The two exemplary recordings shown here are from electrodes located at a distance of 38 m. Action potentials of single cells are visible on several neighboring electrodes. A more extensive analysis of the data recorded with this CMOS-based HD-MEA has been presented in [42] and [43]. VI. CONCLUSION A system to record extracellular activity from electrogenic cells in culture or tissue at high spatial and temporal resolution has been presented. The high-density microelectrode array has been fabricated in CMOS technology combined with additional post-CMOS processing steps. The device enables recording from 126 electrodes selected out of 11 k electrodes. Stimulation features have been implemented, and each electrode can also be used for stimulation. The implemented reconfigurable switch

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[18] G. Zeck and P. Fromherz, “Noninvasive neuroelectronic interfacing with synaptically connected snail neurons immobilized on a semiconductor chip,” PNAS, vol. 98, no. 18, pp. 10 457–10 462, 2001. [19] G. Gholmieh, W. Soussou, M. Han, A. Ahuja, M. Hsiao, D. Song, A. Tanguay, Jr., and T. Berger, “Custom-designed high-density conformal planar multielectrode arrays for brain slice electrophysiology,” J. Neurosci. Methods, vol. 152, no. 1–2, pp. 116–129, 2006. [20] B. Eversmann, M. Jenkner, F. Hofmann, C. Paulus, R. Brederlow, B. Holzapfl, P. Fromherz, M. Merz, M. Brenner, M. Schreiter, R. Gabl, K. Plehnert, M. Steinhauser, G. Eckstein, D. Schmitt-Landsiedel, and R. Thewes, “A 128 128 CMOS biosensor array for extracellular recording of neural activity,” IEEE J. Solid-State Circuits, vol. 38, pp. 2306–2317, 2003. [21] L. Berdondini, P. V. der Wal, O. Guenat, N. de Rooij, M. Koudelka-Hep, P. Seitz, R. Kaufmann, P. Metzler, N. Blanc, and S. Rohr, “High-density electrode array for imaging in vitro electrophysiological activity,” Biosensors Bioelectronics, vol. 21, pp. 167–174, 2005. [22] U. Frey, F. Heer, R. Pedron, S. Hafizovic, F. Greve, J. Sedivy, K. U. Kirstein, and A. Hierlemann, “An 11k-electrode 126-channel high-density microelectrode array to interact with electrogenic cells,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, San Francisco, CA, 2007, pp. 158–593. [23] T. Jochum, T. Denison, and P. Wolf, “Integrated circuit amplifiers for multi-electrode intracortical recording,” J. Neural Eng., vol. 6, no. 1, pp. 012 001–26pp, 2009. [24] K. Wise and J. Angeli, “A microprobe with integrated amplifiers for neurophysiology,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 1971, pp. 100–101. [25] K. Cheung, “Implantable microscale neural interfaces,” Biomed. Microdevices, vol. 9, no. 6, pp. 923–938, Dec. 2007. [26] F. Heer, S. Hafizovic, W. Franks, A. Blau, C. Ziegler, and A. Hierlemann, “CMOS microelectrode array for bidirectional interaction with neuronal networks,” IEEE J. Solid-State Circuits, vol. 41, pp. 1620–1629, 2006. [27] K. Najafi and K. Wise, “An implantable multielectrode array with on-chip signal processing,” IEEE J. Solid-State Circuits, vol. 21, pp. 1035–1044, 1986. [28] T. Delbruck and C. Mead, “Adaptive photoreceptor with wide dynamic range,” in Proc. IEEE Int. Circuits and Systems Symp., 1994, vol. 4, pp. 339–342. [29] R. Harrison and C. Charles, “A low-power low-noise CMOS amplifier for neural recording applications,” IEEE J. Solid-State Circuits, vol. 38, pp. 958–965, 2003. [30] R. Olsson, M. Gulari, and K. Wise, “Silicon neural recording arrays with on-chip electronics for in-vivo data acquisition,” in Proc. 2nd Annu. Int. IEEE-EMB Special Topic Conf. on Microtechnologies in Medicine & Biology, 2002, pp. 237–240. [31] R. Olsson, D. Buhl, A. Sirota, G. Buzsaki, and K. Wise, “Band-tunable and multiplexed integrated circuits for simultaneous recording and stimulation with microelectrode arrays,” IEEE Trans. Biomed. Eng., vol. 52, pp. 1303–1311, 2005. [32] R. H. Olsson, III and K. D. Wise, “A three-dimensional neural recording microsystem with implantable data compression circuitry,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2796–2804, Dec. 2005. [33] D. Hilbiber, “A new semiconductor voltage standard,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 1964, pp. 32–33. [34] R. Widlar, “New developments in IC voltage regulators,” IEEE J. SolidState Circuits, vol. 6, pp. 2–7, 1971. [35] F. Heer, “CMOS-based microelectrode array for communication with electrogenic cells,” Ph.D. dissertation, ETH Zurich, Zurich, Switzerland, 2005, Thesis No. 16330. [36] R. F. Rice, “Some Practical Universal Noiseless Coding Techniques,” Jet Propulsion Lab., Pasadena, CA, JPL Publication, Mar. 1979, pp. 79–22. [37] J. Sedivy, U. Frey, F. Heer, S. Hafizovic, and A. Hierlemann, “Multi-chip high-density microelectrode system for electrogenic-cell recording and stimulation,” in Proc. IEEE Sensors Conf., Atlanta, GA, 2007, pp. 716–719.

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[38] S. Hafizovic, F. Heer, T. Ugniwenko, U. Frey, A. Blau, C. Ziegler, and A. Hierlemann, “A CMOS-based microelectrode array for interaction with neuronal cultures,” J. Neurosci. Methods, vol. 164, no. 1, pp. 93–106, 2007. [39] D. Wagenaar, T. B. DeMarse, and S. M. Potter, “MeaBench: A toolset for multi-electrode data acquisition and on-line analysis,” in Proc. 2nd Int. IEEE EMBS Conf. Neural Eng. Conf. 2005, Mar. 2005, pp. 518–521. [40] W. Franks, I. Schenker, P. Schmutz, and A. Hierlemann, “Impedance characterization and modeling of electrodes for biomedical applications,” IEEE Trans. Biomed. Eng., vol. 52, no. 7, pp. 1295–1302, 2005. [41] U. Egert, Heck, and Aertsen, “Two-dimensional monitoring of spiking networks in acute brain slices,” Experimental Brain Research, vol. 142, pp. 268–274, Jan. 2002. [42] C. D. Sanchez-Bustamante, U. Frey, J. M. Kelm, A. Hierlemann, and M. Fussenegger, “Modulation of cardiomyocyte electrical properties using regulated bone morphogenetic protein-2 expression,” Tissue Engineering Part A, vol. 14, no. 12, pp. 1969–1988, 2008. [43] U. Frey, U. Egert, F. Heer, S. Hafizovic, and A. Hierlemann, “Microelectronic system for high-resolution mapping of extracellular electric fields applied to brain slices,” Biosensors and Bioelectronics, vol. 24, no. 7, pp. 2191–2198, 2009.

Urs Frey received the diploma in electrical engineering from ETH Zurich, Switzerland, in 2003. From 2003 to 2007 he pursued his Ph.D. thesis in electrical engineering at the Physical Electronics Laboratory at ETH Zurich, and received the Ph.D. degree from the Department of Information Technology and Electrical Engineering, ETH Zurich, in 2008. From 2008 to 2009 he was working at the Bio Engineering Laboratory at ETH Zurich, where he was leading the CMOS-based MEA activities. In 2009 he joined IBM Research, Zurich, Switzerland. The focus of his activities is on system design and interface circuitry for CMOS-based sensors and storage devices. Dr. Frey was awarded the ETH medal for his doctoral thesis entitled “Highdensity neural interface and microhotplate gas sensor in CMOS technology.”

ˇ Jan Sedivý received the diploma in electrical engineering from the Czech Technical University, Prague, Czech Republic, in 2005. During 2006–2007, he was a research assistant at the Physical Electronics Laboratory, ETH Zurich, Switzerland. Since 2008 he has been a Ph.D. student at the Czech Technical University, Prague. The focus of his research activities is on digital signal processing in conjunction with field programmable gate arrays and microelectrode chip arrays for electrogenic cells recordings.

Flavio Heer (M’01) received the diploma in physics in 2001 and the Ph.D. degree in 2005 from ETH Zurich, Switzerland. From 2005 to 2007, he was a Research Assistant at the Bio Engineering Laboratory at the ETH Zurich, where he was involved in system design and interface circuitry for CMOS-based biosensors and biochemical sensors. Currently, he is CTO at Zurich Instruments, Zurich, Switzerland. His research interests include signal processing and circuit design for sensor interfaces.

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René Pedron received the Master of Science in electrical engineering and information technology from ETH Zurich, Switzerland, in 2005. In the same year, he was a research associate with the Physical Electronics Laboratory at ETH Zurich. For three years, he has been working in the analog design group of Wipro-NewLogic in Lustenau, Austria, a semiconductor design services provider and supplier of intellectual property.

Marco Ballini received the Laura degree in electrical engineering from the University of Florence, Italy, in 2004. He worked for three years as a researcher in a laser manufacturing company. He is currently working towards the Ph.D. degree in electrical engineering at the Bio Engineering Laboratories, ETH Zurich, Switzerland. The focus of his research activities is on the design of CMOS-based microelectrode arrays.

Jan Müller received the Master degree in electrical engineering from ETH Zurich, Switzerland, in 2009. He is currently working towards the Ph.D. degree in electrical engineering at the Bio Engineering Laboratories, ETH Zurich. The focus of his research activities is on the design of CMOS-based microelectrode arrays.

Douglas Bakkum received the Ph.D. in bioengineering from the Georgia Institute of Technology and Emory University in Atlanta, GA, in 2008. He is currently a Japanese Society for the Promotion of Science (JSPS) Postdoctoral Fellow at the University of Tokyo, Japan. His research includes growing cortical neurons over grids of electrodes to investigate how rules of neural network communication can scale to produce learning, memory, and creativity.

Sadik Hafizovic´ received the diploma in microsystem technology from IMTEK, University of Freiburg, Germany, in 2002. He worked on his diploma thesis in the Tabata Laboratories at the Ritsumeikan University, Japan. Since 2002, he has been with the Physical Electronics Laboratory, ETH Zurich, Switzerland. He is currently a Research Assistant at the Bio Engineering Laboratory at ETH Zurich. The focus of his research activities is on atomicforce microscopy and CMOSbased microelectrode arrays for neuronal interfaces.

Francesca D. Faraci received the Laurea diploma in physics from the University of Genoa, Italy, in 2002, and the Ph.D. in electronics from the University of York, U.K., in 2006. She worked for three years as a research associate at the Department of Electronics of the University of York, mainly on computational electromagnetics and dosimetry for mobile telecommunication applications. She then spent two years as Senior Researcher at the Bio Engineering Laboratory, part of the D-BSSE ETH Zurich in Basel. Currently she is project leader at the TTHF lab at SUPSI (Group for Telecommunication, Telematics and High Frequency systems University of Applied Sciences of Southern Switzerland). Her research interests include bio-electronics, CMOS-based MEA, antennas and HF/RF circuits design, computational electromagnetics, application of evolutionary computation optimizations.

Frauke Greve studied electrical engineering at the University of Bremen, Germany, and at the ETH Zurich, Switzerland, from 1996 and 2002 with an intermediate stay at the University of Plymouth, U.K., and at the University of Waterloo, Canada. In 2002, she started her Ph.D. thesis in the Physics Electronics Laboratory of Prof. Andreas Hierlemann and Prof. Henry Baltes at the ETH Zurich. She finished her thesis entitled “Micromachined platforms for manipulating and recording from cells” in March 2006. Afterwards, she was employed as a Postdoc in the Bioprocess Laboratory of Prof. Sven Panke at the ETH Zurich until October 2008. She is now working as a process engineer for ABB Semiconductors in Lenzburg, Switzerland.

Kay-Uwe Kirstein (M’03) received the diploma in electrical engineering from the University of Technology Hamburg-Harburg (TUHH), Germany, in 1997, and the Ph.D. degree from University Duisburg, Germany, in 2001. From 1997 to 2000, he was a Research Associate with the Fraunhofer Institut of Microelectronic Circuits and Systems, Dresden, Germany (now Fraunhofer Institute for Photonic Microsystems) where he was involved in the development of CMOS-based spatial light modulators. From 2000 to 2002, he worked in the analog circuit design group at Micronas GmbH, Freiburg, Germany. Afterwards, he has been team leader of the circuit design group at the Physical Electronics Laboratory, ETH Zurich, and has also been working on various IC-design projects in industry. Currently, he is part of the sensor development group at Uster Technologies, Uster, Switzerland. His research interests include analog and mixed-signal circuit design and behavioral modeling for CMOS-based microsystems.

Andreas Hierlemann (M’05) completed his college education in chemistry at the University of Tübingen (Diploma 1992) and was awarded a Ph.D. degree in physical chemistry in 1996 by the Eberhard-Karls University in Tübingen, Germany. After that, he held two postdoc positions at the Texas A & M University, 1997, in College Station, Texas, USA, and at the Sandia National Laboratories, 1997–1998, in Albuquerque, New Mexico, USA. In 1999 he joined the Department of Physics of ETH Zurich, where he was appointed associate professor of Microsensorics in June 2004. In April 2008 he became full Professor of Biosystems Engineering at the Department of Biosystems, Science and Engineering (D-BSSE) of ETH Zurich in Basel. His research interests include the development of integrated chemical and biomicrosensor systems, the development of microfluidic techniques for cell handling and cell characterization, and the direct coupling of biological entities, such as neurons or heart cells, to microelectronic chips.

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