The Student's Guide to VHDL, Peter J. Ashenden, Morgan Kaufmann, 1998. 3. ...
Most of the homeworks are mini-projects and require VHDL programming and ...
EE 5325: Hardware Modeling Using VHDL (Spring 2002, Monday and Wednesday: 8:30–9:45 p.m., EC 2.120)
1 General Information Instructor: Office & Phone: E-mail: Office Hours: Required Text: Other References:
Course Web Page: Teaching Assistant:
Mehrdad Nourani EC 3.522, 972-883-4391
[email protected] Monday and Wednesday 4:00–5:00 p.m., or by appointment. VHDL Design Representation and Synthesis, James R. Armstrong, F. Gail Gray, Prentice Hall, 2000. 1. Introductory VHDL, From Simulation to Synthesis, Sudhakar Yalamanchili, Prentice Hall, 2001. 2. The Student’s Guide to VHDL, Peter J. Ashenden, Morgan Kaufmann, 1998. 3. Verilog Digital System Design, Zainalabedin Navabi, McGraw-Hill, 1999. http://webct.utdallas.edu/ http://www.utdallas.edu/˜nourani/Teaching/sp02 ee5325/ To be announced.
2 Catalog Description EE 5325: Hardware Modeling Using VHDL (3 semester hours). This course introduces students to VHDL beginning with simple examples and describing tools and methodologies. It covers the language dwelling on the fundamental simulation concepts. Students are also exposed to the subset of VHDL which may be used for synthesis of custom logic. VHDL simulation and synthesis labs and projects are performed using commercial and/or academic VLSI CAD tools. Prerequisite: EE 4320 or equivalent.
3 Grading Grading will be based on multiple criteria as follows:
Homeworks: Quizzes: Midterm Test: Final Project:
30% 10% 35% 25%
(to be announced ahead) (Wed. 3/6/2002, 8:30–10:30 p.m.) (Due on Mon. 5/6/2002)
4 Course Policy Homeworks will be assigned throughout the semester, and will be due approximately once every two weeks at 8:30 p.m. at the beginning of the lecture period.
Most of the homeworks are mini-projects and require VHDL programming and using SYNOPSYS CAD tools for simulation, analysis and synthesis. To have enough time start as early as possible.
A homework is considered late if it is turned in after 8:30 p.m. of the due date. There will be 20% per day penalty for late homeworks up to 3 days excluding weekends and holidays. Late homeworks and reports won’t be accepted after 3 days.
Make-up tests and quizzes will not be given unless the student has obtained permission from the instructor before the scheduled test. Permission will not be given without documentation of exceptional circumstances.
Announcements and complementary materials will be posted on the course web page. However, regular attendance is highly recommended.
5 Syllabus & Tentative Lecture Plan Weeks Mon. Wed. 1/14 1/16 1/21 1/23 1/28 1/30 2/4 2/6 2/11 2/13 2/18 2/20 2/25 2/27 3/4 3/6 3/11 3/13 3/18 3/20 3/25 3/27 4/1 4/3 4/8 4/10 4/15 4/17 4/22 4/24 4/29 5/1 5/6
Readings
Topics Coverage
Ch 1 Notes
Introduction: course introduction; technologies and style; CAD environments; simulation; synthesis; HDL history and evolution. Martin Luther King Day – University Holiday HDL Overview: level of abstraction; design strategy; modeling; hierarchy; top-down design; design flow; general structure of VHDL language; events and event handling; timing; concurrency; sequentiality; Basic Features: major constructs; lexical description; data types data objects; language statements; test bench; packages; libraries; configurations; file IO, advanced features; Modeling Techniques: behavioral and structural modeling; delay modeling; Algorithmic Level Design: process model; modeling interconnects; multi-valued logic; Register Transfer Level Design: datapath and control units; processor design; sf Library Modeling: cell definition; delay annotation; special components; HDL-Based Techniques: combinational circuit design; designing sequential circuits; Mealy and Moore state machines; control unit; Midterm Test Spring Break – University Holiday
Ch 2 Ch 2 Ch 3 Ch 3 Ch 4 Ch 5 Ch 6 Ch 7 Ch 8 Ch 8
Ch 10 Notes Ch 11 Notes Notes Ch 11 Ch 12 Notes
VHDL for Synthesis: modeling for synthesis; synthesis rules and guidelines; errors; warnings; resolution functions; timing analysis; type conversion; issues on latch and flip-flops; procedures and functions; signals versus variables; if-then-else versus case; resource sharing; binding; loops; multiple processes; initialization; don’t cares; partitioning; handshaking; issues on state machines; case studies for synthesis; concept of FPGAs; concept of FPGAs; simulation and synthesis of FPGAs using VHDL; fault simulation; Verilog HDL: structure and constructs; Verilog versus VHDL; unique features of VHDL and Verilog;
Final Project
