THE IEEE System-on-Chip Conference (SOCC), cur- rently in its 29th year, ... if any additional electronic components are required to make a complete system.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 12, DECEMBER 2010
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Guest Editorial Special Section on 2009 IEEE System-on-Chip Conference
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HE IEEE System-on-Chip Conference (SOCC), currently in its 29th year, covers most areas of possible integration in its technical program. This IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART I: REGULAR PAPERS (TCAS-1) Special Section is devoted to a selection of papers expanded from presentations at SOCC, which was held in Belfast, Northern Ireland, September 9–11, 2009. The SOCC is sponsored by the IEEE Circuits and Systems Society (CAS). SOC is the term used for a fully integrated circuit, where few if any additional electronic components are required to make a complete system. The term has had many and varied definitions over time. Today, a typical SOC IC can be anything from a complex mixed-signal product, in which a wide range of functionality such as RF, analog, power management, and digital are merged, to complex digital-only devices. Such chips may contain high current and/or high voltage outputs and precision operational amplifiers, volatile and nonvolatile memory, sensors, and detectors. As a result, SOCC covers a very wide arena of integrated circuit specialties in design, test, manufacturability and theory. We would like to thank Prof. Wouter A. Serdijn, the Editor-inChief of TCAS-1, for his involvement and support of the SOCC special section. With Prof. Serdijn’s expertise we have selected and invited papers that are focused particularly toward system level, innovative design methodologies, modeling, and forwardlooking ideas to match with the readership interests of TCAS-1. The guest editors would like to acknowledge the 2009 IEEESOCC Track Chairs, the Conference General Cochair, Thomas Büchner, and Technical Program Cochair, Tughrul Arslan. We are also highly indebted to the SOCC and TCAS-1 reviewers and Editorial Board for the success of this Special Section. Contributions ranging from process developments for analog applications in the SOC area to designs that convert from the analog domain to digital, together with memory and digital advances useful in SOC implementation are included in this section. Logic circuitry is discussed in an analysis of MAC architectures in “High-Speed, Energy-Efficient 2-Cycle Multiply-Accumulate (MAC) Architecture and Its Application to a Double-Throughput MAC Unit” from Tung Thanh Hoang, Magnus Själander, and Per Larsson-Edefors. Here, an energy-efficient 2-cycle multiply-accumulate architecture includes accumulation guarding bits and saturation circuitry. Performance improvement of over 30% is observed in the new circuit.
Abhinav Kranti and G. Alastair Armstrong asses a new MOS device design aimed at improving the characteristics of operational transconductance amplifiers in “Nonclassical Channel Design in MOSFETs for Improving OTA Gain-Bandwidth Trade-off.” The work provides a new technique for realizing future ultra-wideband OTA designs using underlapped DG MOSFETs. Nan Xing, Jong-Kwan Woo, Woo-Yeol Shin, Hyunjoong Lee, and Suhwan Kim describe “A 14.6 ps Resolution, 50 ns Input-Range Cyclic Time-to-Digital Converter Using Fractional Difference Conversion Method,” where they develop a new architecture for a time-to-digital converter (TDC) in a 0.18 m CMOS process. An example of memory application in SOC applications is considered in “Single-Ended Subthreshold SRAM with Asymmetrical Write/Read-Assist.” Authors Ming-Hsien Tu, Jihi-Yu Lin, Ming-Chien Tsai, Shyh-Jye Jou, and Ching-Te Chuang describe noise and write margins in this 8T SRAM cell design in 90 nm CMOS technology. Interconnect aspects are addressed in “Variability Aware Low-Power Delay Optimal Buffer Insertion for Global Interconnects” by Ashok Narasimhan and Ramalingam Sridhar. In this paper, degraded system performance caused by global interconnect delay variation is assessed. A methodology is presented to introduce improved optimization robustness. An optimal buffering solution for the interconnect is computed. We sincerely thank all the authors for their contributions and all our dedicated reviewers for their prompt and thorough technical comments which ensured timely publication of these highquality manuscripts.
Digital Object Identifier 10.1109/TCSI.2010.2091190
1549-8328/$26.00 © 2010 IEEE
ANDREW MARSHALL, Guest Editor Silicon Technology Development Texas Instruments Incorporated Dallas, TX 75243 USA SAKIR SEZER, Guest Editor Queen’s University Belfast U.K. GABRIELE MANGANARO, Guest Editor Analog Devices Wilmington, MA 01887 USA
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 12, DECEMBER 2010
Andrew Marshall (F’10) has been with Texas Instruments Incorporated, Dallas, TX, for over 25 years, where he currently works within the Silicon Technology Development Organization. His research interests include the definition of process performance metrics and the development of circuit designs to evaluate and verify performance and power metrics for deep submicrometer silicon technologies. He is author or coauthor of over 60 papers and conference presentations, including the books SOI Design: Analog, Memory and Digital Techniques (Springer, 2002) and Mismatch and Noise in Modern IC Processes (Morgan & Claypool, 2009). He is the inventor or coinventor on 59 issued patents. Dr. Marshall is a Fellow of the Institute of Physics, U.K., and a member of the IEEE System-on-Chip Conference executive committee.
Sakir Sezer has been with Queen’s University Belfast for over 12 years, where he is currently heading the System on Chip research division with over 40 academic and full time researchers. His research is leading major (patented) advances in the field of high-performance content processing and is currently commercialised by Titan IC Systems. He has coauthored over 120 conference and journal papers in the area of high-performance network, content processing and systems on chip. Dr. Sezer has been awarded a number of prestigious awards including the InvestNI Enterprise Fellowship, InvestNI, Enterprise Ireland and Intertrade Ireland innovation and enterprise awards. He is also founder and CTO of Titan IC Systems and a member of the IEEE International System-on-Chip Conference executive committee.
Gabriele Manganaro (S’95–M’99–SM’03) received the Dr.Eng. degree (M.Sc.) in electronic engineering (with full marks) and the Ph.D. degree in electrical engineering from the University of Catania, Italy, in 1994 and 1998 respectively. From 1994 to 1996 he was involved in a joint research program on arrays of nonlinear circuits between the University of Catania and ST Microelectronics, Catania, Italy. From 1996 to 1997 he was a research associate and a lecturer at the Electrical Engineering Department, Texas A&M University, College Station, TX. From 1998 to 2001, he was a Member of the Technical Staff at Texas Instruments Inc., Dallas, TX, in the Data Converter Design Dept. From 2001 to early 2004 he was with Engim Inc., Acton, MA, as Director of Analog Baseband Design. In 2004 he joined National Semiconductor holding various positions including Design Center manager for the Salem, NH, design center and the Munich, Germany, design center and as Design Director for the High Speed Data Conversion Business Unit. In 2010 he joined Analog Devices, Wilmington, MA, as Engineering Director in the High Speed Data Conversion Product Line. He is author/coauthor of 55 scientific papers in international journals and conferences. He has been granted 12 U.S. patents, 2 European patents, and 1 Japanese patent. He is coauthor of the book Cellular Neural Networks (New York: Springer, 1999) based on his doctoral dissertation. His research and professional interests are in the area of high-performance analog integrated circuits design, in particular data converter and phase-locked loop design, and on the theory, design and application of nonlinear electronic circuits and systems. Dr. Manganaro is a Fellow of the Institution of Engineering and Technology (formerly IEE), U.K., and a Full Member of Sigma Xi, MIT Chapter. He was the recipient of the 1994 S.G.S. Thomson (now ST Microelectronics) M. Sc. graduation award, the 1995 CEU Award from the Rutherford Appleton Laboratory (U.K.), the 1999 IEEE Circuits and Systems Outstanding Young Author Award and the 2000 IEEE Dallas Section Outstanding Service Award and co-recipient of the 2007 ESSCIRC best paper award. From 1999 to 2001 he served as program chairman and as general chairman for the Dallas Chapter of the IEEE Circuits and Systems Society. Over the years he has served in the technical and organizational committees of several IEEE international conferences and has given invited lectures in Italy, the U.K., and the United States. Since 2005 he is a member of the Data Conversion subcommittee for the IEEE Solid-State Circuit Conference (ISSCC). He served as Associate Editor for IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART II from 2006 until 2007 and as Associated Editor for IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART I from 2008 until 2009. Since 2010 he is serving as Deputy Editor in Chief for IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART I. He is also a Guest Editor for the special sections on CICC 2009 and 2009 SoCs technologies on IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART I and a Guest Editor for the special issue on ISCAS 2010 to appear in 2011 in the same journal.
