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Guest Editorial Special Section on Embedded and Reconfigurable Systems
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OMPLEXITY of embedded systems has been continuously increasing according to “Moore’s Law,” bringing designers to face new challenges in their designs. At the same time, the number of applications where embedded systems are the most suitable solution has also dramatically increased. Many examples of embedded systems can be found in our everyday lives, from consumer electronics, home appliances, or automotive applications, to integrated manufacturing, aerospace, or office and business equipment. One distinctive characteristic of embedded systems is related to their reactive and real-time nature. Embedded systems need to continuously react to changes in their environments, usually constrained by some predefined timing requirements. The advent of field programmable gate arrays (FPGAs) in the mid-80s of the last century, with their characteristics complementing those of microcontrollers, opened wider opportunities for embedded systems in new application domains [1]. Reconfigurability became also a key feature for some types of applications, for instance, whenever capabilities to maintain and integrate updates into the equipment are of paramount importance. Currently, the design of electronic embedded and reconfigurable systems faces several challenges associated with different types of application-dependent technical requirements regarding performance, cost, size, availability of specific resources, energy consumption, reliability, or capability to verify design correctness. Other nontechnical constraints can also be very important, such as time-to-market (which can be the main factor for profitability), or time-to-prototype (wherever rapid prototyping techniques need to be applied). All these different requirements, and the corresponding design metrics, are usually in conflict, since design decisions made to optimize some of them may lead to very poor indicators in others. This is, for instance, the case in high-performance or high-reliability systems, where costs per unit are significantly high in most situations. Usage of FPGAs, taking advantage of their distinctive characteristics, has been supporting an effective improvement of system’s performance, while keeping costs under control (when compared to custom solutions such as those based on application specific integrated circuits—ASICs), allowing their wide usage within industrial control applications [2], [3], including power electronics control. One of these characteristics is the ability of the devices for partial and dynamic runtime self-reconfiguration, allowing the addition and elimination of parts of a circuit while in operation, so it can be adapted to specific needs on demand of the application running on the device [4]. This possibility enables exploitaDigital Object Identifier 10.1109/TII.2013.2266098
tion of FPGA architectures to build adaptive hardware tuning the platform to very different types of applications. Another aspect receiving special attention is power consumption and power awareness, where the goal is to reduce power consumption, while keeping other indicators (namely performance figures) at predefined levels. Specific techniques are commonly accepted, ranging from generic ones (e.g., partitioning the system into different components and taking benefit of using hardware-software co-design techniques) to complementary specific ones (e.g., power/clock gating, voltage/frequency scaling, and dynamic resource scaling, among others). Taking all these factors into account, it is our pleasure to present this Special Section on Embedded and Reconfigurable Systems of the IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, which addresses state-of-the-art issues on the area, including significant new contributions. Although short, it covers a comprehensive range of subjects, emphasizing power management and performance indicators, development tools, and industrial applications. This Special Section opens with the paper entitled “Power Efficient, FPGA Implementations of Transform Algorithms for Radar-Based Digital Receiver Applications” [5], by S. McKeown and R. Woods, which provides a comprehensive overview on FPGA power reduction techniques and proposes a methodology for the efficient design and implementation of highly parallel fast transform algorithms. A FFT-based digital receiver for Radar is used as application example, illustrating the benefits of the proposed methodology that takes advantage of strong data locality in the processing nodes providing better utilization of the underlying FPGA architecture resources. Power-aware system management is also the topic of the second paper, entitled “Dynamic Power Management Technique for Multi-Core Based Embedded Mobile Devices” [6], by Y.-S. Hwang and K.-S. Chung. The emergence of ubiquitous computing technologies supported by battery-operated embedded mobile devices with limited energy capacity motivates the presented work. The proposal takes advantage of the usage of pragma-based parallel programming paradigms, where the programmer instructs the compiler where to parallelize or serialize codes. While for a sequential execution region only one core is necessary, for a parallel execution region multiple cores will be useful. The number of active cores is dependent on the number of threads. This way, turning on and off individual cores according to the specific needs of current computation, will have a positive impact in terms of power consumption reduction. Being a well-known parallel programming paradigm for shared memory multi-core systems, OpenMP (Open multiprocessing) is used in the paper. Specific pragma
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directives are used to include power management strategies into the code. The techniques were validated on an embedded platform equipped with ARM-11 MPCore and on a desktop PC equipped with Intel Quad Core2 CPU running Linux OS, where no quality-of-service (QoS) violation was observed due to the power-management techniques. QoS is also the main topic for the paper “QoS-Driven Reconfigurable Parallel Computing for NoC-Based Clustered MPSoCs” [7], by J. Joven et al. A Networks-on-Chip (NoC)-Based Multi-Processor Systems-on-Chip (MPSoC) Platform is used to validate a hardware-software QoS-driven reconfigurable parallel computing framework. Authors argue that using a customized Message-Passing Interface (MPI)-like library can adequately hide hardware many-core complexity and support parallel programming on scalable NoC-based clustered MPSoCs. In this sense, a customized on-chip MPI (ocMPI) library was presented and its usage validated with a set of benchmarks and parallel applications. Authors claim that the proposed QoS-aware ocMPI library is a viable solution to manage workloads in highly parallel NoC-based many-core systems with multiple running applications. The next paper in this Special Section, entitled “Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems” [8], by J. Bispo et al., addresses performance improvements on program execution taking advantage of a runtime reconfigurable array of functional units complemented by an offline generation of Reconfigurable Processing Units (RPU). With this strategy, specific computations can be transparently moved from the CPU to specialized RPUs implemented in an FPGA. The proposed system is supported by computational tools allowing the generation of associated hardware descriptions, including configuration and communication information. As pointed out in the previous paragraph, usage of adequate computational tools is of paramount importance to effectively integrate specific methodologies and modeling techniques into engineering development flows. This is particularly true for methodologies relying on model-based developments, where frameworks for verification of properties and automatic code generation, amenable to be deployed into implementation platforms are key factors for the effective usage of underlying modeling formalisms [9]. Modeling formalisms widely used for behavioral description of the systems include state-based formalisms, such as state diagrams, state charts, and Petri nets, to mention only a few, which have been used from the beginning of electronic control systems, as well as computational intelligence-based formalisms, grouping fuzzy control, neural networks, genetic algorithms, particle swarm, and others. Neural networks have received lots of attention in the recent past. Some works, as [10], specifically address embedded systems application area, allowing direct implementation even in low-cost platforms without support from floating-point hardware. The paper entitled “CAD Tools for Hardware Implementation of Embedded Fuzzy Systems on FPGAs” [11], by M. Brox et al., presents two computational tools supporting automatic synthesis of fuzzy logic-based inference systems. The tools are integrated in the last version of Xfuzzy, a widely
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used tool in the area. The proposed tools use two design strategies for synthesizing fuzzy inference systems. One of them emphasizes hardware implementation using Xilinx’s FPGAs, the Matlab/Simulink framework, and digital signal processing (DSP) systems development tools. The second design strategy generates standard synthesizable VHDL code for ASICs and FPGAs platforms. Interoperability with other VHDL synthesis and verification tools, as well as with other FPGA development environments is claimed. The Special Section closes with the paper entitled “FPGABased Test-Bench for Resonant Inverter Load Characterization” [12], by Ó. Jiménez et al. It addresses the application of an FPGA-based system to an industrial induction heating system. The FPGA platform was used for rapid prototyping purposes, the development of an ASIC implementation being the ultimate goal of the work. Hardware-software co-design techniques were extensively used to optimize performance and resource utilization. Tasks that perform high-level functions or those not requiring fast execution were implemented in software (running on a MicroBlaze core), while hardware parts accommodate specific functions associated with high-performance tasks. ACKNOWLEDGMENT The Guest Editors would like to thank all the authors for their interesting and stimulating works (and also for their patience waiting for publication), and all the reviewers who contributed their expertise and time (often conflicting with their busy schedules) for the selection and improvement of the accepted papers. Finally, the Guest Editors would like to express their gratitude to Prof. Bogdan M. Wilamowski, Editor-in-Chief of the IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, for his support throughout the whole process. It was an honor for us to work with him for the success of this Special Section. LUIS GOMES, Guest Editor Faculty of Sciences and Technology, Department of Electrical Engineering Universidade Nova de Lisboa Caparica, 2829-516 Portugal
[email protected] JUAN J. RODRIGUEZ-ANDINA, Guest Editor Department of Electronic Technology University of Vigo Vigo, 36310 Spain
[email protected] REFERENCES [1] J. J. Rodriguez-Andina, M. J. Moure, and M. D. Valdes, “Features, design tools, and application domains of FPGAs,” IEEE Trans. Ind. Electron., vol. 54, no. 4, pp. 1810–1823, Aug. 2007. [2] E. Monmasson, L. Idkhajine, M. N. Cirstea, I. Bahri, A. Tisan, and M. W. Naouar, “FPGAs in industrial control applications,” IEEE Trans. Ind. Informat., vol. 7, no. 2, pp. 224–243, May 2011. [3] E. Monmasson, L. Idkhajine, and M. W. Naouar, “FPGA-based controllers—Different perspectives of power electronics and drive applications,” IEEE Ind. Electron. Mag., vol. 5, no. 1, pp. 14–26, Mar. 2011. [4] J. Becker, M. Huebner, G. Hettich, R. Constapel, J. Eisenmann, and J. Luka, “Dynamic and partial FPGA exploitation,” Proc. IEEE, vol. 95, no. 2, pp. 438–452, Feb. 2007.
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[5] S. McKeown and R. Woods, “Power efficient, FPGA implementations of transform algorithms for radar-based digital receiver applications,” IEEE Trans. Ind. Informat., vol. 9, no. 3, pp. 1591–1600, Aug. 2013. [6] Y.-S. Hwang and K.-S. Chung, “Dynamic power management technique for multi-core based embedded mobile devices,” IEEE Trans. Ind. Informat., vol. 9, no. 3, pp. 1601–1612, Aug. 2013. [7] J. Joven, A. Bagdia, F. Angiolini, P. Strid, D. Castells-Rufas, E. Fernandez-Alonso, J. Carrabina, and G. De Micheli, “QoS-driven reconfigurable parallel computing for NoC-based clustered MPSoCs,” IEEE Trans. Ind. Informat., vol. 9, no. 3, pp. 1613–1624, Aug. 2013. [8] J. Bispo, N. Paulino, J. M. P. Cardoso, and J. C. Ferreira, “Transparent trace-based binary acceleration for reconfigurable HW/SW systems,” IEEE Trans. Ind. Informat., vol. 9, no. 3, pp. 1625–1634, Aug. 2013. [9] L. Gomes and J. M. Fernandes, “Behavioral modeling for embedded systems and technologies: Applications for design and implementation,” IGI Global Jul. 2009. [10] N. J. Cotton and B. M. Wilamowski, “Compensation of nonlinearities using neural networks implemented on inexpensive microcontrollers,” IEEE Trans. Ind. Electron., vol. 58, no. 3, pp. 733–740, Mar. 2011. [11] M. Brox, S. Sánchez-Solano, E. del Toro, P. Brox, and F. J. MorenoVelo, “CAD tools for hardware implementation of embedded fuzzy systems on FPGAs,” IEEE Trans. Ind. Informat., vol. 9, no. 3, pp. 1635–1644, Aug. 2013. [12] Ó. Jiménez, Ó. Luc´ıa, L. A. Barragán, D. Navarro, J. I. Artigas, and I. Urriza, “FPGA-based test-bench for resonant inverter load characterization,” IEEE Trans. Ind. Informat., vol. 9, no. 3, pp. 1645–1654, Aug. 2013.
Luis Gomes (M’96–SM’06) received the Electrotechnology Engineering degree from the Universidade Técnica de Lisboa, Lisbon, Portugal, in 1981, and the Ph.D. degree in digital systems from Universidade Nova de Lisboa, Lisbon, in 1997. He is a Professor with the Electrical Engineering Department, Faculty of Sciences and Technology, Universidade Nova de Lisboa, and a Researcher at UNINOVA Institute, Portugal. From 1984 to 1987, he was with EID, a Portuguese medium enterprise, in the area of electronic system design, in the R&D Engineering Department. He is author/coauthor of more than 200 papers published in journals, books, and conference proceedings. He was coeditor of the books “Hardware Design and Petri Nets” (Kluwer Academic Publishers, 2000), “Advances on Remote Laboratories and E-Learning Experiences” (University of Deusto, 2007), and “Behavioral Modeling for Embedded Systems and Technologies: Applications for Design and Implementation” (IGI Global, 2009). His main interests include the usage of Petri nets and other concurrency models, applied to reconfigurable, and embedded systems co-design. Dr. Gomes has been serving in different roles for the organization of conferences, namely, as General Co-Chair for several IEEE-INDIN International Conference on Industrial Informatics and IEEE-SIES International Symposium on Industrial Embedded Systems, among other events. He has been serving as an Associate Editor for the IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS (2009–2013) and for the IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS (2005–08, 2011–2013), among other editorial boards.
Juan J. Rodriguez-Andina (M’00–SM’04) received the M.Sc. degree from the Technical University of Madrid, Madrid, Spain, in 1990, and the Ph.D. degree (Hon.) from the University of Vigo, Vigo, Spain, in 1996, both in electrical engineering. He is currently an Associate Professor with the Department of Electronic Technology, University of Vigo. He has authored over 130 journal and conference papers, and holds several Spanish, European, and U.S. patents. His research interests include implementation of complex processing and control algorithms in FPGAs and concurrent testing of complex systems, from digital to industrial electronics. Dr. Rodr´ıguez-Andina currently serves as the Editor-in-Chief for the IEEE Industrial Electronics Magazine and as an Associate Editor for the IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS (since 2008) and the IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS (since 2011). He has been serving IEEE conferences in different positions, including General Chair for ISIE’07 and Technical Program Chair for ISIE’12. Since 2007, he is a Member-at-Large of the Administrative Committee (AdCom) of the IEEE Industrial Electronics Society.
