Guest editorial [Special section on innovations in VLSI ... - IEEE Xplore

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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 52, NO. 5, OCTOBER 2003

Guest Editorial

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ITH EVER increasing complexity in systems design with increased levels of integration densities in digital design, better and more effective methods of testing of VLSI chips, the mainstay of many of today’s sophisticated systems, are required to ensure their reliable operation. The concept of testing has a broad applicability, and finding highly efficient testing techniques that guarantee correct systems performance has thus assumed significant importance. Besides, in recent times, a number of major innovations have also occurred in the architecture and design of automatic test equipment (ATE) or IC testers. Some of the examples include fly-by architecture (to overcome round trip delay in gigahertz testing), development of built-in self-testing (BIST) and DFT testers (for ICs with BIST and DFT), virtual testers (to validate a test program before tapeout), event testers (to link design and simulation technologies), remote operations of testers, and the most current developments in open tester architectures. Test and measurement community is increasingly adopting design solutions for test resource partitioning and scheduling, with methods to take simulation test benches directly to ATE. These developments have been demonstrated in the works of various research laboratories and industries; however, practically no worthwhile contribution in these evolving areas could be found in the current literature. One of the major objectives of this Special Section on Innovations in VLSI Automatic Test Equipment was primarily to fill some of the gaps in the increasingly complex arena of VLSI test methodologies. The unprecedented response to our Call for Papers from various segments of the test community from all over the world is a brilliant testimony to the profound interest and increased activities of the researchers, test engineers, and scientists in this very important field. All of the selected papers in this Special Section of the IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT are from those who are established authorities in the area of faulttolerance, reliability, and test generation of digital circuits including VLSI circuits, system-on-chip (SOC) integrated circuits composed of embedded cores, and test equipment. The paper in our Special Section by Chakrabarty and Seuring presents a new space compaction approach that only uses information about the fault-free responses for a precomputed test set and is, therefore, especially suitable for embedded cores. The approach does not make any assumptions about an underlying fault model, nor does it make use of any structural information about the cores. The paper by Das et al., on the other hand, considers the design of efficient time compression support hardware for BIST of VLSI circuits, utilizing concept of parity bit signature that facilitates implementing such support circuits using nonexhaustive or compact test sets, with the primary objective of minimizing the storage requirements for the circuit under test (CUT) while

Digital Object Identifier 10.1109/TIM.2003.819774

maintaining the fault coverage information as best as possible. The paper by Jone et al. proposes a BIST method for detecting nontraditional faults that include single-cell read sensitive faults and read coupling faults of embedded memory arrays for SOC design. The fourth paper in lexicographic order in the series is by Lala and Burress and it presents a synthesis algorithm for generating self-checking combinational logic for implementation on look-up table based FPGAs, which are being increasingly used in many systems including intelligent instrumentation. The fifth paper in the Special Section is by Lin and Mourad and it examines the problem of testing data communication chips, which poses a challenge because of tester limitations. The authors in the paper propose a BIST approach to test the functionality of transceivers on a data communications chip and to reduce the external bandwidth. The next paper is by Rajsuman and it examines the architecture, design, and usage of a new type of semiconductor IC test system. The traditional IC test systems require conversion of design simulation data (vectors) into cyclized form, such as WGL or STIL format. The new architecture described in this paper avoids such conversion and uses design simulation data as such, allowing testing in the design simulation environment like Verilog HDL or VHDL. The seventh paper in the Special Section by S¸ahino˘glu proposes a novel cost-effective stopping rule using Bayesian principles for a Poisson counting process compounded with logarithmic series distribution (LSD) and satisfactorily applies it to the effort-domain sequential software testing through the computed empirical Bayes estimator. It is assumed that the software failures, or branch coverage, whichever the case may be, clumped at a given test case, are positively interrelated (autocorrelated), implying that the occurrence of one software failure (coverage of a branch) adversely affects or incites the occurrence of the next. Our next two papers of the Special Section are by Savir and Guo, and by Sheth and Savir, the former investigating the detectability of parameter faults in linear, time-invariant analog circuits, and the latter describing a new singlelatch scan design technique for digital circuits using a single clock for both scan and functional operations, allowing savings in circuits, pins, and testing time. The last paper in our Special Section by Tseng et al. considers wafer level reliability (WLR) testing for process reliability qualification and in-line monitors, because WLR can provide real-time results for timely improvements. This in-situ test capability is greatly attributed to an automatic parametric tester for sample handling and data collection and analysis. In concluding this Guest Editorial, we would like to express our sincerest gratitude to all those who helped make this Special Section a reality. First and foremost amongst all is our Editor-inChief of the TRANSACTIONS, Dr. Milton Slade, who has been a continuing source of encouragement, advice, and guidance. His immense help and valued suggestions came whenever and in

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whatever form they were solicited. Without him, our dream of this Special Section would never have materialized. We would like to specially acknowledge the immense contributions of Ms. Cam Ingelin, our TRANSACTIONS Administrator, and Ms. Megan Vorel, our IEEE Staff Editor, who rendered help in innumerable possible ways in the ultimate success of our Special Section. Our particular thanks are also due to Dr. Emil M. Petriu, Professor, School of Information Technology and Engineering, University of Ottawa, Ottawa, ON, Canada, Dr. Vincenzo Piuri, Associate Editor of the TRANSACTIONS, Dr. Wen-Ben Jone of the Department of Electrical and Computer Engineering and Computer Science, University of Cincinnati, OH, and Dr. Mansour H. Assaf, former graduate student of Dr. Das at the University of Ottawa. Our heartfelt thanks are also due to those people behind the scenes, those anonymous re-

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viewers, whose selfless, dedicated, and timely professional help contributed to the superb quality of this Special Section of our esteemed TRANSACTIONS.

SUNIL R.DAS, Guest Editor School of Information Technology and Engineering University of Ottawa Ottawa, ON K1N 6N5 Canada [email protected] ROCHIT RAJSUMAN, Guest Editor Advantest America R&D Center Santa Clara, CA 95054 USA [email protected]

Sunil R. Das (M’70–SM’90–F’94) received the B.Sc. (Honors) degree in physics and the M.Sc. (Tech.) and Ph.D. degrees in radiophysics and electronics from the University of Calcutta, Calcutta, West Bengal, India. He is a Professor of Electrical and Computer Engineering at the School of Information Technology and Engineering, University of Ottawa, Ottawa, ON, Canada. He previously held academic and research positions with the Department of Electrical Engineering and Computer Sciences, Computer Science Division, University of California, Berkeley, the Center for Reliable Computing (CRC), Computer Systems Laboratory, Department of Electrical Engineering, Stanford University, Stanford, CA (on sabbatical leave), the Institute of Computer Engineering, National Chiao Tung University, Hsinchu, Taiwan, R.O.C., and the Center of Advanced Study (CAS), Institute of Radiophysics and Electronics, University of Calcutta. He has published extensibly in the areas of switching and automata theory, digital logic design, threshold logic, fault-tolerant computing, microprogramming and microarchitecture, microcode optimization, applied theory of graphs, and combinatorics. He has edited, jointly with P. K. Srimani, a book entitled Distributed Mutual Exclusion Algorithms (Los Alamitos, CA: IEEE Computer Society Press, 1992). He is coauthor, with C. L. Sheng, of a text on digital logic design, being published by Ablex Publishing Corporation. He is an Associate Editor of the International Journal of Parallel and Distributed Systems and Networks published by Acta Press, Calgary, AB, Canada, and a member of the Editorial Board and a Regional Editor for Canada of VLSI Design: An International Journal of Custom-Chip Design, Simulation and Testing published by Gordon and Breach Science Publishers, Inc., NY. He is a former Associate Editor of the SIGDA Newsletter, the publication of the ACM Special Interest Group on Design Automation, and a former Associate Editor of the International Journal of Computer Aided VLSI Design published by Ablex Publishing Corporation, Norwood, NJ. He was also Guest Editor of the International Journal of Computer Aided VLSI Design (September 1991) as well as VLSI Design: An International Journal of Custom-Chip Design, Simulation and Testing for the March 1993, September 1996, and December 2001 Special Issues on VLSI Testing.

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Dr. Das has served as the Managing Editor of the IEEE VLSI Technical Bulletin, a publication of the IEEE Computer Society Technical Committee (TC) on VLSI, and also as an Executive Committee Member of the IEEE Computer Society Technical Committee (TC) on VLSI. He is currently an Associate Editor of the IEEE TRANSACTIONS ON SYSTEMS, MAN, AND CYBERNETICS (now of Part A, Part B, and Part C) and the IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT. He is a former Administrative Committee (ADCOM) Member of the IEEE Systems, Man, and Cybernetics Society and a former Associate Editor of the IEEE TRANSACTIONS ON VLSI SYSTEMS (for two consecutive terms). He has served on the Technical Program Committees and Organizing Committees of many IEEE and non-IEEE International Conferences, Symposia, and Workshops, and also acted as Session Organizer, Session Chair, and Panelist. He also served as the Co-Chair of the IEEE Computer Society Students Activities Committee from Region 7 (Canada). He was the Associate Guest Editor of the IEEE JOURNAL OF SOLID-STATE CIRCUITS Special Issues on Microelectronic Systems (Third and Fourth Special Issues) and Guest Editor, jointly with Rochit Rajsuman, for a Special Section of the IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT on Innovations in VLSI Automatic Test Equipment, October 2003. Dr. Das is a Member of the Association for Computing Machinery (ACM). He was elected one of the delegates of the prestigious Good People, Good Deeds of the Republic of China in 1981 in recognition for his outstanding contributions in the field of research and education. He is listed in the Marquis Who’s Who Biographical Directory of the Computer Graphics Industry, Chicago, IL (First Edition, 1984). He is the 1996 recipient of the IEEE Computer Society’s highly esteemed Technical Achievement Award for his pioneering contributions in the fields of switching theory and modern digital design, digital circuits testing, microarchitecture and microprogram optimization, and combinatorics and graph theory. He is also the 1997 recipient of the IEEE Computer Society’s Meritorious Service Award for excellent service contributions to the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS AND THE SOCIETY, and was elected a Fellow of the Society for Design and Process Science in 1998 for his accomplishments in integration of disciplines, theories and methodologies, development of scientific principles and methods for design and process science as applied to traditional disciplines of engineering, industrial leadership and innovation, and educational leadership and creativity. He became a Golden Core Member of the IEEE Computer Society in 1998 in recognition for being one of the distinguished core of dedicated volunteers and staff whose leadership and services made the IEEE Computer Society the world’s preeminent association of computing professionals. He is the recipient of the IEEE Circuit and Systems Society’s Certificates of Appreciation for services rendered as Associate Editor, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, during 1995–1996 and 1997–1998, and of the IEEE Computer Society’s Certificates of Appreciation for services rendered to the Society as Member of the Society’s Fellow Evaluation Committee, once in 1998 and again in 1999. He served as a Member of the IEEE Computer Society’s Fellow Evaluation Committee for 2001, as well. He was elected a Fellow of the Canadian Academy of Engineering in 2002 for pioneering contributions to computer engineering research—specifically in the fields of switching theory and computer design, fault-tolerant computing, microarchitecture and microprogram optimization, and to some problem areas in applied theory of graphs and combinatorics. He is the recipient of the prestigious Rudolph Christian Karl Diesel Best Paper Award of the Society for Design and Process Science in recognition of the excellence of their paper presented at the Fifth Biennial World Conference on Integrated Design and Process Technology held in Dallas, TX, June 4–8, 2000. He is also the co-recipient of the IEEE’s esteemed Donald G. Fink Prize Paper Award for 2003 for a paper published in the December 2001 issue of the IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT. He was elected a Fellow of the IEEE in 1994 for contributions to switching theory and computer design.

Rochit Rajsuman (S’85–M’88–SM’92–F’03) received the Ph.D. degree in electrical engineering from Colorado State University, Boulder. He served on the faculty in the Department of Computer Engineering and Science at Case Western Reserve University, Cleveland, OH, for almost seven years. During that time, he also held a secondary appointment in the Department of Electrical Engineering. He left academia to join LSI Logic as Product Manager for test methodologies. In that role, he productized a number of test solutions for LSI Logic. From LSI Logic, he moved to a media processor startup, Equator Technologies, where he managed test, fab interface, and part of the corporate technical documentation. In 1998, he joined Advantest America R&D Center, Santa Clara, CA, as a Manager of test research, where he is now a Chief Scientist responsible for managing research and intellectual properties. He has authored/coauthored 40 awarded patents worldwide and over 30 pending. Some of the designs in his patents are now widely used in the industry. He has published over 70 papers in various journals and conferences and authored three books: System-on-a-Chip: Design and Test (Norwood, MA: Artech House, 2000), Iddq Testing for CMOS VLSI (Norwood, MA: Artech House, 1995), and Digital Hardware Testing (Norwood, MA: Artech House, 1992). He has also co-edited the first book on Iddq testing Bridging Faults and Iddq Testing (Los Alamitos, CA: IEEE Computer Society Press, 1992). His book System-on-a-Chip: Design and Test is now on the best sellers list of Artech House, has been converted into an e-Book licensed by other press, and is being translated into Chinese. Dr. Rajsuman is a recipient of the IEEE Computer Society’s Golden Core Award.