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Implementation of a Reconfigurable Optical Logic Gate Using a Single I/Q Modulator With Direct Detection Volume 8, Number 3, June 2016 Xianfeng Tang Yaxue Zhai Lu Sun Yiqiao Feng Donghe Zhao Xiaoguang Zhang Lixia Xi Wenbo Zhang

DOI: 10.1109/JPHOT.2016.2550318 1943-0655 Ó 2016 IEEE

IEEE Photonics Journal

Optical Logic Gate Using I/Q Modulator

Implementation of a Reconfigurable Optical Logic Gate Using a Single I/Q Modulator With Direct Detection Xianfeng Tang, Yaxue Zhai, Lu Sun, Yiqiao Feng, Donghe Zhao, Xiaoguang Zhang, Lixia Xi, and Wenbo Zhang State Key Laboratory of Information Photonics and Optical Communications, Beijing University of Posts and Telecommunications, Beijing 100876, China DOI: 10.1109/JPHOT.2016.2550318 1943-0655 Ó 2016 IEEE. Translations and content mining are permitted for academic research only. Personal use is also permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

Manuscript received March 2, 2016; revised March 29, 2016; accepted March 30, 2016. Date of publication April 4, 2016; date of current version April 27, 2016. This work was supported in part by the Fundamental Research Funds for the Central Universities under Grant 2014RC1201; by the Fund of the State Key Laboratory of Information Photonics and Optical Communications (Beijing University of Posts and Telecommunications); and by the National Natural Science Foundation of China under Grant 61571057, Grant 61527820, and Grant 61575082. Corresponding author: X. Tang (e-mail: [email protected]).

Abstract: We propose and investigate a new scheme to realize all-optical logic gates using a single I/Q modulator with direct detection. Both intensity and phase of the optical signal are utilized to represent the four different states of two binary inputs, whereas direct detection is used to map the four states to the corresponding binary output. This structure is very simple and has the potential to reach high speed. All of the basic logic gates can be implemented by adjusting the bias voltages of the two arms, peak–peak voltages of the driving signals, and the phase shift. Experiments are successfully carried out to realize all six basic logic gates at the data rate up to 10 Gb/s with eye diagrams clearly observed. Extinction ratios (ERs) of the output signals are increased for all these logic gates, compared with the original input signals. ER decreases when increasing the data rate from 1 to 10 Gb/s. Up to 24 logic gates can be implemented by using a single I/Q modulator. Index Terms: Optical logic gates, I/Q modulator, direct detection.

1. Introduction Moore’s law has been used to successfully predict the advancement of electronics, as well as that of the digital/electrical signal processing power, over the past few decades. However, in order to sustain that pace of advancement, silicon-based integrated circuit technologies will always require advanced transistors architecture with low power consumption and leakage, which is extremely challenging with CMOS node at 10 nm and below [1]. On the other hand, all-optical signal processing is considered an alternative when it comes to ultrahigh bandwidth parallel computing. Besides, all-optical signal processing techniques are also highly desirable in future large-capacity optical networks to increase the processing speed and avoid inefficient opticalelectrical-optical (O-E-O) conversions [2]–[4]. As the fundamental elements of the all-optical signal processing, optical logic gates are essential for optical computing as well as optical networking in addressing, switching, header recognition, data encoding, regeneration, parity checking and network coding [5]–[7]. Thus, the implementation of different optical logic gate functions have attracted a lot of interest in recent years.

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Recently, several schemes of realizing optical logic gates have been proposed. These schemes can be roughly divided into two categories: schemes based on nonlinear optics and those based on modulators. In the former schemes, highly nonlinear fiber (HNLF) [6], [8]; semiconductor optical amplifier (SOA) [9], [10]; silicon nanowire [11]; and periodically poled lithium niobate (PPLN) [12] are widely used. However, HNLF is hard for photonic integration [13], SOA is short in speed limit and latency [14], and PPLN needs precise temperature control [15]. In the latter schemes, various modulators and interferometers are adopted, which mainly focus on the usage of the intensity information in the past [16], [17]. In this paper, we propose a new method based on a single I/Q modulator which can be easily reconfigured to implement all the basic functions of optical logic gates. Different from the existing methods using modulators, both amplitude and phase of the optical signal are utilized in our method while direct detection (DD) is adopted at the output port. In the scheme, by setting the power of the input signals, the bias levels, and the phase shifts of the modulators (two arms of I/Q modulator), different all-optical logic gates can be realized using the same set of hardware. The proposed method has many advantages, such as high scalability to more logic gates if needed, simple configuration, relaxed requirements on the power difference between the input signals and also the phase shift between the two arms of the modulator. With the bandwidths of commercial modulators and photodetectors reaching 100 GHz, the processing speed of this scheme has the potential to reach the same level [18], [19]. Six basic logic gates (OR, NOR, AND, NAND, XOR, and NOR) are realized in the experiments at the speed up to 10 Gbit/s (using the existing equipments in the lab) with eye diagrams clearly observed. Extinction ratios (ER) of the output signals are increased for all logic gates compared with the original input signals. It is also studied that performance of the logic gates relies on the speed of the signals. When increasing the data rate, ER will decrease. ER is also influenced by positions of the bias voltages and the misalignment time between the electrical signals applied to the two arms. Up to 24 logic gates can be implemented by changing the configurations based on the same devices.

2. Operating Principle For a typical 2 1 logic gate (two inputs and one output), the function is to map the four combinations of the two input signals [(0, 0), (0, 1), (1, 0), (1, 1)] to the desired two output states (0, or 1). Here, we propose a scheme of using the two binary data to modulate both the amplitude and phase of the light to generate the desired four input states, and using direct-detection (DD) to generate the corresponding two output states. Vector addition is the key function to map the four combinations to two states. By adjusting the modulating conditions, different optical logic gates can be realized. The operational principle of the proposed scheme to realize optical logic gates is illustrated in Fig. 1. The optical logic gates consist of a CW (continuous wave) laser, a parallel “I/Q” modulator driven by two input binary data and a PD (photodetector). By setting voltages of the input data, bias voltages of the two parallel Mach–Zehnder modulators (MZMs) and phase difference between the two arms of the parallel “I/Q” modulator, different logic gates are implemented. The output of I/Q modulator can be expressed as Vbias1 Vbias2 Ein ðt Þ j 2V j 2V Eout ¼ j ðVin1 ðt ÞVbias1 Þ e expðjÞþcos ðVin2 ðt ÞVbias2 Þ e cos insert loss 2V 2V 2 10 20 (1) where Ein ðt Þ is the input electrical field of CW light, Vin1 ðtÞ and Vin2 ðtÞ are the two input binary signals, Vbias1 and Vbias2 are the bias voltages of the two MZMs, and is the phase shift generated on the upper arm. From the expression, we can see that the CW light is modulated by the input data both in amplitude and phase. After PD, the light signals are converted into intensity, ! ! which is equivalent to the mathematical operation of jvector1 þ vector2j2 .

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Fig. 1. System schematic diagram and operating principle (AND gate). (a) Constellation after the upper Mach–Zehnder modulator (MZM-I). (b) Constellation after the phase shifter. (c) Constellation after the lower MZM (MZM-Q). (d) Constellation at the output port of the I/Q modulator. ECL: external cavity laser; black dots: “0” and “1” generated on the two arms; purple and blue dots: constellation points generated through vector addition of the black dots.

TABLE 1 Configurations of six basic logic gates

Take AND gate, for example, in which the parameters used is similar with the one to generate an 8-QAM in [20]. The upper MZM is biased at +Quad point and the lower MZM at null point. These two MZMs are driven by two signals with different voltages: MZM-I is driven with a 2 V peak-to-peak signal, while MZM-Q with a 1.4 V swing signal. Constellations at the outputs of the two MZMs are shown in Fig. 1(a) and (c) respectively. By introducing a phase shift of (typical =4) between the two arms, the constellation of MZM-I output signal is rotated by as shown in Fig. 1(b). Constellation of the combined signal is shown in Fig. 1(d). Four states (1–4) are generated within the new coordinate axes (red axes), which looks like an unbalanced 4-QAM. Here, (1, 1), (1, 0), (0, 0), and (0, 1) are represented by constellation points 1 to 4, sequentially. Since direct detection is used, the four points are further mapped to two points in electrical domain (corresponding to the two circles in Fig. 1(d)). Thus, AND gate is realized. In order to obtain other logic gates, we just need to adjust the bias voltages of the two MZMs, the peak-to-peak voltages of the signals and the phase shift between two arms. Table 1 shows the typical configurations of six basic logic gates. In addition, Fig. 2 gives the illustrations of these six logic gates on constellation. From the transmission curve in Fig. 3, we can see that changing the bias point from Vbias to ðVbias þ V Þ, the phase of the output signal will be inverted. This can also be observed from

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Fig. 2. Configurations and illustrations of the (a) gates.


OR,

(b)

XOR,

(c)

AND,

(d)

NOR,

(e)

XNOR,

and (f)

NAND

Fig. 3. Phase inversion of the output signal by changing the bias from Vbias to ðVbias þ V Þ.

formula (1): A phase of will be added to the output signal of MZM when adding V to Vbias . A NOT gate will be realized by simply changing the bias point from +Quad to −Quad. Besides, a series of more complex logic gates can be constructed based on this property, such as A & B. Hence, this simple structure can be reconfigured to realize 24 logic gates with form of (A or A) (&, þ, ", , , )(B or B).

3. Experimental Results and Discussions The experimental setup of our proposed scheme to realize reconfigurable all-optical logic gates is presented in Fig. 4. A tunable external cavity (ECL) laser with line-width smaller than 100 kHz is used as the light source. The output power of ECL is set at 10 dBm. An I/Q modulator with a 3-dB bandwidth of 22 GHz is driven by the two input binary data with required Vpp as shown in Table 1. Bias voltages of the two MZMs and the phase shifter are also selected as required. An arbitrary waveform generator (AWG) is used to generate the two binary data at up to 10 Gbit/s. A wideband oscilloscope (OSC) is used to detect the light and record the waveform. Logic gates

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Fig. 4. Experimental setup of all-optical logic gates.

Fig. 5. Temporal waveforms and eye diagrams of the input signals and output signals of the logic gates.

with supporting data rates of 1, 2, 5, 6, 8, and 10 Gbit/s, respectively, are realized in the experiments. Fig. 5 shows the temporal waveforms and eye diagrams of the input signals and output signals of the logic gates. From the results, we can see that the expected logic gates are successfully realized using our proposed scheme. Compared with the measured extinction ratios (ERs) of two input signals, ERs of the output signals are all increased to as high as 16.45 dB for these six gates. Fig. 6 gives the ER values when increasing data rate from 1 Gbit/s to 10 Gbit/s for XOR gate. With data rate increasing, ER decreases from 14.37 to around 9 dB. In the experiment, one electrical signal DATA and the delayed signal of its inverse DATA are used as the two inputs. The time delay between the two electrical signals is 2.975 ns and the corresponding misalignment is 25 ps. However, for signals at different data rates, the influence of this misalignment

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Fig. 6. ERs at different data rates for the


XOR

gate and typical eye diagrams.

TABLE 2 Delayed bits and misalignment time at different data rates

time varies. The delayed bits and percentages of misalignment time in one bit period are listed in Table 2 at different data rates. As we can see, this misalignment time becomes more obvious in one bit period when the data rate increases. Due to the misalignment between the two electrical signals, performance of logic gates becomes worse dramatically at data rates higher than 5 Gbit/s. Two rising and falling edges can be clearly seen from the eye diagram of signal at 6 Gbit/s in Fig. 6. For signals at data rate of 10 Gbit/s, timing misalignment occupies up to one fourth of the bit period, which will deteriorate the signal significantly. After further adjusting the time delay between the two electrical signals, a clear eye diagram and a relatively high ER are obtained at 10 Gbit/s. ER value changes a lot even at the same data rate, which is dependent on the type of logic gate. To realize desired logic gate, we have five parameters (bias point1, bias point2, Vpp1, Vpp2, and phase shift) to adjust which are constrained by respective logic relation. ER value is also influenced by the setting of these five parameters. As we can see in Fig. 7, the logic gate of “AND” has the lowest ER value as it has two different bias voltages (+Quad and Null points) shown in Table 1. Other logic gates are generally influenced by the required bias points and the phase shift. In addition, measured ER of the logic gate is also influenced by the insert loss. Simulations are carried out for XOR gate and the results are shown in Fig. 8. For a given input power, ER at the output of logic gate is generally limited by the ER of I/Q modulator when the insert loss is low. In the simulations, input power is set as 10 dBm, and ER of I/Q modulator as 20 dB. Noises including shot noise and thermal noise in photodetector are introduced into the measurement of

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Fig. 7. ERs for different logic gates at the data rate of 1 Gb/s and typical eye diagrams.

Fig. 8. ER and BER versus insertion loss of the

XOR

gate.

ER, which slightly influences the value of measured ER. When the insert loss is low, power of “0” is slightly higher than the minimum-detectable power due to the finite ER of I/Q modulator. Both the powers of “0” and “1” fall in proportion when increasing the insert loss. Measured ER will almost remain unchanged with a little bit decrease due to the existence of noise. When the power level of “0” drops to the minimum-detectable power, ER will decrease dramatically when increasing insert loss. Finally, ER will become 0 when the logic gate malfunctions. In this process, signal-to-noise ratio (SNR) will keep falling as the insert loss increases. Therefore, the measured BER will increase from 0 to 1. Based on the principle of the proposed scheme, 18 more logic gates with form of (A or A)(&, þ, ", , , )(B or B) can be further developed and the processing speed can also be increased.

4. Conclusion We propose a new scheme for realizing various all-optical logic gate functions based on a single I/Q modulator. Both amplitude and phase are used to generate the required four input states of

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the logic gates. Direct detection (DD) with a photo detector is adopted to generate the required two output states. This scheme is very simple and convenient to implement up to 24 logic gates with the same structure. It also shows flexibility on choosing the parameters in the setup. Experiments are successfully carried out to realize six basic logic gates at data rates of 1 Gbit/s to 10 Gbit/s. Extinction ratios of the output signals are increased up to 16.45 dB at 1 Gbit/s compared with the input extinction ratios of around 6 dB. Performance of the logic gates is influenced by the misalignment time of the two input signals, bias points and the phase shift. This scheme has the potential to reach very high processing speed, depending on the bandwidth of modulator and photo detector.

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