Low-cost VLSI architecture design for forward quantization of H.264
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Low-cost VLSI architecture design for forward quantization of H.264
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Low-cost VLSI Architecture Design for Forward Quantization of H.264/AVC G.A. Ruiz1 and J.A. Michell Dpto. de Electrónica y Computadores. Facultad de Ciencias Universidad de Cantabria. Avda. de Los Castros s/n. 39005 Santander (SPAIN) ABSTRACT The H.264/AVC (Advanced Video Codec) is the latest standard for video coding. It assumes a scalar forward quantizer performed at the encoder which can be implemented directly in integer arithmetic. An efficient architecture for the computation of forward quantization of H.264/AVC is presented in this paper. It uses a modification of the quantization operation which reduces the arithmetic operations, and a truncated Booth multiplier based on adaptative statistical approach, which reduces the hardware. The JM reference software’s C code has been re-written to analyze the effect of new algorithm and of truncated Booth multiplier. Simulations made up over popular test sequences used in video standardization show the validity of this approach. These results demonstrate that, at low QP, the PSNR is improved between a maximum of +0.81db and a minimum of 0.31db, with a slight increase in the Bit Rate being around 0.8%. Finally, a suitable architecture for VLSI implementation is presented, which reduces in a 26% the area, 32% the power and 21% the critical path delay in comparison with classical implementation. Moreover, it also reduces the area and increase the speed in comparison with architectures presented in references. Keywords: Quantization, H.264
1. INTRODUCTION THE H.264/ is the latest standard for video coding established by the Joint Video Team between ITU-T VCEG and ISO/IEC MPEG1. H.264 presents a number of features different from the existing standards to support various applications. It assumes a scalar forward quantizer performed at the encoder by a simple scale-and-shift formula which can be implemented directly in integer arithmetic. The step size of the quantizer is controlled with the use of a quantization parameter (QP) which supports 52 different values, from 0 to 51, in increments of one. According to the notation in 2, each transform coefficient with value Wij (i,j= 0 to 3) is quantized in a coefficient Zij by the following equation:
(
)
Z ij = Wij ⋅ MFij + F >> qbits sign( Z ij ) = sign( Wij )
(1)
where MFij is the multiplication factor made up of 6x3 arrays of 14-bit positive integers, qbits=15+floor(QP/6), >> indicates a binary shift right and F is a positive number which can be expressed as F=f > qbits“ makes an integer division with truncation of the result toward zero which causes errors for Wij < 0. For example, the integer -3 in a 4-bit two’scomplement representation is 1101. The operation -3 >>2 should be 0, but 1101>>2 gives -1. To resolve this error, 1
